Home
last modified time | relevance | path

Searched full:pll_bypassnl (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/clk/qcom/
H A Dclk-pll.c21 #define PLL_BYPASSNL BIT(1) macro
30 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; in clk_pll_enable()
40 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
41 PLL_BYPASSNL); in clk_pll_enable()
75 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; in clk_pll_disable()
147 u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N; in clk_pll_set_rate()
274 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_sr2_enable()
275 PLL_BYPASSNL); in clk_pll_sr2_enable()
307 u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N; in clk_pll_sr2_set_rate()
H A Dclk-hfpll.c16 #define PLL_BYPASSNL BIT(1) macro
67 regmap_update_bits(regmap, hd->mode_reg, PLL_BYPASSNL, PLL_BYPASSNL); in __clk_hfpll_enable()
105 if (!(mode & (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL))) in clk_hfpll_enable()
122 PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL, 0); in __clk_hfpll_disable()
214 if (mode != (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL)) { in clk_hfpll_init()
241 return mode == (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL); in hfpll_is_enabled()
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dqcom,qcs615-tlmm.yaml86 pll_bypassnl, pll_reset_n, prng_rosc, qdss_cti, qdss_gpio,
H A Dqcom,sm8250-pinctrl.yaml81 pci_e2, phase_flag, pll_bist, pll_bypassnl, pll_clk, pll_reset,
H A Dqcom,sm6115-tlmm.yaml76 pll_bist, pll_bypassnl, pll_reset, prng_rosc, qdss_cti,
H A Dqcom,qcm2290-tlmm.yaml70 pll_bypassnl, pll_reset, prng_rosc, pwm_0, pwm_1, pwm_2, pwm_3,
H A Dqcom,sdm670-tlmm.yaml75 mss_lte, nav_pps, pa_indicator, pci_e0, pci_e1, phase_flag, pll_bist, pll_bypassnl,
H A Dqcom,sc7280-pinctrl.yaml87 pll_bist, pll_bypassnl, pll_clk, pll_reset, pri_mi2s, prng_rosc,
H A Dqcom,sm7150-tlmm.yaml86 pci_e, phase_flag, pll_bist, pll_bypassnl, pll_reset, pri_mi2s,
H A Dqcom,sc8180x-tlmm.yaml82 pci_e2, pci_e3, phase_flag, pll_bist, pll_bypassnl, pll_reset,
H A Dqcom,sm6375-tlmm.yaml86 phase_flag9, pll_bist, pll_bypassnl, pll_clk, pll_reset,
H A Dqcom,sm6350-tlmm.yaml86 pll_bist, pll_bypassnl, pll_reset, prng_rosc, qdss_cti, qdss_gpio, qdss_gpio0,
H A Dqcom,sdx65-tlmm.yaml68 cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b,