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/linux/Documentation/devicetree/bindings/sound/
H A Dnvidia,tegra-audio-graph-card.yaml32 - const: pll_a
77 clock-names = "pll_a", "plla_out0";
H A Dnvidia,tegra-audio-trimslice.yaml32 clock-names = "pll_a", "pll_a_out0", "mclk";
H A Dnvidia,tegra-audio-alc5632.yaml73 clock-names = "pll_a", "pll_a_out0", "mclk";
H A Dnvidia,tegra-audio-wm9712.yaml75 clock-names = "pll_a", "pll_a_out0", "mclk";
H A Dnvidia,tegra-audio-sgtl5000.yaml66 clock-names = "pll_a", "pll_a_out0", "mclk";
H A Dnvidia,tegra-audio-wm8753.yaml78 clock-names = "pll_a", "pll_a_out0", "mclk";
H A Dnvidia,tegra-audio-rt5640.yaml83 clock-names = "pll_a", "pll_a_out0", "mclk";
H A Dnvidia,tegra-audio-rt5631.yaml84 clock-names = "pll_a", "pll_a_out0", "mclk";
H A Dnvidia,tegra-audio-max98090.yaml96 clock-names = "pll_a", "pll_a_out0", "mclk";
H A Dnvidia,tegra-audio-max9808x.yaml89 clock-names = "pll_a", "pll_a_out0", "mclk";
H A Dnvidia,tegra-audio-rt5677.yaml99 clock-names = "pll_a", "pll_a_out0", "mclk";
H A Dnvidia,tegra-audio-common.yaml22 - const: pll_a
H A Dnvidia,tegra-audio-wm8903.yaml92 clock-names = "pll_a", "pll_a_out0", "mclk";
/linux/sound/soc/tegra/
H A Dtegra_audio_graph_card.c179 priv->clk_plla = devm_clk_get(card->dev, "pll_a"); in tegra_audio_graph_card_probe()
181 dev_err(card->dev, "Can't retrieve clk pll_a\n"); in tegra_audio_graph_card_probe()
H A Dtegra_asoc_machine.c342 dev_err(card->dev, "Can't set pll_a rate: %d\n", err); in tegra_machine_hw_params()
532 machine->clk_pll_a = devm_clk_get(dev, "pll_a"); in tegra_asoc_machine_probe()
534 dev_err(dev, "Can't retrieve clk pll_a\n"); in tegra_asoc_machine_probe()
595 dev_err(dev, "Can't set pll_a rate: %d\n", err); in tegra_asoc_machine_probe()
/linux/drivers/gpu/drm/i915/display/
H A Ddvo_ns2501.c209 u8 pll_a; /* PLL configuration, register A, 1B */ member
236 .pll_a = 17,
256 .pll_a = 25,
275 .pll_a = 11,
613 ns2501_writeb(dvo, NS2501_REG1B, conf->pll_a); in ns2501_mode_set()
/linux/include/dt-bindings/clock/
H A Dsunplus,sp7021-clkc.h76 #define PLL_A 64 macro
/linux/drivers/clk/
H A Dclk-sp7021.c335 /*********************************** PLL_A ***********************************/
630 hws[PLL_A] = sp_pll_register(dev, "plla", &pd_ext, PLLA_CTL, in sp7021_clk_probe()
632 if (IS_ERR(hws[PLL_A])) in sp7021_clk_probe()
633 return PTR_ERR(hws[PLL_A]); in sp7021_clk_probe()
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra20-plutux.dts60 clock-names = "pll_a", "pll_a_out0", "mclk";
H A Dtegra20-tec.dts69 clock-names = "pll_a", "pll_a_out0", "mclk";
H A Dtegra20-medcom-wide.dts95 clock-names = "pll_a", "pll_a_out0", "mclk";
H A Dtegra20-trimslice.dts495 clock-names = "pll_a", "pll_a_out0", "mclk";
/linux/drivers/clk/tegra/
H A Dclk-tegra-audio.c193 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a", in tegra_audio_clk_init()
H A Dclk-tegra-periph.c562 "pll_m", "pll_c", "pll_p", "pll_a", "pll_c2", "pll_c3", "clk_m"
817 GATE("pll_a_out_adsp", "pll_a", 188, 0, tegra_clk_pll_a_out_adsp, 0),
818 GATE("pll_a_out0_out_adsp", "pll_a", 188, 0, tegra_clk_pll_a_out0_out_adsp, 0),
H A Dclk-tegra20.c433 { .con_id = "pll_a", .dt_id = TEGRA20_CLK_PLL_A },
678 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, NULL, 0, in tegra20_pll_init()
683 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a", in tegra20_pll_init()

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