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/linux/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun4i-a10-pll5-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll5-clk.yaml#
23 const: allwinner,sun4i-a10-pll5-clk
47 compatible = "allwinner,sun4i-a10-pll5-clk";
H A Dallwinner,sun4i-a10-mbus-clk.yaml50 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
59 clocks = <&osc24M>, <&pll6 1>, <&pll5>;
H A Dallwinner,sun4i-a10-display-clk.yaml53 clocks = <&pll3>, <&pll7>, <&pll5 1>;
H A Dallwinner,sun4i-a10-mmc-clk.yaml71 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
H A Dallwinner,sun4i-a10-mod0-clk.yaml67 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
/linux/drivers/clk/renesas/
H A Dr8a779f0-cpg-mssr.c64 DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
179 * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
191 /* EXTAL div PLL1 mult/div PLL5 mult/div OSC prediv */
H A Dr8a779a0-cpg-mssr.c77 DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
251 * MD EXTAL PLL1 PLL20 PLL30 PLL4 PLL5 OSC
262 /* EXTAL div PLL1 mult/div PLL5 mult/div OSC prediv */
H A Drzg2l-cpg.c142 * @mux_dsi_div_params: pll5 mux and dsi div parameters
834 * OSC --> PLL5 --> FOUTPOSTDIV-->| in rzg2l_cpg_sipll5_set_rate()
839 * rate and the pll5 parameters for generating FOUTPOSTDIV. It propagates in rzg2l_cpg_sipll5_set_rate()
842 * OSC --> PLL5 --> FOUTPOSTDIV in rzg2l_cpg_sipll5_set_rate()
852 /* Put PLL5 into standby mode */ in rzg2l_cpg_sipll5_set_rate()
857 dev_err(priv->dev, "failed to release pll5 lock"); in rzg2l_cpg_sipll5_set_rate()
884 dev_err(priv->dev, "failed to lock pll5"); in rzg2l_cpg_sipll5_set_rate()
H A Dr9a07g043-cpg.c122 DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1),
H A Dr9a07g044-cpg.c134 DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1),
/linux/Documentation/devicetree/bindings/mips/
H A Dmscc.txt31 configuration and status of PLL5, RCOMP, SyncE, SerDes configurations and
/linux/drivers/clk/mmp/
H A Dclk-of-pxa1928.c41 {0, "pll5", NULL, 0, 1248000000},
146 static const char *sdh_parent_names[] = {"pll1_624", "pll5p", "pll5", "pll1_416"};
/linux/drivers/clk/sunxi/
H A Dclk-sunxi.c195 * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
196 * PLL5 rate is calculated as follows
1006 clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT; in sunxi_divs_clk_setup()
1103 CLK_OF_DECLARE(sun4i_pll5, "allwinner,sun4i-a10-pll5-clk",
H A Dclk-factors.c195 * some factor clocks, such as pll5 and pll6, may have multiple in __sunxi_factors_register()
/linux/include/dt-bindings/clock/
H A Dqcom,gcc-msm8660.h258 #define PLL5 249 macro
H A Dqcom,gcc-mdm9615.h291 #define PLL5 281 macro
H A Dqcom,gcc-msm8960.h289 #define PLL5 281 macro
/linux/drivers/clk/imx/
H A Dclk-imx6sl.c68 static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
221 hws[IMX6SL_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f); in imx6sl_clocks_init()
436 /* set PLL5 video as lcdif pix parent clock */ in imx6sl_clocks_init()
H A Dclk-imx6sll.c27 static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
127 …hws[IMX6SLL_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x… in imx6sll_clocks_init()
H A Dclk-vf610.c81 static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
223 clk[VF610_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll5", "pll5_bypass_src", PLL5_CTRL, 0x3); in vf610_clocks_init()
H A Dclk-imx6q.c89 static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
415 /* Make sure PLL5 is disabled */ in disable_anatop_clocks()
486 hws[IMX6QDL_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f); in imx6q_clocks_init()
H A Dclk-imx6ul.c26 static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
167 hws[IMX6UL_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f); in imx6ul_clocks_init()
H A Dclk-imx6sx.c81 static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
165 hws[IMX6SX_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f); in imx6sx_clocks_init()
/linux/sound/soc/codecs/
H A Dwm8804.c40 { 7, 0x16 }, /* R7 - PLL5 */
/linux/drivers/ptp/
H A Dptp_clockmatrix.c577 /* PLL5 can have OUT8 as second additional output. */ in _sync_pll_output()

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