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/linux/drivers/clk/mediatek/
H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
16 #include "clk-pll.h"
25 #define CON0_ISO_EN BIT(1)
35 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); in mtk_pll_is_prepared() local
37 return (readl(pll->en_addr) & BIT(pll->data->pll_en_bit)) != 0; in mtk_pll_is_prepared()
42 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); in mtk_pll_fenc_is_prepared() local
44 return !!(readl(pll->fenc_addr) & BIT(pll->data->fenc_sta_bit)); in mtk_pll_fenc_is_prepared()
47 static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, in __mtk_pll_recalc_rate() argument
50 int pcwbits = pll->data->pcwbits; in __mtk_pll_recalc_rate()
[all …]
/linux/drivers/clk/tegra/
H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
31 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
34 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
37 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
159 #define PLLSS_EN_DITHER 1
196 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1)
207 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
230 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
231 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dintel_cx0_phy.c1 // SPDX-License-Identifier: MIT
34 #define INTEL_CX0_LANE1 BIT(1)
48 if (display->platform.pantherlake && phy < PHY_C) in intel_encoder_is_c10phy()
51 if ((display->platform.lunarlake || display->platform.meteorlake) && phy < PHY_C) in intel_encoder_is_c10phy()
60 hweight8(lane_mask) != 1)) in lane_mask_to_lane()
74 * In DP-alt with pin assignment D, only PHY lane 0 is owned in intel_cx0_get_owned_lane_mask()
75 * by display and lane 1 is owned by USB. in intel_cx0_get_owned_lane_mask()
87 drm_WARN_ON(display->drm, !enabled); in assert_dc_off()
97 XELPDP_PORT_MSGBUS_TIMER(display, encoder->port, lane), in intel_cx0_program_msgbus_timer()
139 XELPDP_PORT_P2M_MSGBUS_STATUS(display, encoder->port, lane), in intel_clear_response_ready_flag()
[all …]
/linux/drivers/video/fbdev/aty/
H A Dmach64_ct.c1 // SPDX-License-Identifier: GPL-2.0
18 static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll);
19 static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll);
20 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll);
21 static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll);
51 * CLK = ----------------------
62 * are 1,2,4,8 and for some clocks other values are available too.
68 * XCLK The clock rate of the on-chip memory
75 * SCLK Multi-purpose clock
77 * - MCLK and XCLK use the same FB_DIV
[all …]
/linux/drivers/clk/rockchip/
H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
14 #include <linux/clk-provider.h>
51 struct rockchip_clk_pll *pll, unsigned long rate) in rockchip_get_pll_settings() argument
53 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_get_pll_settings()
56 for (i = 0; i < pll->rate_count; i++) { in rockchip_get_pll_settings()
67 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_pll_determine_rate() local
68 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_pll_determine_rate()
72 for (i = 0; i < pll->rate_count; i++) { in rockchip_pll_determine_rate()
73 if (req->rate >= rate_table[i].rate) { in rockchip_pll_determine_rate()
[all …]
/linux/drivers/clk/baikal-t1/
H A Dccu-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Baikal-T1 CCU PLL interface driver
12 #define pr_fmt(fmt) "bt1-ccu-pll: " fmt
20 #include <linux/clk-provider.h>
29 #include "ccu-pll.h"
33 #define CCU_PLL_CTL_RST BIT(1)
49 ((CCU_PLL_CTL_CLKR_MASK >> CCU_PLL_CTL_CLKR_FLD) + 1)
51 ((CCU_PLL_CTL_CLKF_MASK >> (CCU_PLL_CTL_CLKF_FLD + 1)) + 1)
53 ((CCU_PLL_CTL_CLKOD_MASK >> CCU_PLL_CTL_CLKOD_FLD) + 1)
55 ((CCU_PLL_CTL1_BWADJ_MASK >> CCU_PLL_CTL1_BWADJ_FLD) + 1)
[all …]
/linux/arch/mips/ath79/
H A Dclock.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
17 #include <linux/clk-provider.h>
20 #include <dt-bindings/clock/ath79-clk.h>
24 #include <asm/mach-ath79/ath79.h>
25 #include <asm/mach-ath79/ar71xx_regs.h>
99 u32 pll; in ar71xx_clocks_init() local
105 pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG); in ar71xx_clocks_init()
107 div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1; in ar71xx_clocks_init()
110 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; in ar71xx_clocks_init()
[all …]
/linux/drivers/clk/bcm/
H A Dclk-iproc-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include "clk-iproc.h"
19 * PLL MACRO_SELECT modes 0 to 5 choose pre-calculated PLL output frequencies
20 * from a look-up table. Mode 7 allows user to manipulate PLL clock dividers
24 /* number of delay loops waiting for PLL to lock */
75 struct iproc_pll *pll; member
90 return -EINVAL; in pll_calc_param()
92 residual = target_rate - (ndiv_int * parent_rate); in pll_calc_param()
102 vco_out->ndiv_int = ndiv_int; in pll_calc_param()
[all …]
H A Dclk-iproc-armpll.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
13 #include "clk-iproc.h"
66 static unsigned int __get_fid(struct iproc_arm_pll *pll) in __get_fid() argument
71 val = readl(pll->base + IPROC_CLK_ARM_DIV_OFFSET); in __get_fid()
72 if (val & (1 << IPROC_CLK_ARM_DIV_PLL_SELECT_OVERRIDE_SHIFT)) in __get_fid()
80 val = readl(pll->base + IPROC_CLK_POLICY_FREQ_OFFSET); in __get_fid()
84 val = readl(pll->base + IPROC_CLK_POLICY_DBG_OFFSET); in __get_fid()
88 pr_debug("%s: fid override %u->%u\n", __func__, fid, in __get_fid()
101 * - 25 MHz Crystal
[all …]
/linux/drivers/clk/sprd/
H A Dpll.c1 // SPDX-License-Identifier: GPL-2.0
3 // Spreadtrum pll clock driver
13 #include "pll.h"
18 #define pindex(pll, member) \ argument
19 (pll->factors[member].shift / (8 * sizeof(pll->regs_num)))
21 #define pshift(pll, member) \ argument
22 (pll->factors[member].shift % (8 * sizeof(pll->regs_num)))
24 #define pwidth(pll, member) \ argument
25 pll->factors[member].width
27 #define pmask(pll, member) \ argument
[all …]
/linux/drivers/clk/sophgo/
H A Dclk-cv18xx-pll.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
11 #include "clk-cv18xx-pll.h"
36 struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw); in ipll_recalc_rate() local
39 value = readl(pll->common.base + pll->pll_reg); in ipll_recalc_rate()
58 for_each_pll_limit_range(pre, &limit->pre_div) { in ipll_find_rate()
59 for_each_pll_limit_range(div, &limit->div) { in ipll_find_rate()
60 for_each_pll_limit_range(post, &limit->post_div) { in ipll_find_rate()
66 if ((trate - tmp) < (trate - best_rate)) { in ipll_find_rate()
85 return -EINVAL; in ipll_find_rate()
[all …]
/linux/drivers/clk/qcom/
H A Dclk-alpha-pll.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2021, 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
9 #include <linux/clk-provider.h>
13 #include "clk-alpha-pll.h"
16 #define PLL_MODE(p) ((p)->offset + 0x0)
18 # define PLL_BYPASSNL BIT(1)
36 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
37 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
38 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
39 #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
[all …]
H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
17 #include "clk-pll.h"
21 #define PLL_BYPASSNL BIT(1)
26 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable() local
31 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable()
39 /* Disable PLL bypass mode. */ in clk_pll_enable()
40 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
47 * de-asserting the reset. Delay 10us just to be safe. in clk_pll_enable()
51 /* De-assert active-low PLL reset. */ in clk_pll_enable()
[all …]
/linux/drivers/clk/at91/
H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
15 #define PLL_STATUS_MASK(id) (1 << (1 + (id)))
20 #define PLL_MUL(reg, layout) (((reg) >> (layout)->mul_shift) & \
21 (layout)->mul_mask)
23 #define PLL_MUL_MASK(layout) ((layout)->mul_mask)
24 #define PLL_MUL_MAX(layout) (PLL_MUL_MASK(layout) + 1)
30 #define PLL_MAX_ID 1
52 return status & PLL_STATUS_MASK(id) ? 1 : 0; in clk_pll_ready()
57 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_prepare() local
[all …]
/linux/drivers/gpu/drm/sprd/
H A Dmegacores_pll.c1 // SPDX-License-Identifier: GPL-2.0
16 #define H 1
18 #define DATA 1
22 #define AVERAGE(a, b) (min(a, b) + abs((b) - (a)) / 2)
30 static int dphy_calc_pll_param(struct dphy_pll *pll) in dphy_calc_pll_param() argument
38 pll->potential_fvco = pll->freq / khz; in dphy_calc_pll_param()
39 pll->ref_clk = PHY_REF_CLK / khz; in dphy_calc_pll_param()
42 if (pll->potential_fvco >= VCO_BAND_LOW && in dphy_calc_pll_param()
43 pll->potential_fvco <= VCO_BAND_HIGH) { in dphy_calc_pll_param()
44 pll->fvco = pll->potential_fvco; in dphy_calc_pll_param()
[all …]
/linux/drivers/gpu/drm/omapdrm/dss/
H A Dvideo-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
18 struct dss_pll pll; member
30 REG_MOD(vpll->clkctrl_base, 1, 14, 14); /* CIO_CLK_ICG */ in dss_dpll_enable_scp_clk()
35 REG_MOD(vpll->clkctrl_base, 0, 14, 14); /* CIO_CLK_ICG */ in dss_dpll_disable_scp_clk()
40 REG_MOD(vpll->clkctrl_base, 2, 31, 30); /* PLL_POWER_ON_ALL */ in dss_dpll_power_enable()
43 * DRA7x PLL CTRL's PLL_PWR_STATUS seems to always return 0, in dss_dpll_power_enable()
46 msleep(1); in dss_dpll_power_enable()
51 REG_MOD(vpll->clkctrl_base, 0, 31, 30); /* PLL_POWER_OFF */ in dss_dpll_power_disable()
54 static int dss_video_pll_enable(struct dss_pll *pll) in dss_video_pll_enable() argument
[all …]
H A Dpll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
6 #define DSS_SUBSYS_NAME "PLL"
28 int dss_pll_register(struct dss_device *dss, struct dss_pll *pll) in dss_pll_register() argument
32 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { in dss_pll_register()
33 if (!dss->plls[i]) { in dss_pll_register()
34 dss->plls[i] = pll; in dss_pll_register()
35 pll->dss = dss; in dss_pll_register()
40 return -EBUSY; in dss_pll_register()
43 void dss_pll_unregister(struct dss_pll *pll) in dss_pll_unregister() argument
[all …]
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Dvideo-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
20 struct dss_pll pll; member
32 REG_MOD(vpll->clkctrl_base, 1, 14, 14); /* CIO_CLK_ICG */ in dss_dpll_enable_scp_clk()
37 REG_MOD(vpll->clkctrl_base, 0, 14, 14); /* CIO_CLK_ICG */ in dss_dpll_disable_scp_clk()
42 REG_MOD(vpll->clkctrl_base, 2, 31, 30); /* PLL_POWER_ON_ALL */ in dss_dpll_power_enable()
45 * DRA7x PLL CTRL's PLL_PWR_STATUS seems to always return 0, in dss_dpll_power_enable()
48 msleep(1); in dss_dpll_power_enable()
53 REG_MOD(vpll->clkctrl_base, 0, 31, 30); /* PLL_POWER_OFF */ in dss_dpll_power_disable()
56 static int dss_video_pll_enable(struct dss_pll *pll) in dss_video_pll_enable() argument
58 struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll); in dss_video_pll_enable()
[all …]
H A Dpll.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #define DSS_SUBSYS_NAME "PLL"
30 int dss_pll_register(struct dss_pll *pll) in dss_pll_register() argument
36 dss_plls[i] = pll; in dss_pll_register()
41 return -EBUSY; in dss_pll_register()
44 void dss_pll_unregister(struct dss_pll *pll) in dss_pll_unregister() argument
49 if (dss_plls[i] == pll) { in dss_pll_unregister()
61 if (dss_plls[i] && strcmp(dss_plls[i]->name, name) == 0) in dss_pll_find()
68 int dss_pll_enable(struct dss_pll *pll) in dss_pll_enable() argument
72 r = clk_prepare_enable(pll->clkin); in dss_pll_enable()
[all …]
/linux/drivers/clk/imx/
H A Dclk-sscg-pll.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 * Documentation for this SCCG pll can be found at:
8 * https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf#page=834
11 #include <linux/clk-provider.h>
21 /* PLL CFGs */
30 #define PLL_DIVQ_MASK GENMASK(6, 1)
36 /* These are the specification limits for the SSCG PLL */
98 static int clk_sscg_pll_wait_lock(struct clk_sscg_pll *pll) in clk_sscg_pll_wait_lock() argument
102 val = readl_relaxed(pll->base + PLL_CFG0); in clk_sscg_pll_wait_lock()
106 return readl_poll_timeout(pll->base, val, val & PLL_LOCK_MASK, in clk_sscg_pll_wait_lock()
[all …]
H A Dclk-pllv1.c1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/clk-provider.h>
12 #define MFN_SIGN (BIT(MFN_BITS - 1))
13 #define MFN_MASK (MFN_SIGN - 1)
16 * struct clk_pllv1 - IMX PLLv1 clock descriptor
19 * @base: base address of pll registers
22 * PLL clock version 1, found on i.MX1/21/25/27/31/35
32 static inline bool is_imx1_pllv1(struct clk_pllv1 *pll) in is_imx1_pllv1() argument
34 return pll->type == IMX_PLLV1_IMX1; in is_imx1_pllv1()
37 static inline bool is_imx21_pllv1(struct clk_pllv1 *pll) in is_imx21_pllv1() argument
[all …]
/linux/drivers/clk/mxs/
H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
14 * struct clk_pll - mxs pll clock
15 * @hw: clk_hw for the pll
16 * @base: base address of the pll
18 * @rate: the clock rate of the pll
20 * The mxs pll is a fixed rate clock with power and gate control,
34 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_prepare() local
36 writel_relaxed(1 << pll->power, pll->base + SET); in clk_pll_prepare()
45 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_unprepare() local
[all …]
/linux/drivers/clk/nuvoton/
H A Dclk-ma35d1-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Chi-Fang Li <cfli0@nuvoton.com>
8 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
18 #include "clk-ma35d1.h"
20 /* PLL frequency limits */
22 #define PLL_FREF_MIN_FREQ (1 * HZ_PER_MHZ)
36 /* bit fields for REG_CLK_PLL0CTL0, which is SMIC PLL design */
49 #define PLL_CTL1_BP BIT(1)
54 #define INDIV_MIN 1
[all …]
/linux/drivers/clk/x86/
H A Dclk-cgu-pll.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020-2022 MaxLinear, Inc.
9 #include <linux/clk-provider.h>
15 #include "clk-cgu.h"
42 struct lgm_clk_pll *pll = to_lgm_clk_pll(hw); in lgm_pll_recalc_rate() local
45 mult = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 0, 12); in lgm_pll_recalc_rate()
46 div = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 18, 6); in lgm_pll_recalc_rate()
47 frac = lgm_get_clk_val(pll->membase, pll->reg, 2, 24); in lgm_pll_recalc_rate()
49 if (pll->type == TYPE_LJPLL) in lgm_pll_recalc_rate()
57 struct lgm_clk_pll *pll = to_lgm_clk_pll(hw); in lgm_pll_is_enabled() local
[all …]
/linux/drivers/clk/st/
H A Dclkgen-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include <linux/clk-provider.h>
24 * PLL configuration register bits for PLL3200 C32
35 * PLL configuration register bits for PLL4600 C28
82 .num_odfs = 1,
93 { .name = "clk-s-a0-pll-odf-0", },
102 { .name = "clk-s-c0-pll0-odf-0", },
117 .num_odfs = 1,
128 { .name = "clk-s-c0-pll1-odf-0", },
143 .num_odfs = 1,
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