1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
16 #include "clk-pll.h"
25 #define CON0_ISO_EN		BIT(1)
35 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);  in mtk_pll_is_prepared()  local
37 	return (readl(pll->en_addr) & BIT(pll->data->pll_en_bit)) != 0;  in mtk_pll_is_prepared()
42 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);  in mtk_pll_fenc_is_prepared()  local
44 	return !!(readl(pll->fenc_addr) & BIT(pll->data->fenc_sta_bit));  in mtk_pll_fenc_is_prepared()
47 static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,  in __mtk_pll_recalc_rate()  argument
50 	int pcwbits = pll->data->pcwbits;  in __mtk_pll_recalc_rate()
56 	/* The fractional part of the PLL divider. */  in __mtk_pll_recalc_rate()
57 	ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;  in __mtk_pll_recalc_rate()
59 		pcwfbits = pcwbits - ibits;  in __mtk_pll_recalc_rate()
63 	if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0)))  in __mtk_pll_recalc_rate()
64 		c = 1;  in __mtk_pll_recalc_rate()
71 	return ((unsigned long)vco + postdiv - 1) / postdiv;  in __mtk_pll_recalc_rate()
74 static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll)  in __mtk_pll_tuner_enable()  argument
78 	if (pll->tuner_en_addr) {  in __mtk_pll_tuner_enable()
79 		r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);  in __mtk_pll_tuner_enable()
80 		writel(r, pll->tuner_en_addr);  in __mtk_pll_tuner_enable()
81 	} else if (pll->tuner_addr) {  in __mtk_pll_tuner_enable()
82 		r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;  in __mtk_pll_tuner_enable()
83 		writel(r, pll->tuner_addr);  in __mtk_pll_tuner_enable()
87 static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll)  in __mtk_pll_tuner_disable()  argument
91 	if (pll->tuner_en_addr) {  in __mtk_pll_tuner_disable()
92 		r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);  in __mtk_pll_tuner_disable()
93 		writel(r, pll->tuner_en_addr);  in __mtk_pll_tuner_disable()
94 	} else if (pll->tuner_addr) {  in __mtk_pll_tuner_disable()
95 		r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;  in __mtk_pll_tuner_disable()
96 		writel(r, pll->tuner_addr);  in __mtk_pll_tuner_disable()
100 static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,  in mtk_pll_set_rate_regs()  argument
106 	__mtk_pll_tuner_disable(pll);  in mtk_pll_set_rate_regs()
109 	val = readl(pll->pd_addr);  in mtk_pll_set_rate_regs()
110 	val &= ~(POSTDIV_MASK << pll->data->pd_shift);  in mtk_pll_set_rate_regs()
111 	val |= (ffs(postdiv) - 1) << pll->data->pd_shift;  in mtk_pll_set_rate_regs()
114 	if (pll->pd_addr != pll->pcw_addr) {  in mtk_pll_set_rate_regs()
115 		writel(val, pll->pd_addr);  in mtk_pll_set_rate_regs()
116 		val = readl(pll->pcw_addr);  in mtk_pll_set_rate_regs()
120 	val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1,  in mtk_pll_set_rate_regs()
121 			pll->data->pcw_shift);  in mtk_pll_set_rate_regs()
122 	val |= pcw << pll->data->pcw_shift;  in mtk_pll_set_rate_regs()
123 	writel(val, pll->pcw_addr);  in mtk_pll_set_rate_regs()
124 	chg = readl(pll->pcw_chg_addr) |  in mtk_pll_set_rate_regs()
125 	      BIT(pll->data->pcw_chg_bit ? : PCW_CHG_BIT);  in mtk_pll_set_rate_regs()
126 	writel(chg, pll->pcw_chg_addr);  in mtk_pll_set_rate_regs()
127 	if (pll->tuner_addr)  in mtk_pll_set_rate_regs()
128 		writel(val + 1, pll->tuner_addr);  in mtk_pll_set_rate_regs()
131 	__mtk_pll_tuner_enable(pll);  in mtk_pll_set_rate_regs()
137  * mtk_pll_calc_values - calculate good values for a given input frequency.
138  * @pll:	The pll
145 void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,  in mtk_pll_calc_values()  argument
148 	unsigned long fmin = pll->data->fmin ? pll->data->fmin : (1000 * MHZ);  in mtk_pll_calc_values()
149 	const struct mtk_pll_div_table *div_table = pll->data->div_table;  in mtk_pll_calc_values()
154 	if (freq > pll->data->fmax)  in mtk_pll_calc_values()
155 		freq = pll->data->fmax;  in mtk_pll_calc_values()
161 		for (val = 0; div_table[val + 1].freq != 0; val++) {  in mtk_pll_calc_values()
162 			if (freq > div_table[val + 1].freq)  in mtk_pll_calc_values()
165 		*postdiv = 1 << val;  in mtk_pll_calc_values()
168 			*postdiv = 1 << val;  in mtk_pll_calc_values()
175 	ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;  in mtk_pll_calc_values()
176 	_pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits);  in mtk_pll_calc_values()
185 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);  in mtk_pll_set_rate()  local
189 	mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate);  in mtk_pll_set_rate()
190 	mtk_pll_set_rate_regs(pll, pcw, postdiv);  in mtk_pll_set_rate()
197 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);  in mtk_pll_recalc_rate()  local
201 	postdiv = (readl(pll->pd_addr) >> pll->data->pd_shift) & POSTDIV_MASK;  in mtk_pll_recalc_rate()
202 	postdiv = 1 << postdiv;  in mtk_pll_recalc_rate()
204 	pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift;  in mtk_pll_recalc_rate()
205 	pcw &= GENMASK(pll->data->pcwbits - 1, 0);  in mtk_pll_recalc_rate()
207 	return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv);  in mtk_pll_recalc_rate()
212 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);  in mtk_pll_determine_rate()  local
216 	mtk_pll_calc_values(pll, &pcw, &postdiv, req->rate,  in mtk_pll_determine_rate()
217 			    req->best_parent_rate);  in mtk_pll_determine_rate()
219 	req->rate = __mtk_pll_recalc_rate(pll, req->best_parent_rate, pcw,  in mtk_pll_determine_rate()
227 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);  in mtk_pll_prepare()  local
230 	r = readl(pll->pwr_addr) | CON0_PWR_ON;  in mtk_pll_prepare()
231 	writel(r, pll->pwr_addr);  in mtk_pll_prepare()
232 	udelay(1);  in mtk_pll_prepare()
234 	r = readl(pll->pwr_addr) & ~CON0_ISO_EN;  in mtk_pll_prepare()
235 	writel(r, pll->pwr_addr);  in mtk_pll_prepare()
236 	udelay(1);  in mtk_pll_prepare()
238 	r = readl(pll->en_addr) | BIT(pll->data->pll_en_bit);  in mtk_pll_prepare()
239 	writel(r, pll->en_addr);  in mtk_pll_prepare()
241 	if (pll->data->en_mask) {  in mtk_pll_prepare()
242 		r = readl(pll->base_addr + REG_CON0) | pll->data->en_mask;  in mtk_pll_prepare()
243 		writel(r, pll->base_addr + REG_CON0);  in mtk_pll_prepare()
246 	__mtk_pll_tuner_enable(pll);  in mtk_pll_prepare()
250 	if (pll->data->flags & HAVE_RST_BAR) {  in mtk_pll_prepare()
251 		r = readl(pll->base_addr + REG_CON0);  in mtk_pll_prepare()
252 		r |= pll->data->rst_bar_mask;  in mtk_pll_prepare()
253 		writel(r, pll->base_addr + REG_CON0);  in mtk_pll_prepare()
261 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);  in mtk_pll_unprepare()  local
264 	if (pll->data->flags & HAVE_RST_BAR) {  in mtk_pll_unprepare()
265 		r = readl(pll->base_addr + REG_CON0);  in mtk_pll_unprepare()
266 		r &= ~pll->data->rst_bar_mask;  in mtk_pll_unprepare()
267 		writel(r, pll->base_addr + REG_CON0);  in mtk_pll_unprepare()
270 	__mtk_pll_tuner_disable(pll);  in mtk_pll_unprepare()
272 	if (pll->data->en_mask) {  in mtk_pll_unprepare()
273 		r = readl(pll->base_addr + REG_CON0) & ~pll->data->en_mask;  in mtk_pll_unprepare()
274 		writel(r, pll->base_addr + REG_CON0);  in mtk_pll_unprepare()
277 	r = readl(pll->en_addr) & ~BIT(pll->data->pll_en_bit);  in mtk_pll_unprepare()
278 	writel(r, pll->en_addr);  in mtk_pll_unprepare()
280 	r = readl(pll->pwr_addr) | CON0_ISO_EN;  in mtk_pll_unprepare()
281 	writel(r, pll->pwr_addr);  in mtk_pll_unprepare()
283 	r = readl(pll->pwr_addr) & ~CON0_PWR_ON;  in mtk_pll_unprepare()
284 	writel(r, pll->pwr_addr);  in mtk_pll_unprepare()
289 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);  in mtk_pll_prepare_setclr()  local
291 	writel(BIT(pll->data->pll_en_bit), pll->en_set_addr);  in mtk_pll_prepare_setclr()
293 	/* Wait 20us after enable for the PLL to stabilize */  in mtk_pll_prepare_setclr()
301 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);  in mtk_pll_unprepare_setclr()  local
303 	writel(BIT(pll->data->pll_en_bit), pll->en_clr_addr);  in mtk_pll_unprepare_setclr()
325 struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,  in mtk_clk_register_pll_ops()  argument
334 	pll->base_addr = base + data->reg;  in mtk_clk_register_pll_ops()
335 	pll->pwr_addr = base + data->pwr_reg;  in mtk_clk_register_pll_ops()
336 	pll->pd_addr = base + data->pd_reg;  in mtk_clk_register_pll_ops()
337 	pll->pcw_addr = base + data->pcw_reg;  in mtk_clk_register_pll_ops()
338 	if (data->pcw_chg_reg)  in mtk_clk_register_pll_ops()
339 		pll->pcw_chg_addr = base + data->pcw_chg_reg;  in mtk_clk_register_pll_ops()
341 		pll->pcw_chg_addr = pll->base_addr + REG_CON1;  in mtk_clk_register_pll_ops()
342 	if (data->tuner_reg)  in mtk_clk_register_pll_ops()
343 		pll->tuner_addr = base + data->tuner_reg;  in mtk_clk_register_pll_ops()
344 	if (data->tuner_en_reg || data->tuner_en_bit)  in mtk_clk_register_pll_ops()
345 		pll->tuner_en_addr = base + data->tuner_en_reg;  in mtk_clk_register_pll_ops()
346 	if (data->en_reg)  in mtk_clk_register_pll_ops()
347 		pll->en_addr = base + data->en_reg;  in mtk_clk_register_pll_ops()
349 		pll->en_addr = pll->base_addr + REG_CON0;  in mtk_clk_register_pll_ops()
350 	if (data->en_set_reg)  in mtk_clk_register_pll_ops()
351 		pll->en_set_addr = base + data->en_set_reg;  in mtk_clk_register_pll_ops()
352 	if (data->en_clr_reg)  in mtk_clk_register_pll_ops()
353 		pll->en_clr_addr = base + data->en_clr_reg;  in mtk_clk_register_pll_ops()
354 	pll->hw.init = &init;  in mtk_clk_register_pll_ops()
355 	pll->data = data;  in mtk_clk_register_pll_ops()
357 	pll->fenc_addr = base + data->fenc_sta_ofs;  in mtk_clk_register_pll_ops()
359 	init.name = data->name;  in mtk_clk_register_pll_ops()
360 	init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0;  in mtk_clk_register_pll_ops()
362 	if (data->parent_name)  in mtk_clk_register_pll_ops()
363 		init.parent_names = &data->parent_name;  in mtk_clk_register_pll_ops()
366 	init.num_parents = 1;  in mtk_clk_register_pll_ops()
368 	ret = clk_hw_register(NULL, &pll->hw);  in mtk_clk_register_pll_ops()
373 	return &pll->hw;  in mtk_clk_register_pll_ops()
379 	struct mtk_clk_pll *pll;  in mtk_clk_register_pll()  local
381 	const struct clk_ops *pll_ops = data->ops ? data->ops : &mtk_pll_ops;  in mtk_clk_register_pll()
383 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);  in mtk_clk_register_pll()
384 	if (!pll)  in mtk_clk_register_pll()
385 		return ERR_PTR(-ENOMEM);  in mtk_clk_register_pll()
387 	hw = mtk_clk_register_pll_ops(pll, data, base, pll_ops);  in mtk_clk_register_pll()
389 		kfree(pll);  in mtk_clk_register_pll()
396 	struct mtk_clk_pll *pll;  in mtk_clk_unregister_pll()  local
401 	pll = to_mtk_clk_pll(hw);  in mtk_clk_unregister_pll()
404 	kfree(pll);  in mtk_clk_unregister_pll()
418 		return -EINVAL;  in mtk_clk_register_plls()
422 		const struct mtk_pll_data *pll = &plls[i];  in mtk_clk_register_plls()  local
424 		if (!IS_ERR_OR_NULL(clk_data->hws[pll->id])) {  in mtk_clk_register_plls()
426 				node, pll->id);  in mtk_clk_register_plls()
430 		hw = mtk_clk_register_pll(pll, base);  in mtk_clk_register_plls()
433 			pr_err("Failed to register clk %s: %pe\n", pll->name,  in mtk_clk_register_plls()
438 		clk_data->hws[pll->id] = hw;  in mtk_clk_register_plls()
444 	while (--i >= 0) {  in mtk_clk_register_plls()
445 		const struct mtk_pll_data *pll = &plls[i];  in mtk_clk_register_plls()  local
447 		mtk_clk_unregister_pll(clk_data->hws[pll->id]);  in mtk_clk_register_plls()
448 		clk_data->hws[pll->id] = ERR_PTR(-ENOENT);  in mtk_clk_register_plls()
460 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);  in mtk_clk_pll_get_base()  local
462 	return pll->base_addr - data->reg;  in mtk_clk_pll_get_base()
474 	for (i = num_plls; i > 0; i--) {  in mtk_clk_unregister_plls()
475 		const struct mtk_pll_data *pll = &plls[i - 1];  in mtk_clk_unregister_plls()  local
477 		if (IS_ERR_OR_NULL(clk_data->hws[pll->id]))  in mtk_clk_unregister_plls()
486 		base = mtk_clk_pll_get_base(clk_data->hws[pll->id], pll);  in mtk_clk_unregister_plls()
488 		mtk_clk_unregister_pll(clk_data->hws[pll->id]);  in mtk_clk_unregister_plls()
489 		clk_data->hws[pll->id] = ERR_PTR(-ENOENT);  in mtk_clk_unregister_plls()