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Searched full:pl1 (Results 1 – 25 of 35) sorted by relevance

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/freebsd/crypto/krb5/src/kdc/
H A Dkdc_transit.c163 int pl, pl1; /* prefix length */ in add_to_transited() local
328 if ((pl1 = subrealm(prev,realm))) { in add_to_transited()
329 if (strlen(current) + (pl1>0?pl1:-pl1) + 1 >= MAX_REALM_LN) { in add_to_transited()
333 if (pl1 > 0) { in add_to_transited()
334 strncat(current, realm, (unsigned) pl1); in add_to_transited()
337 strncat(current, realm+strlen(realm)+pl1, (unsigned) (-pl1)); in add_to_transited()
/freebsd/sys/arm/include/
H A Dsysreg.h164 #define CP15_ATS1CPR(rr) p15, 0, rr, c7, c8, 0 /* Stage 1 Current state PL1 read */
165 #define CP15_ATS1CPW(rr) p15, 0, rr, c7, c8, 1 /* Stage 1 Current state PL1 write */
170 #define CP15_ATS12NSOPR(rr) p15, 0, rr, c7, c8, 4 /* Stages 1 and 2 Non-secure only PL1 read */
171 #define CP15_ATS12NSOPW(rr) p15, 0, rr, c7, c8, 5 /* Stages 1 and 2 Non-secure only PL1 write */
253 #define CP15_TPIDRPRW(rr) p15, 0, rr, c13, c0, 4 /* PL1 only Thread ID Register */
262 #define CP15_CNTKCTL(rr) p15, 0, rr, c14, c1, 0 /* Timer PL1 Control Register */
263 #define CP15_CNTP_TVAL(rr) p15, 0, rr, c14, c2, 0 /* PL1 Physical Timer Value Register */
264 #define CP15_CNTP_CTL(rr) p15, 0, rr, c14, c2, 1 /* PL1 Physical Timer Control Register */
273 #define CP15_CNTP_CVAL(rq, rr) p15, 2, rq, rr, c14 /* PL1 Physical Timer Compare Value Register */
H A Dcpu.h616 * cp15_ats1cpr_check() ... check stage 1 privileged (PL1) read access
617 * cp15_ats1cpw_check() ... check stage 1 privileged (PL1) write access
/freebsd/contrib/tcsh/
H A DNewThings117 6.00 PL1
152 5.19 PL1
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dnvidia,tegra210-pinmux.txt108 pk3, pk4, pk5, pk6, pk7, pl0, pl1, pwr_i2c_scl_py3, pwr_i2c_sda_py4,
131 pa6, pcc7, pe6, pe7, ph6, pk0, pk1, pk2, pk3, pk4, pk5, pk6, pk7, pl0, pl1,
H A Dnvidia,tegra210-pinmux.yaml56 pk0, pk1, pk2, pk3, pk4, pk5, pk6, pk7, pl0, pl1,
/freebsd/crypto/openssl/crypto/evp/
H A Devp_fetch.c534 OSSL_PROPERTY_LIST *pl1, *pl2; in evp_default_properties_merge() local
540 if ((pl1 = ossl_parse_query(libctx, propq, 1)) == NULL) { in evp_default_properties_merge()
544 pl2 = ossl_property_merge(pl1, *plp); in evp_default_properties_merge()
545 ossl_property_free(pl1); in evp_default_properties_merge()
/freebsd/sys/contrib/device-tree/src/arm/allwinner/
H A Dsunxi-bananapi-m2-plus-v1.2.dtsi22 gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */
H A Dsun8i-h2-plus-bananapi-m2-zero.dts71 gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */
H A Dsun8i-a23-a33.dtsi823 pins = "PL0", "PL1";
829 pins = "PL0", "PL1";
/freebsd/contrib/sendmail/cf/mailer/
H A Dfax.m416 # Tested with HylaFAX 4.0pl1
/freebsd/contrib/llvm-project/compiler-rt/lib/tsan/rtl/
H A Dtsan_fd.cpp83 atomic_uintptr_t *pl1 = &fdctx.tab[fd / kTableSizeL2]; in fddesc() local
84 uptr l1 = atomic_load(pl1, memory_order_consume); in fddesc()
91 if (atomic_compare_exchange_strong(pl1, &l1, (uptr)p, memory_order_acq_rel)) in fddesc()
/freebsd/sys/arm/allwinner/a83t/
H A Da83t_r_padconf.c37 { "PL1", 0, 1, { "gpio_in", "gpio_out", "s_rsb", "s_i2c", NULL, NULL, "eint" } },
/freebsd/sys/arm/allwinner/h3/
H A Dh3_r_padconf.c42 {"PL1", 0, 1, {"gpio_in", "gpio_out", "s_twi", NULL, NULL, NULL, "pl_eint1", NULL}, 6, 1, 0},
/freebsd/sys/arm/allwinner/a64/
H A Da64_r_padconf.c39 { "PL1", 0, 1, { "gpio_in", "gpio_out", "s_rsb", "s_i2c", NULL, NULL, "pl_eint1" }, 6, 1, 0},
/freebsd/sys/arm/allwinner/h6/
H A Dh6_r_padconf.c36 {"PL1", 0, 1, {"gpio_in", "gpio_out", NULL, "s_i2c", NULL, NULL, "pl_eint1", NULL}, 6, 1, 0},
/freebsd/sys/arm/allwinner/a31/
H A Da31_r_padconf.c38 {"PL1", 0, 1, {"gpio_in", "gpio_out", "s_twi", "s_p2wi", NULL, NULL, NULL, NULL}},
/freebsd/contrib/llvm-project/llvm/lib/BinaryFormat/
H A DXCOFF.cpp94 LANG_CASE(PL1) in getNameForTracebackTableLanguageId()
/freebsd/sys/contrib/device-tree/src/arm64/allwinner/
H A Dsun50i-h616.dtsi883 pins = "PL0", "PL1";
888 pins = "PL0", "PL1";
H A Dsun50i-a100.dtsi319 pins = "PL0", "PL1";
H A Dsun50i-h6.dtsi1011 pins = "PL0", "PL1";
1021 pins = "PL0", "PL1";
/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_pinmux.c200 GRP(0x9f8, pl1, 0, 0, 0, 0),
406 GMUX(0x278, L, 1, pl1, soc, rsvd1, rsvd2, rsvd3, -1, 0, 0, 0, 0),
/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra210-p2571.dts615 pl1 {
616 nvidia,pins = "pl1";
H A Dtegra210-p2595.dtsi604 pl1 {
605 nvidia,pins = "pl1";
/freebsd/contrib/llvm-project/llvm/include/llvm/BinaryFormat/
H A DXCOFF.h368 PL1, enumerator

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