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/freebsd/sys/contrib/device-tree/Bindings/display/panel/
H A Dpanel-mipi-dbi-spi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-mipi-dbi-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Noralf Trønnes <noralf@tronnes.org>
23 - Power:
24 - Vdd: Power supply for display module
25 Called power-supply in this binding.
26 - Vddi: Logic level supply for interface signals
27 Called io-supply in this binding.
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/freebsd/contrib/file/magic/Magdir/
H A Dmodem2 #------------------------------------------------------------------------------
7 1 string PC\ Research,\ Inc Digifax-G3-File
18 # 16 0-bits near beginning like True Type fonts *.ttf, Postscript PrinterFontMetric *.pfm, FTYPE.HY…
20 # maximal 7 0-bits for pixel sequences or 11 0-bits for EOL in G3
22 # skip IRCAM file (VAX big-endian) ./audio
37 # skip few (5/41) DEGAS mid-res bitmap (GEMINI01.PI2 GEMINI02.PI2 GEMINI03.PI2 CODE_RAM.PI2 TBX_DEM…
39 >>>>>>>>-0 offset !32034 raw G3 (Group 3) FAX, byte-padded
40 # version 5.25 labeled the entry above "raw G3 data, byte-padded"
44 # unusual image starting with black pixel
47 # 16 0-bits near beginning like PicturePuzzler found on Golden Orchard Apple CD Rom
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H A Dimages2 #------------------------------------------------------------------------------
4 # images: file(1) magic for image formats (see also "iff", and "c-lang" for
9 # merging several one- and two-line files into here.
13 # Targa - matches `povray', `ppmtotga' and `xv' outputs
19 # Note: called by DROID "Truevision TGA Bitmap" version 1.0 via PUID x-fmt/367
23 # or theoretically 2-128 reserved for use by Truevision or 128-255 may be used for developer applic…
32 # Targa image data (strength=70=110-40) before some Commodore disc image (strength=70=70+0 ./c64) l…
35 !:strength -40
37 #>(2.S-2) belong !0x28632943
47 # skip arches.3200 , Finder.Root , Slp.1 by looking for low pixel depth 1 8 15 16 24 32
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H A Dpc981 #------------------------------------------------------------------------------
4 # Fabio R. Schmidlin <sd-snatcher@users.sourceforge.net>
6 # Maki-chan v1 Graphic format
7 # The image resolution should be X=(44.L - 40.L) and Y=(46.L - 42.L), but I couldn't find a way to …
9 0 string/b MAKI01 Maki-chan v1.
22 # Maki-chan v2 Graphic format
26 0 string/b MAKI02\ \ Maki-chan v2 image,
32 #Maki-chan video modes are a bit messy and seems to have been expanded over the years without too m…
35 # - b0=pixel aspect ratio: 1=2:1 (note: this ignores that the machine's 1:1 pixel aspect ratio is…
36 # - b1=number of colors: 0=16 colors, 1=8 colors
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H A Dcups2 #------------------------------------------------------------------------------
4 # Cups: file(1) magic for the cups raster file format
6 # https://www.cups.org/documentation.php/spec-raster.html
9 0 name cups-le
15 >392 lelong x %d bits/pixel
41 # Cups Raster image format, Big Endian
46 !:mime application/vnd.cups-raster
47 >0 use \^cups-le
50 # Cups Raster image format, Little Endian
55 !:mime application/vnd.cups-raster
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H A Dterminfo2 #------------------------------------------------------------------------------
6 # URL: https://invisible-island.net/ncurses/man/term.5.html
7 # URL: https://invisible-island.net/ncurses/man/scr_dump.5.html
14 # 5th character of terminal name list, but not Targa image pixel size (15 16 24 32)
17 >>12 regex \^[a-zA-Z0-9][a-zA-Z0-9.][^|]* Compiled terminfo entry "%-s"
18 !:mime application/x-terminfo
22 #------------------------------------------------------------------------------
24 #------------------------------------------------------------------------------
27 # imitate the legacy compiled-format, to get the entry-name printed
30 >>12 regex \^[a-zA-Z0-9][a-zA-Z0-9.][^|]* Compiled 32-bit terminfo entry "%-s"
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/freebsd/sys/contrib/device-tree/Bindings/display/bridge/
H A Dfsl,imx8qxp-ldb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
20 format and can map the input to VESA or JEIDA standards. The two channels
28 input color format. The two channels can be used simultaneously, either
33 A side note is that i.MX8qm/qxp LDB is officially called pixel mapper in
34 the SoC reference manuals. The pixel mapper uses logic of LDBs embedded in
41 - fsl,imx8qm-ldb
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H A Dadi,adv7511.txt2 ------------------------------------------------
11 - compatible: Should be one of:
18 - reg: I2C slave addresses
27 color depth, color format, clock mode, bit justification and random
32 - adi,input-depth: Number of bits per color component at the input (8, 10 or
34 - adi,input-colorspace: The input color space, one of "rgb", "yuv422" or
36 - adi,input-clock: The input clock type, one of "1x" (one clock cycle per
37 pixel), "2x" (two clock cycles per pixel), "ddr" (one clock cycle per pixel,
40 The following input format properties are required except in "rgb 1x" and
43 - adi,input-style: The input components arrangement variant (1, 2 or 3), as
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H A Dadi,adv7511.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
21 - adi,adv7511
22 - adi,adv7511w
23 - adi,adv7513
37 reg-names:
40 needing a non-default address.
43 - const: main
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/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dst,stm32-dma2d.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/st,stm32-dma2d.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Chrom-Art Accelerator DMA2D
10 Chrom-ART Accelerator(DMA2D), graphical hardware accelerator
15 - Filling a part or the whole of a destination image with a specific color.
16 - Copying a part or the whole of a source image into a part or the whole of
18 - Copying a part or the whole of a source image into a part or the whole of
19 a destination image with a pixel format conversion.
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H A Drenesas,rzg2l-cru.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/renesas,rzg2l-cru.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
14 The CRU image processing module is a data conversion module equipped with pixel
15 color space conversion, LUT, pixel format conversion, etc. An MIPI CSI-2 input and
16 parallel (including ITU-R BT.656) input are provided as the image sensor interface.
21 - enum:
22 - renesas,r9a07g043-cru # RZ/G2UL
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H A Drenesas,fdp1.txt1 Renesas R-Car Fine Display Processor (FDP1)
2 -------------------------------------------
4 The FDP1 is a de-interlacing module which converts interlaced video to
5 progressive video. It is capable of performing pixel format conversion between
11 - compatible: must be "renesas,fdp1"
12 - reg: the register base and size for the device registers
13 - interrupts : interrupt specifier for the FDP1 instance
14 - clocks: reference to the functional clock
18 - power-domains: reference to the power domain that the FDP1 belongs to, if
20 - renesas,fcp: a phandle referencing the FCP that handles memory accesses
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H A Dnxp,dw100.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xavier Roumegue <xavier.roumegue@oss.nxp.com>
12 description: |-
13 The Dewarp Engine provides high-performance dewarp processing for the
15 and wide angle lenses. It is implemented with a line/tile-cache based
18 The engine can be used to perform scaling, cropping and pixel format
24 - nxp,imx8mp-dw100
34 - description: The AXI clock
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H A Drenesas,fdp1.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Fine Display Processor (FDP1)
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 The FDP1 is a de-interlacing module which converts interlaced video to
14 progressive video. It is capable of performing pixel format conversion
21 - renesas,fdp1
32 power-domains:
42 Not allowed on R-Car Gen2, mandatory on R-Car Gen3.
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/freebsd/sys/contrib/device-tree/Bindings/media/xilinx/
H A Dvideo.txt2 -------------------------------------
10 cores are represented as defined in ../video-interfaces.txt.
16 -----------------
20 - xlnx,video-format: This property represents a video format transmitted on an
21 AXI bus between video IP cores, using its VF code as defined in "AXI4-Stream
22 Video IP and System Design Guide" [UG934]. How the format relates to the IP
25 - xlnx,video-width: This property qualifies the video format with the sample
26 width expressed as a number of bits per pixel component. All components must
29 - xlnx,cfa-pattern: When the video format is set to Mono/Sensor, this property
/freebsd/sys/arm/nvidia/drm2/
H A Dtegra_dc.c1 /*-
55 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, 4 * (_r), (_v))
56 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, 4 * (_r))
58 #define LOCK(_sc) mtx_lock(&(_sc)->mtx)
59 #define UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
61 mtx_sleep(sc, &sc->mtx, 0, "tegra_dc_wait", timeout);
63 mtx_init(&_sc->mtx, device_get_nameunit(_sc->dev), "tegra_dc", MTX_DEF)
64 #define LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx)
65 #define ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED)
66 #define ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->mtx, MA_NOTOWNED)
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/freebsd/contrib/llvm-project/llvm/include/llvm/BinaryFormat/
H A DDXContainer.h1 //===-- llvm/BinaryFormat/DXContainer.h - The DXBC file format --*- C++/-*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines manifest constants for the DXContainer object file format.
11 //===----------------------------------------------------------------------===//
25 // The DXContainer file format is arranged as a header and "parts". Semantically
26 // parts are similar to sections in other object file formats. The File format
42 assert(Kind <= Triple::Amplification - Triple::Pixel && in getShaderStage()
44 return static_cast<Triple::EnvironmentType>(Triple::Pixel + Kind); in getShaderStage()
54 // taking into account source information (-Zss)
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/freebsd/sys/contrib/v4l/
H A Dvideodev2.h4 * Copyright (C) 1999-2007 the contributors
46 * All kernel-specific stuff were moved to media/v4l2-dev.h, so
108 /* Four-character-code (FOURCC) */
125 buffer, top-bottom order */
126 V4L2_FIELD_SEQ_BT = 6, /* same as above + bottom-top order */
196 /* ITU-R 601 -- broadcast NTSC/PAL */
199 /* 1125-Line (US) HDTV */
205 /* broken BT878 extents (601, luma range 16-253 instead of 16-235) */
213 * unspecified chromaticities and full 0-255 on each of the
290 /* Pixel format FOURCC depth Description */
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/freebsd/sys/dev/drm2/
H A Ddrm_crtc.c2 * Copyright (c) 2006-2008 Intel Corporation
84 * Non-global properties, but "required" for certain connectors.
88 { DRM_MODE_SUBCONNECTOR_Automatic, "Automatic" }, /* DVI-I and TV-out */
89 { DRM_MODE_SUBCONNECTOR_DVID, "DVI-D" }, /* DVI-I */
90 { DRM_MODE_SUBCONNECTOR_DVIA, "DVI-A" }, /* DVI-I */
97 { DRM_MODE_SUBCONNECTOR_Unknown, "Unknown" }, /* DVI-I and TV-out */
98 { DRM_MODE_SUBCONNECTOR_DVID, "DVI-D" }, /* DVI-I */
99 { DRM_MODE_SUBCONNECTOR_DVIA, "DVI-A" }, /* DVI-I */
107 { DRM_MODE_SUBCONNECTOR_Automatic, "Automatic" }, /* DVI-I and TV-out */
108 { DRM_MODE_SUBCONNECTOR_Composite, "Composite" }, /* TV-out */
[all …]
H A Ddrm_crtc.h3 * Copyright © 2007-2008 Dave Airlie
4 * Copyright © 2007-2008 Intel Corporation
104 MODE_UNVERIFIED = -3, /* mode needs to reverified */
105 MODE_BAD = -2, /* unspecified reason */
106 MODE_ERROR = -1 /* error condition */
204 /* Clock limits FIXME: storage format */
263 uint32_t pixel_format; /* fourcc format */
300 * drm_crtc_funcs - control CRTCs for a given device
360 * drm_crtc - central CRTC control structure
377 * @pixeldur_ns: precise pixel timing
[all …]
/freebsd/sys/contrib/device-tree/Bindings/media/i2c/
H A Dmt9m001.txt1 MT9M001: 1/2-Inch Megapixel Digital Image Sensor
3 The MT9M001 is an SXGA-format with a 1/2-inch CMOS active-pixel digital
8 - compatible: shall be "onnn,mt9m001".
9 - clocks: reference to the master clock into sensor
13 - reset-gpios: GPIO handle which is connected to the reset pin of the chip.
15 - standby-gpios: GPIO handle which is connected to the standby pin of the chip.
19 sub-node for its digital output video port, in accordance with the video
21 Documentation/devicetree/bindings/media/video-interfaces.txt
26 camera-sensor@5d {
29 reset-gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
[all …]
H A Daptina,mt9v111.txt2 ----------------------------
4 The Aptina MT9V111 is a 1/4-Inch VGA-format digital image sensor with a core
7 The sensor has an active pixel array of 640x480 pixels and can output a number
8 of image resolution and formats controllable through a simple two-wires
12 --------------------
14 - compatible: shall be "aptina,mt9v111".
15 - clocks: reference to the system clock input provider.
18 --------------------
20 - enable-gpios: output enable signal, pin name "OE#". Active low.
21 - standby-gpios: low power state control signal, pin name "STANDBY".
[all …]
H A Daptina,mt9v111.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacopo Mondi <jacopo@jmondi.org>
13 The Aptina MT9V111 is a 1/4-Inch VGA-format digital image sensor with a core
16 The sensor has an active pixel array of 640x480 pixels and can output a number
17 of image resolutions and formats controllable through a simple two-wires
30 enable-gpios:
34 standby-gpios:
39 reset-gpios:
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/ti/
H A Dti,am65x-dss.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/ti/ti,am65x-dss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Jyri Sarha <jsarha@ti.com>
12 - Tomi Valkeinen <tomi.valkeinen@ti.com>
19 format. The first plane is full video plane with all features and the
25 - ti,am625-dss
26 - ti,am62a7,dss
27 - ti,am65x-dss
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/freebsd/sys/powerpc/mpc85xx/
H A Dfsl_diu.c1 /*-
121 #define DIU_CTRLDESCL(n, m) 0x200 + (0x40 * n) + 0x4 * (m - 1)
127 #define BPP_MASK 0xf /* Bit per pixel Mask */
128 #define BPP_SHIFT 16 /* Bit per pixel Shift */
179 { -1, 0 }
205 reg = bus_read_4(sc->res[0], DIU_INT_STATUS); in diu_intr()
206 bus_write_4(sc->res[0], DIU_INT_STATUS, reg); in diu_intr()
225 /* adding freq/2 to round-to-closest */ in diu_set_pxclk()
243 panel = &sc->sc_panel; in diu_init()
246 reg = bus_read_4(sc->res[0], DIU_DIU_MODE); in diu_init()
[all …]

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