1 /*-
121 #define DIU_CTRLDESCL(n, m)	0x200 + (0x40 * n) + 0x4 * (m - 1)
127 #define	 BPP_MASK		0xf		/* Bit per pixel Mask */
128 #define	 BPP_SHIFT		16		/* Bit per pixel Shift */
179 	{ -1, 0 }
205 	reg = bus_read_4(sc->res[0], DIU_INT_STATUS);  in diu_intr()
206 	bus_write_4(sc->res[0], DIU_INT_STATUS, reg);  in diu_intr()
225 	/* adding freq/2 to round-to-closest */  in diu_set_pxclk()
243 	panel = &sc->sc_panel;  in diu_init()
246 	reg = bus_read_4(sc->res[0], DIU_DIU_MODE);  in diu_init()
248 	bus_write_4(sc->res[0], DIU_DIU_MODE, reg);  in diu_init()
250 	if (diu_set_pxclk(sc->sc_dev, panel->panel_freq) < 0) {  in diu_init()
256 	bus_write_4(sc->res[0], DIU_GAMMA, vtophys(sc->sc_gamma));  in diu_init()
257 	bus_write_4(sc->res[0], DIU_CURSOR, vtophys(sc->sc_cursor));  in diu_init()
258 	bus_write_4(sc->res[0], DIU_CURS_POS, 0);  in diu_init()
260 	reg = ((sc->sc_info.fb_height) << DELTA_Y_S);  in diu_init()
261 	reg |= sc->sc_info.fb_width;  in diu_init()
262 	bus_write_4(sc->res[0], DIU_DISP_SIZE, reg);  in diu_init()
264 	reg = (panel->panel_hbp << BP_H_SHIFT);  in diu_init()
265 	reg |= (panel->panel_hpw << PW_H_SHIFT);  in diu_init()
266 	reg |= (panel->panel_hfp << FP_H_SHIFT);  in diu_init()
267 	bus_write_4(sc->res[0], DIU_HSYN_PARA, reg);  in diu_init()
269 	reg = (panel->panel_vbp << BP_V_SHIFT);  in diu_init()
270 	reg |= (panel->panel_vpw << PW_V_SHIFT);  in diu_init()
271 	reg |= (panel->panel_vfp << FP_V_SHIFT);  in diu_init()
272 	bus_write_4(sc->res[0], DIU_VSYN_PARA, reg);  in diu_init()
274 	bus_write_4(sc->res[0], DIU_BGND, 0);  in diu_init()
277 	bus_write_4(sc->res[0], DIU_INT_MASK, 0x3f);  in diu_init()
280 	sc->sc_planes[0] = contigmalloc(sizeof(struct diu_area_descriptor),  in diu_init()
282 	bus_write_4(sc->res[0], DIU_DESC_1, vtophys(sc->sc_planes[0]));  in diu_init()
283 	bus_write_4(sc->res[0], DIU_DESC_2, 0);  in diu_init()
284 	bus_write_4(sc->res[0], DIU_DESC_3, 0);  in diu_init()
288 	/* Word 0: Pixel format */  in diu_init()
289 	/* Set to 8:8:8:8 ARGB, 4 bytes per pixel, no flip. */  in diu_init()
297 	sc->sc_planes[0]->pixel_format = reg;  in diu_init()
299 	sc->sc_planes[0]->bitmap_address = htole32(sc->sc_info.fb_pbase);  in diu_init()
301 	reg = (sc->sc_info.fb_width | (sc->sc_info.fb_height << 12));  in diu_init()
302 	sc->sc_planes[0]->source_size = htole32(reg);  in diu_init()
304 	reg = (sc->sc_info.fb_width | (sc->sc_info.fb_height << 16));  in diu_init()
305 	sc->sc_planes[0]->aoi_size = htole32(reg);  in diu_init()
307 	sc->sc_planes[0]->aoi_offset = 0;  in diu_init()
309 	sc->sc_planes[0]->display_offset = 0;  in diu_init()
311 	sc->sc_planes[0]->chroma_key_max = 0;  in diu_init()
314 	sc->sc_planes[0]->chroma_key_min = htole32(reg);  in diu_init()
316 	sc->sc_planes[0]->next_ad_addr = 0;  in diu_init()
319 	bus_write_4(sc->res[0], DIU_PLUT, 0x1f5f666);  in diu_init()
322 	reg = bus_read_4(sc->res[0], DIU_DIU_MODE);  in diu_init()
325 	bus_write_4(sc->res[0], DIU_DIU_MODE, reg);  in diu_init()
343 	sc->sc_dev = dev;  in diu_attach()
345 	if (bus_alloc_resources(dev, diu_spec, sc->res)) {  in diu_attach()
352 	err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_BIO | INTR_MPSAFE,  in diu_attach()
353 	    NULL, diu_intr, sc, &sc->ih);  in diu_attach()
365 			    "No EDID data and no video-mode env set\n");  in diu_attach()
377 		/* Parse video-mode kenv variable. */  in diu_attach()
391 	sc->sc_panel.panel_width = videomode->hdisplay;  in diu_attach()
392 	sc->sc_panel.panel_height = videomode->vdisplay;  in diu_attach()
393 	sc->sc_panel.panel_hbp = videomode->hsync_start - videomode->hdisplay;  in diu_attach()
394 	sc->sc_panel.panel_hfp = videomode->htotal - videomode->hsync_end;  in diu_attach()
395 	sc->sc_panel.panel_hpw = videomode->hsync_end - videomode->hsync_start;  in diu_attach()
396 	sc->sc_panel.panel_vbp = videomode->vsync_start - videomode->vdisplay;  in diu_attach()
397 	sc->sc_panel.panel_vfp = videomode->vtotal - videomode->vsync_end;  in diu_attach()
398 	sc->sc_panel.panel_vpw = videomode->vsync_end - videomode->vsync_start;  in diu_attach()
399 	sc->sc_panel.panel_freq = videomode->dot_clock;  in diu_attach()
401 	sc->sc_info.fb_width = sc->sc_panel.panel_width;  in diu_attach()
402 	sc->sc_info.fb_height = sc->sc_panel.panel_height;  in diu_attach()
403 	sc->sc_info.fb_stride = sc->sc_info.fb_width * 4;  in diu_attach()
404 	sc->sc_info.fb_bpp = sc->sc_info.fb_depth = 32;  in diu_attach()
405 	sc->sc_info.fb_size = sc->sc_info.fb_height * sc->sc_info.fb_stride;  in diu_attach()
406 	sc->sc_info.fb_vbase = (intptr_t)contigmalloc(sc->sc_info.fb_size,  in diu_attach()
408 	sc->sc_info.fb_pbase = (intptr_t)vtophys(sc->sc_info.fb_vbase);  in diu_attach()
409 	sc->sc_info.fb_flags = FB_FLAG_MEMATTR;  in diu_attach()
410 	sc->sc_info.fb_memattr = VM_MEMATTR_DEFAULT;  in diu_attach()
413 	sc->sc_gamma = contigmalloc(3 * 256, M_DEVBUF, 0, 0,  in diu_attach()
417 		sc->sc_gamma[i] = (i % 256);  in diu_attach()
419 	/* Cursor format is 32x32x16bpp */  in diu_attach()
420 	sc->sc_cursor = contigmalloc(32 * 32 * 2, M_DEVBUF, M_ZERO, 0,  in diu_attach()
425 	sc->sc_info.fb_name = device_get_nameunit(dev);  in diu_attach()
428 	sc->sc_fbd = device_add_child(dev, "fbd", device_get_unit(dev));  in diu_attach()
429 	if (sc->sc_fbd == NULL)  in diu_attach()
432 	if ((err = device_probe_and_attach(sc->sc_fbd)) != 0) {  in diu_attach()
444 	return (&sc->sc_info);  in diu_fb_getinfo()