xref: /freebsd/sys/contrib/device-tree/Bindings/media/renesas,fdp1.yaml (revision c66ec88fed842fbaad62c30d510644ceb7bd2d71)
1*c66ec88fSEmmanuel Vadot# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2*c66ec88fSEmmanuel Vadot%YAML 1.2
3*c66ec88fSEmmanuel Vadot---
4*c66ec88fSEmmanuel Vadot$id: http://devicetree.org/schemas/media/renesas,fdp1.yaml#
5*c66ec88fSEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml#
6*c66ec88fSEmmanuel Vadot
7*c66ec88fSEmmanuel Vadottitle: Renesas R-Car Fine Display Processor (FDP1)
8*c66ec88fSEmmanuel Vadot
9*c66ec88fSEmmanuel Vadotmaintainers:
10*c66ec88fSEmmanuel Vadot  - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
11*c66ec88fSEmmanuel Vadot
12*c66ec88fSEmmanuel Vadotdescription:
13*c66ec88fSEmmanuel Vadot  The FDP1 is a de-interlacing module which converts interlaced video to
14*c66ec88fSEmmanuel Vadot  progressive video. It is capable of performing pixel format conversion
15*c66ec88fSEmmanuel Vadot  between YCbCr/YUV formats and RGB formats. Only YCbCr/YUV formats are
16*c66ec88fSEmmanuel Vadot  supported as an input to the module.
17*c66ec88fSEmmanuel Vadot
18*c66ec88fSEmmanuel Vadotproperties:
19*c66ec88fSEmmanuel Vadot  compatible:
20*c66ec88fSEmmanuel Vadot    enum:
21*c66ec88fSEmmanuel Vadot      - renesas,fdp1
22*c66ec88fSEmmanuel Vadot
23*c66ec88fSEmmanuel Vadot  reg:
24*c66ec88fSEmmanuel Vadot    maxItems: 1
25*c66ec88fSEmmanuel Vadot
26*c66ec88fSEmmanuel Vadot  interrupts:
27*c66ec88fSEmmanuel Vadot    maxItems: 1
28*c66ec88fSEmmanuel Vadot
29*c66ec88fSEmmanuel Vadot  clocks:
30*c66ec88fSEmmanuel Vadot    maxItems: 1
31*c66ec88fSEmmanuel Vadot
32*c66ec88fSEmmanuel Vadot  power-domains:
33*c66ec88fSEmmanuel Vadot    maxItems: 1
34*c66ec88fSEmmanuel Vadot
35*c66ec88fSEmmanuel Vadot  resets:
36*c66ec88fSEmmanuel Vadot    maxItems: 1
37*c66ec88fSEmmanuel Vadot
38*c66ec88fSEmmanuel Vadot  renesas,fcp:
39*c66ec88fSEmmanuel Vadot    $ref: /schemas/types.yaml#/definitions/phandle
40*c66ec88fSEmmanuel Vadot    description:
41*c66ec88fSEmmanuel Vadot      A phandle referencing the FCP that handles memory accesses for the FDP1.
42*c66ec88fSEmmanuel Vadot      Not allowed on R-Car Gen2, mandatory on R-Car Gen3.
43*c66ec88fSEmmanuel Vadot
44*c66ec88fSEmmanuel Vadotrequired:
45*c66ec88fSEmmanuel Vadot  - compatible
46*c66ec88fSEmmanuel Vadot  - reg
47*c66ec88fSEmmanuel Vadot  - interrupts
48*c66ec88fSEmmanuel Vadot  - clocks
49*c66ec88fSEmmanuel Vadot  - power-domains
50*c66ec88fSEmmanuel Vadot  - resets
51*c66ec88fSEmmanuel Vadot
52*c66ec88fSEmmanuel VadotadditionalProperties: false
53*c66ec88fSEmmanuel Vadot
54*c66ec88fSEmmanuel Vadotexamples:
55*c66ec88fSEmmanuel Vadot  - |
56*c66ec88fSEmmanuel Vadot    #include <dt-bindings/clock/renesas-cpg-mssr.h>
57*c66ec88fSEmmanuel Vadot    #include <dt-bindings/interrupt-controller/arm-gic.h>
58*c66ec88fSEmmanuel Vadot    #include <dt-bindings/power/r8a7795-sysc.h>
59*c66ec88fSEmmanuel Vadot
60*c66ec88fSEmmanuel Vadot    fdp1@fe940000 {
61*c66ec88fSEmmanuel Vadot        compatible = "renesas,fdp1";
62*c66ec88fSEmmanuel Vadot        reg = <0xfe940000 0x2400>;
63*c66ec88fSEmmanuel Vadot        interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
64*c66ec88fSEmmanuel Vadot        clocks = <&cpg CPG_MOD 119>;
65*c66ec88fSEmmanuel Vadot        power-domains = <&sysc R8A7795_PD_A3VP>;
66*c66ec88fSEmmanuel Vadot        resets = <&cpg 119>;
67*c66ec88fSEmmanuel Vadot        renesas,fcp = <&fcpf0>;
68*c66ec88fSEmmanuel Vadot    };
69*c66ec88fSEmmanuel Vadot...
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