| /linux/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/ |
| H A D | pipeline.json | 9 "PublicDescription": "This event counts valid cycles of EAGA pipeline.",
12 "BriefDescription": "This event counts valid cycles of EAGA pipeline."
15 "PublicDescription": "This event counts valid cycles of EAGB pipeline.",
18 "BriefDescription": "This event counts valid cycles of EAGB pipeline."
21 "PublicDescription": "This event counts valid cycles of EXA pipeline.",
24 "BriefDescription": "This event counts valid cycles of EXA pipeline."
27 "PublicDescription": "This event counts valid cycles of EXB pipeline.",
30 "BriefDescription": "This event counts valid cycles of EXB pipeline."
33 "PublicDescription": "This event counts valid cycles of FLA pipeline.",
36 "BriefDescription": "This event counts valid cycles of FLA pipeline."
[all …]
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| /linux/drivers/staging/media/atomisp/pci/runtime/pipeline/src/ |
| H A D | pipeline.c | 35 struct ia_css_pipeline *pipeline,
44 static void ia_css_pipeline_set_zoom_stage(struct ia_css_pipeline *pipeline);
57 struct ia_css_pipeline *pipeline, in ia_css_pipeline_create() argument
62 assert(pipeline); in ia_css_pipeline_create()
63 IA_CSS_ENTER_PRIVATE("pipeline = %p, pipe_id = %d, pipe_num = %d, dvs_frame_delay = %d", in ia_css_pipeline_create()
64 pipeline, pipe_id, pipe_num, dvs_frame_delay); in ia_css_pipeline_create()
65 if (!pipeline) { in ia_css_pipeline_create()
70 pipeline_init_defaults(pipeline, pipe_id, pipe_num, dvs_frame_delay); in ia_css_pipeline_create()
93 /* @brief destroy a pipeline
95 * @param[in] pipeline
[all …]
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| /linux/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/ |
| H A D | pipeline.json | 5 "BriefDescription": "This event counts valid cycles of EAGA pipeline."
10 "BriefDescription": "This event counts valid cycles of EAGB pipeline."
15 "BriefDescription": "This event counts valid cycles of PRX pipeline."
20 "BriefDescription": "This event counts valid cycles of EXA pipeline."
25 "BriefDescription": "This event counts valid cycles of EXB pipeline."
30 "BriefDescription": "This event counts valid cycles of EXC pipeline."
35 "BriefDescription": "This event counts valid cycles of EXD pipeline."
40 "BriefDescription": "This event counts valid cycles of FLA pipeline."
45 "BriefDescription": "This event counts valid cycles of FLB pipeline."
50 "BriefDescription": "This event counts valid cycles of STEA pipeline."
[all …]
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| /linux/Documentation/gpu/ |
| H A D | komeda-kms.rst | 15 architecture. A display pipeline is made up of multiple individual and
16 functional pipeline stages called components, and every component has some
17 specific capabilities that can give the flowed pipeline pixel data a
24 Layer is the first pipeline stage, which prepares the pixel data for the next
58 Final stage of display pipeline, Timing controller is not for the pixel
76 Possible D71 Pipeline usage
94 Single pipeline data flow
98 :alt: Single pipeline digraph
99 :caption: Single pipeline data flow
140 Dual pipeline with Slave enabled
[all …]
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| /linux/tools/perf/pmu-events/arch/powerpc/power10/ |
| H A D | pipeline.json | 5 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered a TLB miss or…
55 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load…
60 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline finished at dispatch a…
85 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load…
90 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the s…
95 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a lwsync waiting t…
135 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was dispatched but not…
150 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the L…
155 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline required special handl…
165 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load…
[all …]
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| /linux/Documentation/gpu/rfc/ |
| H A D | color_pipeline.rst | 4 Linux Color Pipeline API
96 The Color Pipeline API
112 via the NEXT property of a drm_colorop to constitute a color pipeline.
137 as the entire pipeline can get bypassed by setting the COLOR_PIPELINE on
140 NEXT: The ID of the next drm_colorop in a color pipeline, or 0 if this
192 first drm_colorop in a pipeline. A driver can create and advertise none,
194 pipeline by setting the COLOR PIPELINE to the respective value.
198 on the colorop object IDs it is important to perform the Color Pipeline
199 Discovery, described below, instead of hard-coding color pipeline
202 pieces of HW. Color Pipeline Discovery can work universally, as long as
[all …]
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| /linux/drivers/gpu/drm/msm/disp/mdp5/ |
| H A D | mdp5_crtc.c | 95 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; in crtc_flush() local
102 return mdp5_ctl_commit(ctl, pipeline, flush_mask, start); in crtc_flush()
127 mixer = mdp5_cstate->pipeline.mixer; in crtc_flush_all()
130 r_mixer = mdp5_cstate->pipeline.r_mixer; in crtc_flush_all()
141 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; in complete_flip() local
159 mdp5_ctl_blend(ctl, pipeline, NULL, NULL, 0, 0); in complete_flip()
215 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; in blend_setup() local
220 struct mdp5_hw_mixer *mixer = pipeline->mixer; in blend_setup()
222 struct mdp5_hw_mixer *r_mixer = pipeline->r_mixer; in blend_setup()
355 mdp5_ctl_blend(ctl, pipeline, stage, r_stage, plane_cnt, in blend_setup()
[all …]
|
| H A D | mdp5_cmd_encoder.c | 129 struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc); in mdp5_cmd_encoder_disable() local
136 mdp5_ctl_set_encoder_state(ctl, pipeline, false); in mdp5_cmd_encoder_disable()
137 mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true); in mdp5_cmd_encoder_disable()
147 struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc); in mdp5_cmd_encoder_enable() local
155 mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true); in mdp5_cmd_encoder_enable()
157 mdp5_ctl_set_encoder_state(ctl, pipeline, true); in mdp5_cmd_encoder_enable()
|
| /linux/drivers/gpu/drm/xen/ |
| H A D | xen_drm_front_conn.c | 50 struct xen_drm_front_drm_pipeline *pipeline = in connector_detect() local
54 pipeline->conn_connected = false; in connector_detect()
56 return pipeline->conn_connected ? connector_status_connected : in connector_detect()
64 struct xen_drm_front_drm_pipeline *pipeline = in connector_get_modes() local
75 videomode.hactive = pipeline->width; in connector_get_modes()
76 videomode.vactive = pipeline->height; in connector_get_modes()
105 struct xen_drm_front_drm_pipeline *pipeline = in xen_drm_front_conn_init() local
110 pipeline->conn_connected = true; in xen_drm_front_conn_init()
|
| /linux/sound/soc/sof/ |
| H A D | ipc4-pcm.c | 97 /* trigger a single pipeline */ in sof_ipc4_set_multi_pipeline_state()
116 /* ipc_size includes the count and the pipeline IDs for the number of pipelines */ in sof_ipc4_set_multi_pipeline_state()
129 dev_dbg(sdev->dev, "Set pipeline %d to state %d%s", instance_id, state, in sof_ipc4_set_pipeline_state()
148 struct sof_ipc4_pipeline *pipeline = pipe_widget->private; in sof_ipc4_add_pipeline_by_priority() local
152 /* add pipeline from low priority to high */ in sof_ipc4_add_pipeline_by_priority()
153 if (ascend && pipeline->priority < pipe_priority[i]) in sof_ipc4_add_pipeline_by_priority()
155 /* add pipeline from high priority to low */ in sof_ipc4_add_pipeline_by_priority()
156 else if (!ascend && pipeline->priority > pipe_priority[i]) in sof_ipc4_add_pipeline_by_priority()
167 pipe_priority[i] = pipeline->priority; in sof_ipc4_add_pipeline_by_priority()
177 struct sof_ipc4_pipeline *pipeline = pipe_widget->private; in sof_ipc4_add_pipeline_to_trigger_list() local
[all …]
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| H A D | ipc4-topology.c | 199 [SOF_PIPELINE_TOKENS] = {"Pipeline tokens", pipeline_tokens, ARRAY_SIZE(pipeline_tokens)},
580 struct sof_ipc4_pipeline *pipeline = pipe_widget->private; in sof_ipc4_update_card_components_string() local
591 if (!pipeline->use_chain_dma) in sof_ipc4_update_card_components_string()
681 struct sof_ipc4_pipeline *pipeline = pipe_widget->private; in sof_ipc4_widget_setup_pcm() local
683 sps->dsp_max_burst_size_in_ms = pipeline->use_chain_dma ? in sof_ipc4_widget_setup_pcm()
757 struct sof_ipc4_pipeline *pipeline; in sof_ipc4_widget_setup_comp_dai() local
797 pipeline = pipe_widget->private; in sof_ipc4_widget_setup_comp_dai()
799 if (pipeline->use_chain_dma && in sof_ipc4_widget_setup_comp_dai()
930 struct sof_ipc4_pipeline *pipeline; in sof_ipc4_widget_setup_comp_pipeline() local
934 pipeline = kzalloc_obj(*pipeline); in sof_ipc4_widget_setup_comp_pipeline()
[all …]
|
| /linux/drivers/gpu/drm/msm/adreno/ |
| H A D | adreno_gen7_0_0_snapshot.h | 306 /* Block: GRAS Cluster: A7XX_CLUSTER_GRAS Pipeline: PIPE_BR */
316 /* Block: GRAS Cluster: A7XX_CLUSTER_GRAS Pipeline: PIPE_BV */
326 /* Block: PC Cluster: A7XX_CLUSTER_FE Pipeline: PIPE_BR */
334 /* Block: PC Cluster: A7XX_CLUSTER_FE Pipeline: PIPE_BV */
342 /* Block: RB_RAC Cluster: A7XX_CLUSTER_PS Pipeline: PIPE_BR */
358 /* Block: RB_RBP Cluster: A7XX_CLUSTER_PS Pipeline: PIPE_BR */
373 /* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: PIPE_BR Location: HLSQ_STATE */
384 /* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: PIPE_LPAC Location: HLSQ_STATE */
393 /* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: PIPE_BR Location: HLSQ_DP */
400 /* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: PIPE_LPAC Location: HLSQ_DP */
[all …]
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| H A D | adreno_gen7_9_0_snapshot.h | 229 * Pipeline: PIPE_NONE
293 * Pipeline: PIPE_NONE
337 * Pipeline: PIPE_NONE
358 * Pipeline: PIPE_NONE
370 * Pipeline: PIPE_NONE
385 * Pipeline: PIPE_NONE
399 * Pipeline: PIPE_BR
420 * Pipeline: PIPE_BV
441 * Pipeline: PIPE_LPAC
453 * Pipeline: PIPE_BR
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|
| /linux/tools/perf/pmu-events/arch/x86/amdzen4/ |
| H A D | cache.json | 448 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L…
454 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L…
460 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L…
466 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L…
472 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L…
478 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L…
484 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L…
490 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L…
496 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of all ty…
502 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in …
[all …]
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| /linux/drivers/media/platform/xilinx/ |
| H A D | xilinx-dma.h | 29 * struct xvip_pipeline - Xilinx Video IP pipeline structure
30 * @pipe: media pipeline
31 * @lock: protects the pipeline @stream_count
32 * @use_count: number of DMA engines using the pipeline
34 * @num_dmas: number of DMA engines in the pipeline
35 * @output: DMA engine at the output of the pipeline
64 * @pipe: pipeline belonging to the DMA channel
|
| /linux/sound/soc/sof/intel/ |
| H A D | hda-dai-ops.c | 129 struct sof_ipc4_pipeline *pipeline; in hda_ipc4_get_hext_stream()
136 pipeline = pipe_widget->private; in hda_ipc4_get_hext_stream()
138 /* mark pipeline so that it can be skipped during FE trigger */ in hda_ipc4_get_hext_stream()
139 pipeline->skip_during_fe_trigger = true; in hda_ipc4_get_hext_stream()
300 struct sof_ipc4_pipeline *pipeline; in hda_ipc4_pre_trigger()
308 pipeline = pipe_widget->private; in hda_ipc4_pre_trigger()
327 pipeline->state = SOF_IPC4_PIPE_PAUSED; in hda_ipc4_pre_trigger()
377 struct sof_ipc4_pipeline *pipeline; in hda_ipc4_post_trigger()
385 pipeline = pipe_widget->private; in hda_ipc4_post_trigger()
394 if (pipeline in hda_ipc4_post_trigger()
130 struct sof_ipc4_pipeline *pipeline; hda_ipc4_get_hext_stream() local
301 struct sof_ipc4_pipeline *pipeline; hda_ipc4_pre_trigger() local
378 struct sof_ipc4_pipeline *pipeline; hda_ipc4_post_trigger() local
627 struct sof_ipc4_pipeline *pipeline = pipe_widget->private; hda_select_dai_widget_ops() local
[all...] |
| /linux/Documentation/driver-api/media/ |
| H A D | mc-core.rst | 24 in a System-on-Chip image processing pipeline), DMA channels or physical
199 A media pipeline is a set of media streams which are interdependent. This
202 due to the software design. Most commonly a media pipeline consists of a single
205 When starting streaming, drivers must notify all entities in the pipeline to
209 The function will mark all the pads which are part of the pipeline as streaming.
212 stored in every pad in the pipeline. Drivers should embed the struct
213 media_pipeline in higher-level pipeline structures and can then access the
214 pipeline through the struct media_pad pipe field.
217 The pipeline pointer must be identical for all nested calls to the function.
244 for any entity which has sink pads in the pipeline. The
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| /linux/include/media/ |
| H A D | v4l2-mc.h | 51 * start a pipeline between the media source and the media
67 * active media pipeline between the media source and the
143 * v4l2_pipeline_pm_get - Increase the use count of a pipeline
144 * @entity: The root entity of a pipeline
149 * Update the use count of all entities in the pipeline and power entities on.
160 * v4l2_pipeline_pm_put - Decrease the use count of a pipeline
161 * @entity: The root entity of a pipeline
166 * Update the use count of all entities in the pipeline and power entities off.
|
| /linux/tools/perf/pmu-events/arch/x86/amdzen6/ |
| H A D | branch-prediction.json | 40 …"BriefDescription": "Branch predictor pipeline flushes due to internal conditions such as a second…
79 …"BriefDescription": "Redirects of the pipeline frontend caused by resyncs. These are retire time p…
85 …"BriefDescription": "Redirects of the pipeline frontend caused by mispredicts. These are used for …
91 "BriefDescription": "Redirects of the pipeline frontend caused by any reason."
|
| H A D | l2-cache.json | 179 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache and are g…
185 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache and are g…
191 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache and are g…
197 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache but hit in …
203 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache but hit in …
209 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache but hit in …
215 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 as well as the L3…
221 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 as well as the L3…
227 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 as well as the L3…
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| /linux/drivers/media/mc/ |
| H A D | mc-entity.c | 250 * and @pad1. If two pads are interdependent they are part of the same pipeline
427 * Pipeline management
431 * The pipeline traversal stack stores pads that are reached during graph
436 * To find further pads in the pipeline, the traversal algorithm follows
444 * struct media_pipeline_walk_entry - Entry in the pipeline traversal stack
455 * struct media_pipeline_walk - State used by the media pipeline traversal
530 "media pipeline: pushed entry %u: '%s':%u\n", in media_pipeline_walk_push()
552 "media pipeline: entry %u has no more links, popping\n", in media_pipeline_walk_pop()
562 "media pipeline: moved entry %u to next link\n", in media_pipeline_walk_pop()
568 /* Free all memory allocated while walking the pipeline. */
[all …]
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| /linux/drivers/media/platform/microchip/ |
| H A D | microchip-isc.h | 78 /* Pipeline bitmap */
98 * struct fmt_config - ISC format configuration and internal pipeline
112 * @bits_pipeline: Configuration of the pipeline, which modules are enabled
236 * @pipeline: configuration of the ISC pipeline
263 * @adapt_pipeline: pointer to a function that adapts the pipeline bits
264 * to the product specific pipeline
275 * @mpipe: media device pipeline used by the isc
314 struct regmap_field *pipeline[ISC_PIPE_LINE_NODE_NUM]; member
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| /linux/drivers/gpu/drm/arm/display/komeda/ |
| H A D | komeda_pipeline.c | 16 /** komeda_pipeline_add - Add a pipeline to &komeda_dev */
30 DRM_ERROR("Request pipeline size too small.\n"); in komeda_pipeline_add()
120 DRM_ERROR("Unknown pipeline resource ID: %d.\n", id); in komeda_pipeline_get_component_pos()
160 return komeda_pipeline_get_first_component(c->pipeline, avail_inputs); in komeda_component_pickup_input()
209 c->pipeline = pipe; in komeda_component_add()
257 DRM_INFO("Pipeline-%d: n_layers: %d, n_scalers: %d, output: %s.\n", in komeda_pipeline_dump()
276 struct komeda_pipeline *pipe = c->pipeline; in komeda_component_verify_inputs()
343 return slave ? slave->pipeline : NULL; in komeda_pipeline_get_slave()
367 seq_printf(sf, "\n======== Pipeline-%d ==========\n", pipe->id); in komeda_pipeline_dump_register()
|
| /linux/drivers/net/ipa/ |
| H A D | ipa_cmd.h | 107 * @clear_full: Pipeline clear option; true means full pipeline clear
124 * ipa_cmd_pipeline_clear_add() - Add pipeline clear commands to a transaction
130 * ipa_cmd_pipeline_clear_count() - # commands required to clear pipeline
133 * to hold commands to clear the pipeline
138 * ipa_cmd_pipeline_clear_wait() - Wait pipeline clear to complete
|
| /linux/Documentation/admin-guide/media/ |
| H A D | qcom_camss.rst | 38 - 1 / 2 VFE (Video Front End) module(s). Contain a pipeline of image processing
40 interface feeds the input data to the image processing pipeline. The image
41 processing pipeline contains also a scale and crop module at the end. Three
43 pipeline. The VFE also contains the AXI bus interface which writes the output
137 The media controller pipeline graph is as follows (with connected two / three
146 Media pipeline graph 8x16
152 Media pipeline graph 8x96
|