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/linux/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/
H A Dpipeline.json9 "PublicDescription": "This event counts valid cycles of EAGA pipeline.",
12 "BriefDescription": "This event counts valid cycles of EAGA pipeline."
15 "PublicDescription": "This event counts valid cycles of EAGB pipeline.",
18 "BriefDescription": "This event counts valid cycles of EAGB pipeline."
21 "PublicDescription": "This event counts valid cycles of EXA pipeline.",
24 "BriefDescription": "This event counts valid cycles of EXA pipeline."
27 "PublicDescription": "This event counts valid cycles of EXB pipeline.",
30 "BriefDescription": "This event counts valid cycles of EXB pipeline."
33 "PublicDescription": "This event counts valid cycles of FLA pipeline.",
36 "BriefDescription": "This event counts valid cycles of FLA pipeline."
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/linux/drivers/gpu/drm/xen/
H A Dxen_drm_front_kms.c94 static void send_pending_event(struct xen_drm_front_drm_pipeline *pipeline) in send_pending_event() argument
96 struct drm_crtc *crtc = &pipeline->pipe.crtc; in send_pending_event()
101 if (pipeline->pending_event) in send_pending_event()
102 drm_crtc_send_vblank_event(crtc, pipeline->pending_event); in send_pending_event()
103 pipeline->pending_event = NULL; in send_pending_event()
111 struct xen_drm_front_drm_pipeline *pipeline = in display_enable() local
120 ret = xen_drm_front_mode_set(pipeline, crtc->x, crtc->y, in display_enable()
127 pipeline->conn_connected = false; in display_enable()
135 struct xen_drm_front_drm_pipeline *pipeline = in display_disable() local
140 ret = xen_drm_front_mode_set(pipeline, 0, 0, 0, 0, 0, in display_disable()
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H A Dxen_drm_front_conn.c50 struct xen_drm_front_drm_pipeline *pipeline = in connector_detect() local
54 pipeline->conn_connected = false; in connector_detect()
56 return pipeline->conn_connected ? connector_status_connected : in connector_detect()
64 struct xen_drm_front_drm_pipeline *pipeline = in connector_get_modes() local
75 videomode.hactive = pipeline->width; in connector_get_modes()
76 videomode.vactive = pipeline->height; in connector_get_modes()
105 struct xen_drm_front_drm_pipeline *pipeline = in xen_drm_front_conn_init() local
110 pipeline->conn_connected = true; in xen_drm_front_conn_init()
/linux/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/
H A Dpipeline.json5 "BriefDescription": "This event counts valid cycles of EAGA pipeline."
10 "BriefDescription": "This event counts valid cycles of EAGB pipeline."
15 "BriefDescription": "This event counts valid cycles of PRX pipeline."
20 "BriefDescription": "This event counts valid cycles of EXA pipeline."
25 "BriefDescription": "This event counts valid cycles of EXB pipeline."
30 "BriefDescription": "This event counts valid cycles of EXC pipeline."
35 "BriefDescription": "This event counts valid cycles of EXD pipeline."
40 "BriefDescription": "This event counts valid cycles of FLA pipeline."
45 "BriefDescription": "This event counts valid cycles of FLB pipeline."
50 "BriefDescription": "This event counts valid cycles of STEA pipeline."
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/linux/drivers/isdn/mISDN/
H A Ddsp_pipeline.c163 int dsp_pipeline_init(struct dsp_pipeline *pipeline) in dsp_pipeline_init() argument
165 if (!pipeline) in dsp_pipeline_init()
168 INIT_LIST_HEAD(&pipeline->list); in dsp_pipeline_init()
173 static inline void _dsp_pipeline_destroy(struct dsp_pipeline *pipeline) in _dsp_pipeline_destroy() argument
177 list_for_each_entry_safe(entry, n, &pipeline->list, list) { in _dsp_pipeline_destroy()
180 dsp_hwec_disable(container_of(pipeline, struct dsp, in _dsp_pipeline_destroy()
181 pipeline)); in _dsp_pipeline_destroy()
188 void dsp_pipeline_destroy(struct dsp_pipeline *pipeline) in dsp_pipeline_destroy() argument
191 if (!pipeline) in dsp_pipeline_destroy()
194 _dsp_pipeline_destroy(pipeline); in dsp_pipeline_destroy()
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/linux/Documentation/gpu/
H A Dkomeda-kms.rst15 architecture. A display pipeline is made up of multiple individual and
16 functional pipeline stages called components, and every component has some
17 specific capabilities that can give the flowed pipeline pixel data a
24 Layer is the first pipeline stage, which prepares the pixel data for the next
58 Final stage of display pipeline, Timing controller is not for the pixel
76 Possible D71 Pipeline usage
94 Single pipeline data flow
98 :alt: Single pipeline digraph
99 :caption: Single pipeline data flow
140 Dual pipeline with Slave enabled
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/linux/tools/perf/pmu-events/arch/powerpc/power10/
H A Dpipeline.json5 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered a TLB miss or…
55 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load…
60 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline finished at dispatch a…
85 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load…
90 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the s…
95 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a lwsync waiting t…
135 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was dispatched but not…
150 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the L…
155 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline required special handl…
165 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load…
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/linux/drivers/net/wireless/ti/wl18xx/
H A Ddebugfs.c143 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, hs_tx_stat_fifo_int, "%u");
144 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, enc_tx_stat_fifo_int, "%u");
145 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, enc_rx_stat_fifo_int, "%u");
146 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, rx_complete_stat_fifo_int, "%u");
147 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, pre_proc_swi, "%u");
148 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, post_proc_swi, "%u");
149 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, sec_frag_swi, "%u");
150 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, pre_to_defrag_swi, "%u");
151 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, defrag_to_rx_xfer_swi, "%u");
152 WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, dec_packet_in, "%u");
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/linux/sound/soc/sof/
H A Dipc4-pcm.c84 /* trigger a single pipeline */ in sof_ipc4_set_multi_pipeline_state()
103 /* ipc_size includes the count and the pipeline IDs for the number of pipelines */ in sof_ipc4_set_multi_pipeline_state()
116 dev_dbg(sdev->dev, "Set pipeline %d to state %d%s", instance_id, state, in sof_ipc4_set_pipeline_state()
135 struct sof_ipc4_pipeline *pipeline = pipe_widget->private; in sof_ipc4_add_pipeline_by_priority() local
139 /* add pipeline from low priority to high */ in sof_ipc4_add_pipeline_by_priority()
140 if (ascend && pipeline->priority < pipe_priority[i]) in sof_ipc4_add_pipeline_by_priority()
142 /* add pipeline from high priority to low */ in sof_ipc4_add_pipeline_by_priority()
143 else if (!ascend && pipeline->priority > pipe_priority[i]) in sof_ipc4_add_pipeline_by_priority()
154 pipe_priority[i] = pipeline->priority; in sof_ipc4_add_pipeline_by_priority()
164 struct sof_ipc4_pipeline *pipeline in sof_ipc4_add_pipeline_to_trigger_list() local
202 struct sof_ipc4_pipeline *pipeline = pipe_widget->private; sof_ipc4_update_pipeline_state() local
358 struct sof_ipc4_pipeline *pipeline = pipe_widget->private; sof_ipc4_chain_dma_trigger() local
410 struct sof_ipc4_pipeline *pipeline; sof_ipc4_trigger_pipelines() local
765 struct sof_ipc4_pipeline *pipeline = pipe_widget->private; sof_ipc4_pcm_dai_link_fixup() local
[all...]
H A Dipc4-topology.c190 [SOF_PIPELINE_TOKENS] = {"Pipeline tokens", pipeline_tokens, ARRAY_SIZE(pipeline_tokens)}, in sof_ipc4_find_swidget_by_ids()
571 struct sof_ipc4_pipeline *pipeline = pipe_widget->private; in sof_ipc4_widget_setup_pcm()
581 if (!pipeline->use_chain_dma) in sof_ipc4_widget_setup_pcm()
742 struct sof_ipc4_pipeline *pipeline; in sof_ipc4_widget_setup_comp_dai()
782 pipeline = pipe_widget->private; in sof_ipc4_widget_setup_comp_dai()
784 if (pipeline->use_chain_dma && in sof_ipc4_widget_setup_comp_dai()
915 struct sof_ipc4_pipeline *pipeline; in sof_ipc4_widget_setup_comp_pipeline()
919 pipeline = kzalloc(sizeof(*pipeline), GFP_KERNEL); in sof_ipc4_widget_setup_comp_pipeline()
920 if (!pipeline) in sof_ipc4_widget_setup_comp_pipeline()
529 struct sof_ipc4_pipeline *pipeline = pipe_widget->private; sof_ipc4_update_card_components_string() local
700 struct sof_ipc4_pipeline *pipeline; sof_ipc4_widget_setup_comp_dai() local
873 struct sof_ipc4_pipeline *pipeline; sof_ipc4_widget_setup_comp_pipeline() local
1236 struct sof_ipc4_pipeline *pipeline; sof_ipc4_update_resource_usage() local
1508 struct sof_ipc4_pipeline *pipeline; sof_ipc4_unprepare_copier_module() local
1895 struct sof_ipc4_pipeline *pipeline = pipe_widget->private; sof_ipc4_prepare_copier_module() local
1972 struct sof_ipc4_pipeline *pipeline = pipe_widget->private; sof_ipc4_prepare_copier_module() local
2791 struct sof_ipc4_pipeline *pipeline; sof_ipc4_widget_setup() local
2973 struct sof_ipc4_pipeline *pipeline = swidget->private; sof_ipc4_widget_free() local
3002 struct sof_ipc4_pipeline *pipeline = pipe_widget->private; sof_ipc4_widget_free() local
3305 struct sof_ipc4_pipeline *pipeline = pipe_widget->private; sof_ipc4_dai_config() local
[all...]
/linux/drivers/gpu/drm/arm/display/komeda/
H A Dkomeda_pipeline.h21 /* pipeline component IDs */
76 * component into the display pipeline.
82 /** @pipeline: the komeda pipeline this component belongs to */
83 struct komeda_pipeline *pipeline; member
119 * pipeline.
385 * Represent a complete display pipeline and hold all functional components.
388 /** @obj: link pipeline as private obj of drm_atomic_state */
394 /** @id: pipeline id */
396 /** @avail_comps: available components mask of pipeline */
401 * When disable the pipeline, some components can not be disabled
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H A Dkomeda_pipeline.c16 /** komeda_pipeline_add - Add a pipeline to &komeda_dev */
30 DRM_ERROR("Request pipeline size too small.\n"); in komeda_pipeline_add()
120 DRM_ERROR("Unknown pipeline resource ID: %d.\n", id); in komeda_pipeline_get_component_pos()
160 return komeda_pipeline_get_first_component(c->pipeline, avail_inputs); in komeda_component_pickup_input()
209 c->pipeline = pipe; in komeda_component_add()
257 DRM_INFO("Pipeline-%d: n_layers: %d, n_scalers: %d, output: %s.\n", in komeda_pipeline_dump()
276 struct komeda_pipeline *pipe = c->pipeline; in komeda_component_verify_inputs()
343 return slave ? slave->pipeline : NULL; in komeda_pipeline_get_slave()
367 seq_printf(sf, "\n======== Pipeline-%d ==========\n", pipe->id); in komeda_pipeline_dump_register()
/linux/drivers/media/platform/xilinx/
H A Dxilinx-dma.h29 * struct xvip_pipeline - Xilinx Video IP pipeline structure
30 * @pipe: media pipeline
31 * @lock: protects the pipeline @stream_count
32 * @use_count: number of DMA engines using the pipeline
34 * @num_dmas: number of DMA engines in the pipeline
35 * @output: DMA engine at the output of the pipeline
64 * @pipe: pipeline belonging to the DMA channel
/linux/tools/perf/pmu-events/arch/x86/amdzen4/
H A Dcache.json448 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L…
454 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L…
460 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L…
466 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L…
472 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L…
478 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L…
484 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L…
490 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L…
496 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of all ty…
502 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in …
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/linux/drivers/gpu/drm/msm/adreno/
H A Dadreno_gen7_0_0_snapshot.h306 /* Block: GRAS Cluster: A7XX_CLUSTER_GRAS Pipeline: A7XX_PIPE_BR */
316 /* Block: GRAS Cluster: A7XX_CLUSTER_GRAS Pipeline: A7XX_PIPE_BV */
326 /* Block: PC Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BR */
334 /* Block: PC Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BV */
342 /* Block: RB_RAC Cluster: A7XX_CLUSTER_PS Pipeline: A7XX_PIPE_BR */
358 /* Block: RB_RBP Cluster: A7XX_CLUSTER_PS Pipeline: A7XX_PIPE_BR */
373 /* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BR Location: HLSQ_STATE */
384 /* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_LPAC Location: HLSQ_STATE */
393 /* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BR Location: HLSQ_DP */
400 /* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_LPAC Location: HLSQ_DP */
[all …]
H A Dadreno_gen7_9_0_snapshot.h229 * Pipeline: A7XX_PIPE_NONE
293 * Pipeline: A7XX_PIPE_NONE
337 * Pipeline: A7XX_PIPE_NONE
358 * Pipeline: A7XX_PIPE_NONE
370 * Pipeline: A7XX_PIPE_NONE
385 * Pipeline: A7XX_PIPE_NONE
399 * Pipeline: A7XX_PIPE_BR
420 * Pipeline: A7XX_PIPE_BV
441 * Pipeline: A7XX_PIPE_LPAC
453 * Pipeline: A7XX_PIPE_BR
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/linux/sound/soc/sof/intel/
H A Dhda-dai-ops.c130 struct sof_ipc4_pipeline *pipeline; in hda_ipc4_get_hext_stream() local
137 pipeline = pipe_widget->private; in hda_ipc4_get_hext_stream()
139 /* mark pipeline so that it can be skipped during FE trigger */ in hda_ipc4_get_hext_stream()
140 pipeline->skip_during_fe_trigger = true; in hda_ipc4_get_hext_stream()
301 struct sof_ipc4_pipeline *pipeline; in hda_ipc4_pre_trigger() local
309 pipeline = pipe_widget->private; in hda_ipc4_pre_trigger()
328 pipeline->state = SOF_IPC4_PIPE_PAUSED; in hda_ipc4_pre_trigger()
378 struct sof_ipc4_pipeline *pipeline; in hda_ipc4_post_trigger() local
386 pipeline = pipe_widget->private; in hda_ipc4_post_trigger()
395 if (pipeline->state != SOF_IPC4_PIPE_PAUSED) { in hda_ipc4_post_trigger()
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/linux/Documentation/driver-api/media/
H A Dmc-core.rst24 in a System-on-Chip image processing pipeline), DMA channels or physical
199 A media pipeline is a set of media streams which are interdependent. This
202 due to the software design. Most commonly a media pipeline consists of a single
205 When starting streaming, drivers must notify all entities in the pipeline to
209 The function will mark all the pads which are part of the pipeline as streaming.
212 stored in every pad in the pipeline. Drivers should embed the struct
213 media_pipeline in higher-level pipeline structures and can then access the
214 pipeline through the struct media_pad pipe field.
217 The pipeline pointer must be identical for all nested calls to the function.
244 for any entity which has sink pads in the pipeline. The
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/linux/Documentation/devicetree/bindings/display/
H A Darm,komeda.yaml15 to a 4K resolution each. Each pipeline can be composed of up to four
59 '^pipeline@[01]$':
90 - pipeline@0
107 dp0_pipe0: pipeline@0 {
119 dp0_pipe1: pipeline@1 {
/linux/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_cmd_encoder.c129 struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc); in mdp5_cmd_encoder_disable() local
136 mdp5_ctl_set_encoder_state(ctl, pipeline, false); in mdp5_cmd_encoder_disable()
137 mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true); in mdp5_cmd_encoder_disable()
147 struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc); in mdp5_cmd_encoder_enable() local
155 mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true); in mdp5_cmd_encoder_enable()
157 mdp5_ctl_set_encoder_state(ctl, pipeline, true); in mdp5_cmd_encoder_enable()
/linux/include/media/
H A Dv4l2-mc.h51 * start a pipeline between the media source and the media
67 * active media pipeline between the media source and the
143 * v4l2_pipeline_pm_get - Increase the use count of a pipeline
144 * @entity: The root entity of a pipeline
149 * Update the use count of all entities in the pipeline and power entities on.
160 * v4l2_pipeline_pm_put - Decrease the use count of a pipeline
161 * @entity: The root entity of a pipeline
166 * Update the use count of all entities in the pipeline and power entities off.
/linux/drivers/net/ipa/
H A Dipa_cmd.h107 * @clear_full: Pipeline clear option; true means full pipeline clear
124 * ipa_cmd_pipeline_clear_add() - Add pipeline clear commands to a transaction
130 * ipa_cmd_pipeline_clear_count() - # commands required to clear pipeline
133 * to hold commands to clear the pipeline
138 * ipa_cmd_pipeline_clear_wait() - Wait pipeline clear to complete
/linux/drivers/media/platform/microchip/
H A Dmicrochip-isc.h78 /* Pipeline bitmap */
98 * struct fmt_config - ISC format configuration and internal pipeline
112 * @bits_pipeline: Configuration of the pipeline, which modules are enabled
236 * @pipeline: configuration of the ISC pipeline
263 * @adapt_pipeline: pointer to a function that adapts the pipeline bits
264 * to the product specific pipeline
275 * @mpipe: media device pipeline used by the isc
314 struct regmap_field *pipeline[ISC_PIPE_LINE_NODE_NUM]; member
/linux/Documentation/admin-guide/media/
H A Dqcom_camss.rst38 - 1 / 2 VFE (Video Front End) module(s). Contain a pipeline of image processing
40 interface feeds the input data to the image processing pipeline. The image
41 processing pipeline contains also a scale and crop module at the end. Three
43 pipeline. The VFE also contains the AXI bus interface which writes the output
137 The media controller pipeline graph is as follows (with connected two / three
146 Media pipeline graph 8x16
152 Media pipeline graph 8x96
/linux/drivers/staging/media/atomisp/
H A Dnotes.txt5 pipeline. It does not have its own memory, but instead uses main memory.
14 The actual processing pipeline is made by loading one or more programs,
25 So in this case a single binary handles the entire pipeline.
29 on the ISP can do multiple processing steps in a single pipeline

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