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/linux/drivers/i2c/busses/
H A Di2c-mxs.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
6 * Copyright (C) 2011-2012 Wolfram Sang, Pengutronix e.K.
8 * based on a (non-working) driver which was:
10 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
25 #include <linux/dma-mapping.h>
27 #include <linux/dma/mxs-dma.h>
29 #define DRIVER_NAME "mxs-i2c"
69 #define MXS_I2C_DATA(i2c) ((i2c->dev_type == MXS_I2C_V1) ? 0x60 : 0xa0)
71 #define MXS_I2C_DEBUG0_CLR(i2c) ((i2c->dev_type == MXS_I2C_V1) ? 0x78 : 0xb8)
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/linux/drivers/net/wireless/broadcom/b43legacy/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "Broadcom 43xx-legacy wireless support (mac80211 stack)"
18 b43-fwcutter.
23 # Auto-select SSB PCI-HOST support, if possible
31 # Auto-select SSB PCICORE driver, if possible
46 # This config option automatically enables b43 HW-RNG support,
47 # if the HW-RNG core is enabled.
54 bool "Broadcom 43xx-legacy debugging"
70 prompt "Broadcom 43xx-legacy data transfer mode"
75 bool "DMA + PIO"
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/linux/include/linux/
H A Dcb710.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright by Michał Mirosław, 2008-2009
21 /* per-virtual-slot structure */
28 /* per-device structure */
50 /* slot port accessors - so the logic is more clear in the code */
55 iowrite##t(value, slot->iobase + port); \
61 return ioread##t(slot->iobase + port); \
68 (ioread##t(slot->iobase + port) & ~clear)|set, \
69 slot->iobase + port); \
91 return dev_get_drvdata(slot->pdev.dev.parent); in cb710_slot_to_chip()
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/linux/drivers/net/wireless/broadcom/b43/
H A Dpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 PIO data transfer
8 Copyright (c) 2005-2008 Michael Buesch <m@bues.ch>
14 #include "pio.h"
30 * PIO controller ID and store the packet index number in generate_cookie()
37 cookie = (((u16)q->index + 1) << 12); in generate_cookie()
38 cookie |= pack->index; in generate_cookie()
48 struct b43_pio *pio = &dev->pio; in parse_cookie() local
54 q = pio->tx_queue_AC_BK; in parse_cookie()
57 q = pio->tx_queue_AC_BE; in parse_cookie()
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/linux/arch/mips/include/asm/sgi/
H A Dhpc3.h40 u32 _unused0[0x1000/4 - 2]; /* padding */
48 #define HPC3_PDMACTRL_SEL 0x00000002 /* little endian transfer */
51 #define HPC3_PDMACTRL_ACT 0x00000010 /* start dma transfer */
54 #define HPC3_PDMACTRL_HW 0x0000ff00 /* DMA High-water mark */
58 u32 _unused1[0x1000/4 - 1]; /* padding */
65 u32 _unused0[0x1000/4 - 2]; /* padding */
67 #define HPC3_SBCD_BCNTMSK 0x00003fff /* bytes to transfer from/to memory */
77 #define HPC3_SCTRL_AMASK 0x20 /* DMA active inhibits PIO */
89 #define HPC3_SDCFG_HW 0x01000 /* Enable 16-bit halfword DMA accesses to scsi */
95 volatile u32 pconfig; /* PIO configuration register */
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/linux/drivers/ata/
H A Dpata_pdc202xx_old.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_pdc202xx_old.c - Promise PDC202xx PATA for new ATA layer
29 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in pdc2026x_cable_detect()
33 if (cis & (1 << (10 + ap->port_no))) in pdc2026x_cable_detect()
41 iowrite8(tf->command, ap->ioaddr.command_addr); in pdc202xx_exec_command()
47 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in pdc202xx_irq_check()
51 if (ap->port_no) { in pdc202xx_irq_check()
67 * pdc202xx_configure_piomode - set chip PIO timing
70 * @pio: PIO mode
72 * Called to do the PIO mode setup. Our timing registers are shared
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H A Dlibata-sff.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * libata-sff.c - helper library for PCI IDE BMDMA
5 * Copyright 2003-2006 Red Hat, Inc. All rights reserved.
6 * Copyright 2003-2006 Jeff Garzik
9 * as Documentation/driver-api/libata.rst
12 * http://www.sata-io.org/
53 * ata_sff_check_status - Read device status reg & clear interrupt
56 * Reads ATA taskfile status register for currently-selected device
65 return ioread8(ap->ioaddr.status_addr); in ata_sff_check_status()
70 * ata_sff_altstatus - Read device alternate status reg
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H A Dpata_ns87415.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_ns87415.c - NS87415 (and PARISC SUPERIO 87560) PATA
8 * as it requires timing reloads on PIO/DMA transitions but it is otherwise
20 * Implement lazy pio/dma switching for better performance
39 * ns87415_set_mode - Initialize host controller mode timings
46 * for PIO/DMA switches.
54 struct pci_dev *dev = to_pci_dev(ap->host->dev); in ns87415_set_mode()
55 int unit = 2 * ap->port_no + adev->devno; in ns87415_set_mode()
63 /* Timing register format is 17 - low nybble read timing with in ns87415_set_mode()
64 the high nybble being 16 - x for recovery time in PCI clocks */ in ns87415_set_mode()
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H A Dpata_atiixp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_atiixp.c - ATI PATA for new ATA layer
5 * (C) 2009-2010 Bartlomiej Zolnierkiewicz
9 * linux/drivers/ide/pci/atiixp.c Version 0.01-bart2 Feb. 26, 2004
39 /* Board has onboard PATA<->SATA converters */
40 .ident = "MSI E350DM-E33",
43 DMI_MATCH(DMI_BOARD_NAME, "E350DM-E33(MS-7720)"),
51 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in atiixp_cable_detect()
59 pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ap->port_no, &udma); in atiixp_cable_detect()
68 * atiixp_prereset - perform reset handling
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H A Dpata_sl82c105.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_sl82c105.c - SL82C105 PATA for new ATA layer
14 * PIO and DMA. We thus flip to the DMA timings in dma_start and flip back
16 * method as the PIO method is always called and will set the right PIO
45 * sl82c105_pre_reset - probe begin
58 struct ata_port *ap = link->ap; in sl82c105_pre_reset()
59 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in sl82c105_pre_reset()
61 if (ap->port_no && !pci_test_config_bits(pdev, &sl82c105_enable_bits[ap->port_no])) in sl82c105_pre_reset()
62 return -ENOENT; in sl82c105_pre_reset()
68 * sl82c105_configure_piomode - set chip PIO timing
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/linux/drivers/scsi/arm/
H A Darxescsi.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 1997-2000 Russell King, Stefan Hanske
12 * 30-08-1997 RMK 0.0.0 Created, READONLY version as cumana_2.c
13 * 22-01-1998 RMK 0.0.1 Updated to 2.1.80
14 * 15-04-1998 RMK 0.0.1 Only do PIO if FAS216 will allow it.
15 * 11-06-1998 SH 0.0.2 Changed to support ARXE 16-bit SCSI card
17 * 01-01-2000 SH 0.1.0 Added *real* pseudo dma writing
19 * 02-04-2000 RMK 0.1.1 Updated for new error handling code.
20 * 22-10-2000 SH Updated for new registering scheme.
63 * Purpose : initialises DMA/PIO
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H A Dcumana_2.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 1997-2005 Russell King
8 * 30-08-1997 RMK 0.0.0 Created, READONLY version.
9 * 22-01-1998 RMK 0.0.1 Updated to 2.1.80.
10 * 15-04-1998 RMK 0.0.1 Only do PIO if FAS216 will allow it.
11 * 02-05-1998 RMK 0.0.2 Updated & added DMA support.
12 * 27-06-1998 RMK Changed asm/delay.h to linux/delay.h
13 * 18-08-1998 RMK 0.0.3 Fixed synchronous transfer depth.
14 * 02-04-2000 RMK 0.0.4 Updated for new error handling code.
25 #include <linux/dma-mapping.h>
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/linux/arch/sparc/kernel/
H A Dsbus.c1 // SPDX-License-Identifier: GPL-2.0
37 #define IOMMU_CONTROL (0x2400UL - 0x2400UL) /* IOMMU control register */
38 #define IOMMU_TSBBASE (0x2408UL - 0x2400UL) /* TSB base address register */
39 #define IOMMU_FLUSH (0x2410UL - 0x2400UL) /* IOMMU flush register */
40 #define IOMMU_VADIAG (0x4400UL - 0x2400UL) /* SBUS virtual address diagnostic */
41 #define IOMMU_TAGCMP (0x4408UL - 0x2400UL) /* TLB tag compare diagnostics */
42 #define IOMMU_LRUDIAG (0x4500UL - 0x2400UL) /* IOMMU LRU queue diagnostics */
43 #define IOMMU_TAGDIAG (0x4580UL - 0x2400UL) /* TLB tag diagnostics */
44 #define IOMMU_DRAMDIAG (0x4600UL - 0x2400UL) /* TLB data RAM diagnostics */
50 #define STRBUF_CONTROL (0x2800UL - 0x2800UL) /* Control */
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H A Dpci_psycho.c1 // SPDX-License-Identifier: GPL-2.0
99 #define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
100 #define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
101 #define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
102 #define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
103 #define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
104 #define PSYCHO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
105 #define PSYCHO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
106 #define PSYCHO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */
121 #define PSYCHO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */
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/linux/Documentation/driver-api/
H A Dlibata.rst12 transports for ATA and ATAPI devices, and SCSI<->ATA translation for ATA
16 internals, and a couple sample ATA low-level drivers.
22 is defined for every low-level libata
23 hardware driver, and it controls how the low-level driver interfaces
26 FIS-based drivers will hook into the system with ``->qc_prep()`` and
27 ``->qc_issue()`` high-level hooks. Hardware which behaves in a manner
33 ----------------------------------------------------------
35 Post-IDENTIFY device configuration
44 Typically used to apply device-specific fixups prior to issue of SET
45 FEATURES - XFER MODE, and prior to operation.
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/linux/Documentation/devicetree/bindings/ata/
H A Data-generic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ata-generic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
13 Generic Parallel ATA controllers supporting PIO modes only.
18 - enum:
19 - arm,vexpress-cf
20 - fsl,mpc8349emitx-pata
21 - const: ata-generic
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/linux/drivers/usb/musb/
H A Dtusb6010_omap.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/dma-mapping.h>
20 #define to_chdat(c) ((struct tusb_omap_dma_ch *)(c)->private_data)
63 u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); in tusb_omap_use_shared_dmareq()
66 dev_dbg(chdat->musb->controller, "ep%i dmareq0 is busy for ep%i\n", in tusb_omap_use_shared_dmareq()
67 chdat->epnum, reg & 0xf); in tusb_omap_use_shared_dmareq()
68 return -EAGAIN; in tusb_omap_use_shared_dmareq()
71 if (chdat->tx) in tusb_omap_use_shared_dmareq()
72 reg = (1 << 4) | chdat->epnum; in tusb_omap_use_shared_dmareq()
74 reg = chdat->epnum; in tusb_omap_use_shared_dmareq()
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/linux/sound/soc/dwc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
14 bool "PCM PIO extension for I2S driver"
18 a PCM and uses PIO to transfer data.
/linux/include/uapi/rdma/hfi/
H A Dhfi1_ioctl.h1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
28 * - Redistributions of source code must retain the above copyright
30 * - Redistributions in binary form must reproduce the above copyright
34 * - Neither the name of Intel Corporation nor the names of its
89 __u16 credits; /* number of PIO credits for this context */
100 /* virtual address of first page in transfer */
106 /* length of transfer buffer programmed by this request */
112 * open to get implementation-specific info, and info specific to this
133 /* PIO credit return address, */
136 * Base address of write-only pio buffers for this process.
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/linux/drivers/scsi/isci/
H A Drequest.h7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
64 * isci_stp_request - extra request infrastructure to handle pio/atapi protocol
65 * @pio_len - number of bytes requested at PIO setup
66 * @status - pio setup ending status value to tell us if we need
67 * to wait for another fis or if the transfer is complete. Upon
69 * @sgl - track pio transfer progress as we iterate through the sgl
103 * - TMF requests are completed in the thread that started them;
104 * - regular requests are completed in the request completion callback
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/linux/drivers/hid/intel-thc-hid/intel-thc/
H A Dintel-thc-dev.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include "intel-thc-dma.h"
12 #include "intel-thc-wot.h"
29 * @THC_NONDMA_INT: THC non-DMA interrupt
34 * @THC_PIO_DONE_INT: THC PIO complete interrupt
36 * @THC_TXN_ERR_INT: THC transfer error interrupt
53 * struct thc_device - THC private device struct
58 * @pio_int_supported: PIO interrupt supported flag
60 * @wot: THC Wake-on-Touch data
66 * @i2c_subip_regs: The copy of THC I2C sub-system registers for resuming restore
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/linux/drivers/spi/
H A Dspi-ep93xx.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010-2011 Mika Westerberg
7 * Explicit FIFO handling code was inspired by amba-pl022 driver.
9 * Chip select support using other than built-in GPIOs by H. Hartley Sweeten.
21 #include <linux/dma-direction.h>
22 #include <linux/dma-mapping.h>
69 * struct ep93xx_spi - EP93xx SPI controller structure
73 * @tx: current byte in transfer to transmit
74 * @rx: current byte in transfer to receive
75 * @fifo_level: how full is FIFO (%0..%SPI_FIFO_SIZE - %1). Receiving one
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/linux/Documentation/hid/
H A Dintel-thc-hid.rst1 .. SPDX-License-Identifier: GPL-2.0
10 - A natively half-duplex Quad I/O capable SPI master
11 - Low latency I2C interface to support HIDI2C compliant devices
12 - A HW sequencer with RW DMA capability to system memory
29 -------------------------------
31 Below diagram illustrates the high-level architecture of THC software/hardware stack, which is fully
36 ----------------------------------------------
37 | +-----------------------------------+ |
39 | +-----------------------------------+ |
40 | +-----------------------------------+ |
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/linux/include/linux/spi/
H A Dspi_bitbang.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 u16 flags; /* extra spi->mode support */
18 * for this transfer; zeroes restore defaults from spi_device.
29 * already have one (transfer.{tx,rx}_dma is zero), or use PIO
39 /* you can call these default bitbang->master methods from your custom
/linux/drivers/pci/controller/
H A Dpci-aardvark.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/irqchip/irq-msi-lib.h>
21 #include <linux/pci-ecam.h>
30 #include "../pci-bridge-emul.h"
44 /* PIO registers base address and register offsets */
140 #define OB_WIN_DEFAULT_ACTIONS (OB_WIN_ACTIONS(OB_WIN_COUNT-1) + 0x4)
294 writel(val, pcie->base + reg); in advk_writel()
299 return readl(pcie->base + reg); in advk_readl()
314 /* check if LTSSM is in normal operation - some L* state */ in advk_pcie_link_up()
322 * According to PCIe Base specification 3.0, Table 4-14: Link in advk_pcie_link_active()
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