Lines Matching +full:pio +full:- +full:transfer

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
17 #include <linux/fault-inject.h>
60  * struct dw_mci - MMC controller state shared between all slots
65  * @sg: Scatterlist entry currently being processed by PIO code, if any.
66  * @sg_miter: PIO mapping scatterlist iterator.
71  *	transfer is in progress.
72  * @stop_abort: The command currently prepared for stoping transfer.
73  * @prev_blksz: The former transfer blksz record.
75  * @use_dma: Which DMA channel is in use for the current transfer, zero
76  *	denotes PIO mode.
77  * @using_dma: Whether DMA is in use for the current transfer.
78  * @dma_64bit_address: Whether DMA supports 64-bit address mode or not.
81  * @dma_ops: Pointer to platform-specific DMA callbacks.
85  * @dms: structure of slave-dma private data.
88  *	data transfer. Only valid when EVENT_DATA_COMPLETE or
92  * @dir_status: Direction of current transfer.
115  * @wm_aligned: force fifo watermark equal with data length in PIO mode.
129  * @cto_timer: Timer for broken command transfer over scheme.
130  * @dto_timer: Timer for broken data transfer over scheme.
135  * @lock is a softirq-safe spinlock protecting @queue as well as
142  * @irq_lock is an irq-safe spinlock protecting the INTMASK register
144  * enough to read-modify-write INTMASK and no other locks are grabbed when
152  * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
284 /* Force 32-bit access to the FIFO */
334  * Registers to support idmac 64-bit address mode
371 /* time-out register defines */
376 /* card-type register defines */
455 /* UHS-1 register defines */
466 /* FIFO register access macros. These should not change the data endian-ness
478  * Some dw_mmc devices have 64-bit FIFOs, but expect them to be
479  * accessed using two 32-bit accesses. If such controller is used
480  * with a 64-bit kernel, this has to be done explicitly.
504 	readl_relaxed((dev)->regs + SDMMC_##reg)
506 	writel_relaxed((value), (dev)->regs + SDMMC_##reg)
508 /* 16-bit FIFO access macros */
510 	readw_relaxed((dev)->regs + SDMMC_##reg)
512 	writew_relaxed((value), (dev)->regs + SDMMC_##reg)
514 /* 64-bit FIFO access macros */
517 	readq_relaxed((dev)->regs + SDMMC_##reg)
519 	writeq_relaxed((value), (dev)->regs + SDMMC_##reg)
530 	(*(volatile u64 __force *)((dev)->regs + SDMMC_##reg))
532 	(*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value))
547  * struct dw_mci_slot - MMC slot state
555  * @clock: Clock rate configured by set_ios(). Protected by host->lock.
585  * dw_mci driver data - dw-mshc implementation specific driver data.