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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmediatek,mt65xx-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@kernel.org>
13 The MediaTek's MT65xx Pin controller is used to control SoC pins.
18 - mediatek,mt2701-pinctrl
19 - mediatek,mt2712-pinctrl
20 - mediatek,mt6397-pinctrl
21 - mediatek,mt7623-pinctrl
[all …]
H A Dsunplus,sp7021-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/sunplus,sp7021-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Dvorkin Dmitry <dvorkin@tibbo.com>
12 - Wells Lu <wellslutw@gmail.com>
15 The Sunplus SP7021 pin controller is used to control SoC pins. Please
16 refer to pinctrl-bindings.txt in this directory for details of the common
19 SP7021 has 99 digital GPIO pins which are numbered from GPIO 0 to 98. All
20 are multiplexed with some special function pins. SP7021 has 3 types of
[all …]
H A Dst,stm32-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre TORGUE <alexandre.torgue@foss.st.com>
15 controller. It controls the input/output settings on the available pins and
17 on-chip controllers onto these pads.
22 - st,stm32f429-pinctrl
23 - st,stm32f469-pinctrl
24 - st,stm32f746-pinctrl
[all …]
/linux/drivers/pinctrl/nomadik/
H A Dpinctrl-abx500.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 /* pins alternate function */
34 * struct abx500_function - ABx500 pinctrl mux function
46 * struct abx500_pingroup - describes a ABx500 pin group
48 * @pins: an array of discrete physical pins used in this group, taken
49 * from the driver-local pin enumeration space
50 * @num_pins: the number of pins in this group array, i.e. the number of
51 * elements in .pins so we can iterate over that array
52 * @altsetting: the altsetting to apply to all pins in this group to
57 const unsigned int *pins; member
[all …]
/linux/Documentation/iio/
H A Dad4695.rst1 .. SPDX-License-Identifier: GPL-2.0-only
14 The following chips are supported by this driver:
26 -----
[all...]
/linux/drivers/pinctrl/tegra/
H A Dpinctrl-tegra.h1 /* SPDX-License-Identifier: GPL-2.0-only */
47 /* argument: Integer, range is HW-dependant */
49 /* argument: Integer, range is HW-dependant */
51 /* argument: Integer, range is HW-dependant */
53 /* argument: Integer, range is HW-dependant */
55 /* argument: Integer, range is HW-dependant */
75 * struct tegra_function - Tegra pinctrl mux function
87 * struct tegra_pingroup - Tegra pin group
89 * @pins An array of pin IDs included in this pin group.
90 * @npins The number of entries in @pins.
[all …]
/linux/include/linux/gpio/
H A Dgpio-nomadik.h1 /* SPDX-License-Identifier: GPL-2.0 */
127 * Used to reference an Other alternate-C function.
138 * struct prcm_gpio_altcx - Other alternate-C function
139 * @used: other alternate-C function availability
150 * struct prcm_gpio_altcx_pin_desc - Other alternate-C pin
152 * @altcx: array of other alternate-C[1-4] functions
160 * struct nmk_function - Nomadik pinctrl mux function
172 * struct nmk_pingroup - describes a Nomadik pin group
173 * @grp: Generic data of the pin group (name and pins)
174 * @altsetting: the altsetting to apply to all pins in this group to
[all …]
/linux/arch/arm/boot/dts/st/
H A Dste-snowball.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011 ST-Ericsson AB
6 /dts-v1/;
7 #include "ste-db9500.dtsi"
8 #include "ste-href-ab8500.dtsi"
9 #include "ste-href-family-pinctrl.dtsi"
13 compatible = "calaosystems,snowball-a9500", "st-ericsson,u9500";
21 compatible = "simple-battery";
22 battery-type = "lithium-ion-polymer";
25 thermal-zones {
[all …]
/linux/drivers/pinctrl/spear/
H A Dpinctrl-spear.h26 * struct spear_pmx_mode - SPEAr pmx mode
42 * struct spear_muxreg - SPEAr mux reg configuration
54 const unsigned *pins; member
85 .pins = __pins, \
92 * struct spear_modemux - SPEAr mode mux configuration
104 * struct spear_pingroup - SPEAr pin group configurations
106 * @pins: array containing pin numbers
107 * @npins: size of pins array
111 * A representation of a group of pins in the SPEAr pin controller. Each group
116 const unsigned *pins; member
[all …]
/linux/arch/alpha/kernel/
H A Dsys_cabriolet.c1 // SPDX-License-Identifier: GPL-2.0
40 int ofs = (irq - 16) / 8; in cabriolet_update_irq_hw()
47 cabriolet_update_irq_hw(d->irq, cached_irq_mask &= ~(1UL << d->irq)); in cabriolet_enable_irq()
53 cabriolet_update_irq_hw(d->irq, cached_irq_mask |= 1UL << d->irq); in cabriolet_disable_irq()
78 pld &= pld - 1; /* clear least bit set */ in cabriolet_device_interrupt()
111 if (request_irq(16 + 4, no_action, 0, "isa-cascade", NULL)) in common_init_irq()
112 pr_err("Failed to register isa-cascade interrupt\n"); in common_init_irq()
162 * the on-board NCR and Tulip chips. In the code below, I have used
166 * that's printed on the board. The interrupt pins from the PCI slots
167 * are wired into 3 interrupt summary registers at 0x804, 0x805 and
[all …]
/linux/drivers/net/can/
H A Dti_hecc.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
28 #include <linux/can/rx-offload.h>
36 #define HECC_MAX_MAILBOXES 32 /* hardware mailboxes - do not change */
37 #define MAX_TX_PRIO 0x3F /* hardware value - do not change */
42 * for the mailbox logic to work. Top mailbox numbers are reserved for RX
55 #define HECC_TX_MB_MASK (HECC_MAX_TX_MBOX - 1)
56 #define HECC_TX_MASK ((HECC_MAX_TX_MBOX - 1) | HECC_TX_PRIO_MASK)
60 * The remaining mailboxes are used for reception and are delivered
62 * changed while CAN-bus traffic is being received.
[all …]
/linux/arch/mips/include/asm/sgi/
H A Dheart.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2004-2007 Stanislaw Skowronek <skylark@unaligned.org>
7 * 2007-2015 Joshua Kinard <kumba@gentoo.org>
16 * There are 8 DIMM slots on an IP30 system
17 * board, which are grouped into four banks
27 * struct ip30_heart_regs - struct that maps IP30 HEART registers.
28 * @mode: HEART_MODE - Purpose Unknown, machine reset called from here.
29 * @sdram_mode: HEART_SDRAM_MODE - purpose unknown.
30 * @mem_refresh: HEART_MEM_REF - purpose unknown.
31 * @mem_req_arb: HEART_MEM_REQ_ARB - purpose unknown.
[all …]
/linux/drivers/pinctrl/
H A Dpinmux.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2012 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
24 #include <linux/radix-tree.h>
38 const struct pinmux_ops *ops = pctldev->desc->pmxops; in pinmux_check_ops()
44 !ops->get_functions_count || in pinmux_check_ops()
45 !ops->get_function_name || in pinmux_check_ops()
46 !ops->get_function_groups || in pinmux_check_ops()
47 !ops->set_mux) { in pinmux_check_ops()
48 dev_err(pctldev->dev, "pinmux ops lacks necessary functions\n"); in pinmux_check_ops()
[all …]
/linux/drivers/usb/serial/
H A Dark3116.c1 // SPDX-License-Identifier: GPL-2.0+
9 * - implements a driver for the arkmicro ark3116 chipset (vendor=0x6547,
10 * productid=0x0232) (used in a datacable called KQ-U8A)
52 struct usb_device *dev = serial->dev; in is_irda()
53 if (le16_to_cpu(dev->descriptor.idVendor) == 0x18ec && in is_irda()
54 le16_to_cpu(dev->descriptor.idProduct) == 0x3118) in is_irda()
81 /* 0xfe 0x40 are magic values taken from original driver */ in ark3116_write_reg()
82 result = usb_control_msg(serial->dev, in ark3116_write_reg()
83 usb_sndctrlpipe(serial->dev, 0), in ark3116_write_reg()
96 /* 0xfe 0xc0 are magic values taken from original driver */ in ark3116_read_reg()
[all …]
/linux/drivers/pinctrl/starfive/
H A Dpinctrl-starfive-jh7100.c1 // SPDX-License-Identifier: GPL-2.0
26 #include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
29 #include "../pinctrl-utils.h"
33 #define DRIVER_NAME "pinctrl-starfive"
37 * https://github.com/starfive-tech/JH7100_Docs
43 * are enabled. If set to 0 the GPIO interrupts are disabled.
48 * The following 32-bit registers come in pairs, but only the offset of the
49 * first register is defined. The first controls (interrupts for) GPIO 0-31 and
50 * the second GPIO 32-63.
54 * Interrupt Type. If set to 1 the interrupt is edge-triggered. If set to 0 the
[all …]
/linux/arch/x86/kernel/
H A Dmpparse.c1 // SPDX-License-Identifier: GPL-2.0
4 * compliant MP-table parsing routines.
45 while (len--) in mpf_checksum()
55 topology_register_apic(m->apicid, CPU_ACPIID_INVALID, m->cpuflag & CPU_ENABLED); in MP_processor_info()
56 if (!(m->cpuflag & CPU_ENABLED)) in MP_processor_info()
59 if (m->cpuflag & CPU_BOOTPROCESSOR) in MP_processor_info()
60 bootup_cpu = " (Bootup-CPU)"; in MP_processor_info()
62 pr_info("Processor #%d%s\n", m->apicid, bootup_cpu); in MP_processor_info()
69 memcpy(str, m->bustype, 6); in mpc_oem_bus_info()
71 apic_pr_verbose("Bus #%d is %s\n", m->busid, str); in mpc_oem_bus_info()
[all …]
/linux/arch/xtensa/variants/fsf/include/variant/
H A Dcore.h8 * Copyright (C) 1999-2006 Tensilica Inc.
21 * configured, and a value of 0 otherwise. These macros are always defined.
25 /*----------------------------------------------------------------------
27 ----------------------------------------------------------------------*/
29 #define XCHAL_HAVE_BE 1 /* big-endian byte ordering */
35 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
36 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
45 #define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
67 #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
74 /*----------------------------------------------------------------------
[all …]
/linux/sound/mips/
H A Dad1843.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2003 Vivien Chappelier <vivien.chappelier@linux-mips.org>
20 * AD1843 bitfield definitions. All are named as in the AD1843 data
25 * Only the bitfields we need are defined.
35 ad1843_PDNO = { 0, 14, 1 }, /* Converter Power-Down Flag */
177 w = ad1843->read(ad1843->chip, field->reg); in ad1843_read_bits()
178 return w >> field->lo_bit & ((1 << field->nbits) - 1); in ad1843_read_bits()
191 w = ad1843->read(ad1843->chip, field->reg); in ad1843_write_bits()
192 mask = ((1 << field->nbits) - 1) << field->lo_bit; in ad1843_write_bits()
193 oldval = (w & mask) >> field->lo_bit; in ad1843_write_bits()
[all …]
/linux/drivers/mfd/
H A Dstmpe.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) ST-Ericsson SA 2010
7 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
26 * struct stmpe_platform_data - STMPE platform data
43 return stmpe->variant->enable(stmpe, blocks, true); in __stmpe_enable()
48 return stmpe->variant->enable(stmpe, blocks, false); in __stmpe_disable()
55 ret = stmpe->ci->read_byte(stmpe, reg); in __stmpe_reg_read()
57 dev_err(stmpe->dev, "failed to read reg %#x: %d\n", reg, ret); in __stmpe_reg_read()
59 dev_vdbg(stmpe->dev, "rd: reg %#x => data %#x\n", reg, ret); in __stmpe_reg_read()
68 dev_vdbg(stmpe->dev, "wr: reg %#x <= %#x\n", reg, val); in __stmpe_reg_write()
[all …]
/linux/arch/arm/boot/dts/qcom/
H A Dqcom-msm8974.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interconnect/qcom,msm8974.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
10 #include <dt-bindings/gpio/gpio.h>
13 #address-cells = <1>;
[all …]
/linux/drivers/gpio/
H A Dgpio-max732x.c1 // SPDX-License-Identifier: GPL-2.0-only
26 * - Push Pull Output
27 * - Input
28 * - Open Drain I/O
31 * datasheets. 'I' and 'P' ports are interrupt capables, some with
34 * There are two groups of I/O ports, each group usually includes
37 * - Group A : by I2C address 0b'110xxxx
38 * - Group B : by I2C address 0b'101xxxx
43 * Within each group of ports, there are five known combinations of
49 * and GPIOs from GROUP_A are numbered before those from GROUP_B
[all …]
/linux/sound/soc/atmel/
H A Dmchp-i2s-mcc.c1 // SPDX-License-Identifier: GPL-2.0
3 // Driver for Microchip I2S Multi-channel controller
29 * ---- I2S Controller Register map ----
75 * ---- Control Register (Write-only) ----
86 * ---- Mode Register A (Read/Write) ----
135 /* Number of TDM Channels - 1 */
138 ((((ch) - 1) << 13) & MCHP_I2SMCC_MRA_NBCHAN_MASK)
169 * ---- Mode Register B (Read/Write) ----
171 /* all enabled I2S left channels are filled first, then I2S right channels */
175 * channel, until all channels are filled
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8976.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016-2022, AngeloGioacchino Del Regno
9 #include <dt-bindings/clock/qcom,gcc-msm8976.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
17 interrupt-parent = <&intc>;
18 #address-cells = <2>;
[all …]
/linux/arch/xtensa/variants/dc232b/include/variant/
H A Dcore.h8 * Copyright (c) 1999-2007 Tensilica Inc.
21 * configured, and a value of 0 otherwise. These macros are always defined.
25 /*----------------------------------------------------------------------
27 ----------------------------------------------------------------------*/
29 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
35 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
36 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
46 #define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
68 #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
75 /*----------------------------------------------------------------------
[all …]
/linux/arch/xtensa/variants/test_mmuhifi_c3/include/variant/
H A Dcore.h7 * Copyright (c) 1999-2009 Tensilica Inc.
20 * configured, and a value of 0 otherwise. These macros are always defined.
24 /*----------------------------------------------------------------------
26 ----------------------------------------------------------------------*/
28 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
34 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
35 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
45 #define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
70 #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
81 /*----------------------------------------------------------------------
[all …]

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