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/linux/drivers/gpio/
H A Dgpio-adp5585.c1 // SPDX-License-Identifier: GPL-2.0-only
24 * Bank 0 covers pins "GPIO 1/R0" to "GPIO 6/R5", numbered 0 to 5 by the
25 * driver, and bank 1 covers pins "GPIO 7/C0" to "GPIO 11/C4", numbered 6 to
31 #define ADP5585_BIT(n) ((n) >= 6 ? BIT((n) - 6) : BIT(n))
34 * Bank 0 covers pins "GPIO 1/R0" to "GPIO 8/R7", numbered 0 to 7 by the
35 * driver, bank 1 covers pins "GPIO 9/C0" to "GPIO 16/C7", numbered 8 to
36 * 15 and bank 3 covers pins "GPIO 17/C8" to "GPIO 19/C10", numbered 16 to 18.
92 const struct adp5585_gpio_chip *info = adp5585_gpio->info; in adp5585_gpio_get_direction()
95 regmap_read(adp5585_gpio->regmap, info->gpio_dir_a + info->bank(off), &val); in adp5585_gpio_get_direction()
97 return val & info->bit(off) ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; in adp5585_gpio_get_direction()
[all …]
H A Dgpio-max732x.c1 // SPDX-License-Identifier: GPL-2.0-only
26 * - Push Pull Output
27 * - Input
28 * - Open Drain I/O
31 * datasheets. 'I' and 'P' ports are interrupt capables, some with
34 * There are two groups of I/O ports, each group usually includes
37 * - Group A : by I2C address 0b'110xxxx
38 * - Group B : by I2C address 0b'101xxxx
43 * Within each group of ports, there are five known combinations of
49 * and GPIOs from GROUP_A are numbered before those from GROUP_B
[all …]
/linux/drivers/pinctrl/nomadik/
H A Dpinctrl-abx500.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 /* pins alternate function */
34 * struct abx500_function - ABx500 pinctrl mux function
46 * struct abx500_pingroup - describes a ABx500 pin group
48 * @pins: an array of discrete physical pins used in this group, taken
49 * from the driver-local pin enumeration space
50 * @num_pins: the number of pins in this group array, i.e. the number of
51 * elements in .pins so we can iterate over that array
52 * @altsetting: the altsetting to apply to all pins in this group to
57 const unsigned int *pins; member
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dsunplus,sp7021-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/sunplus,sp7021-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Dvorkin Dmitry <dvorkin@tibbo.com>
12 - Wells Lu <wellslutw@gmail.com>
15 The Sunplus SP7021 pin controller is used to control SoC pins. Please
16 refer to pinctrl-bindings.txt in this directory for details of the common
19 SP7021 has 99 digital GPIO pins which are numbered from GPIO 0 to 98. All
20 are multiplexed with some special function pins. SP7021 has 3 types of
[all …]
H A Dst,stm32-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre TORGUE <alexandre.torgue@foss.st.com>
15 controller. It controls the input/output settings on the available pins and
17 on-chip controllers onto these pads.
22 - st,stm32f429-pinctrl
23 - st,stm32f469-pinctrl
24 - st,stm32f746-pinctrl
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/linux/arch/arm/boot/dts/st/
H A Dste-snowball.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011 ST-Ericsson AB
6 /dts-v1/;
7 #include "ste-db9500.dtsi"
8 #include "ste-href-ab8500.dtsi"
9 #include "ste-href-family-pinctrl.dtsi"
13 compatible = "calaosystems,snowball-a9500", "st-ericsson,u9500";
21 compatible = "simple-battery";
22 battery-type = "lithium-ion-polymer";
25 thermal-zones {
[all …]
/linux/drivers/pinctrl/spear/
H A Dpinctrl-spear.h26 * struct spear_pmx_mode - SPEAr pmx mode
42 * struct spear_muxreg - SPEAr mux reg configuration
54 const unsigned *pins; member
85 .pins = __pins, \
92 * struct spear_modemux - SPEAr mode mux configuration
104 * struct spear_pingroup - SPEAr pin group configurations
106 * @pins: array containing pin numbers
107 * @npins: size of pins array
111 * A representation of a group of pins in the SPEAr pin controller. Each group
116 const unsigned *pins; member
[all …]
/linux/arch/alpha/kernel/
H A Dsys_cabriolet.c1 // SPDX-License-Identifier: GPL-2.0
40 int ofs = (irq - 16) / 8; in cabriolet_update_irq_hw()
47 cabriolet_update_irq_hw(d->irq, cached_irq_mask &= ~(1UL << d->irq)); in cabriolet_enable_irq()
53 cabriolet_update_irq_hw(d->irq, cached_irq_mask |= 1UL << d->irq); in cabriolet_disable_irq()
78 pld &= pld - 1; /* clear least bit set */ in cabriolet_device_interrupt()
111 if (request_irq(16 + 4, no_action, 0, "isa-cascade", NULL)) in common_init_irq()
112 pr_err("Failed to register isa-cascade interrupt\n"); in common_init_irq()
162 * the on-board NCR and Tulip chips. In the code below, I have used
166 * that's printed on the board. The interrupt pins from the PCI slots
167 * are wired into 3 interrupt summary registers at 0x804, 0x805 and
[all …]
/linux/drivers/net/ethernet/freescale/
H A Dfsl_pq_mdio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation
9 * Copyright 2002-2004, 2008-2009 Freescale Semiconductor, Inc.
72 * Per-device-type data. Each type of device tree node that we support gets
94 * control interfaces like onchip SERDES and are always tied to the local
95 * mdio pins, which may not be the same as system mdio bus, used for
101 struct fsl_pq_mdio_priv *priv = bus->priv; in fsl_pq_mdio_write()
102 struct fsl_pq_mii __iomem *regs = priv->regs; in fsl_pq_mdio_write()
106 iowrite32be((mii_id << 8) | regnum, &regs->miimadd); in fsl_pq_mdio_write()
109 iowrite32be(value, &regs->miimcon); in fsl_pq_mdio_write()
[all …]
/linux/drivers/net/can/
H A Dti_hecc.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
28 #include <linux/can/rx-offload.h>
36 #define HECC_MAX_MAILBOXES 32 /* hardware mailboxes - do not change */
37 #define MAX_TX_PRIO 0x3F /* hardware value - do not change */
42 * for the mailbox logic to work. Top mailbox numbers are reserved for RX
55 #define HECC_TX_MB_MASK (HECC_MAX_TX_MBOX - 1)
56 #define HECC_TX_MASK ((HECC_MAX_TX_MBOX - 1) | HECC_TX_PRIO_MASK)
60 * The remaining mailboxes are used for reception and are delivered
62 * changed while CAN-bus traffic is being received.
[all …]
/linux/drivers/usb/serial/
H A Dark3116.c1 // SPDX-License-Identifier: GPL-2.0+
9 * - implements a driver for the arkmicro ark3116 chipset (vendor=0x6547,
10 * productid=0x0232) (used in a datacable called KQ-U8A)
52 struct usb_device *dev = serial->dev; in is_irda()
53 if (le16_to_cpu(dev->descriptor.idVendor) == 0x18ec && in is_irda()
54 le16_to_cpu(dev->descriptor.idProduct) == 0x3118) in is_irda()
81 /* 0xfe 0x40 are magic values taken from original driver */ in ark3116_write_reg()
82 result = usb_control_msg(serial->dev, in ark3116_write_reg()
83 usb_sndctrlpipe(serial->dev, 0), in ark3116_write_reg()
96 /* 0xfe 0xc0 are magic values taken from original driver */ in ark3116_read_reg()
[all …]
/linux/drivers/pinctrl/starfive/
H A Dpinctrl-starfive-jh7100.c1 // SPDX-License-Identifier: GPL-2.0
26 #include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
29 #include "../pinctrl-utils.h"
33 #define DRIVER_NAME "pinctrl-starfive"
37 * https://github.com/starfive-tech/JH7100_Docs
43 * are enabled. If set to 0 the GPIO interrupts are disabled.
48 * The following 32-bit registers come in pairs, but only the offset of the
49 * first register is defined. The first controls (interrupts for) GPIO 0-31 and
50 * the second GPIO 32-63.
54 * Interrupt Type. If set to 1 the interrupt is edge-triggered. If set to 0 the
[all …]
/linux/drivers/pinctrl/
H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2012 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
62 * pinctrl_provide_dummies() - indicate if pinctrl provides dummy state support
77 return pctldev->desc->name; in pinctrl_dev_get_name()
83 return dev_name(pctldev->dev); in pinctrl_dev_get_devname()
89 return pctldev->driver_data; in pinctrl_dev_get_drvdata()
94 * get_pinctrl_dev_from_devname() - look up pin controller device
110 if (!strcmp(dev_name(pctldev->dev), devname)) { in get_pinctrl_dev_from_devname()
129 if (device_match_of_node(pctldev->dev, np)) { in get_pinctrl_dev_from_of_node()
[all …]
/linux/arch/x86/kernel/
H A Dmpparse.c1 // SPDX-License-Identifier: GPL-2.0
4 * compliant MP-table parsing routines.
45 while (len--) in mpf_checksum()
55 topology_register_apic(m->apicid, CPU_ACPIID_INVALID, m->cpuflag & CPU_ENABLED); in MP_processor_info()
56 if (!(m->cpuflag & CPU_ENABLED)) in MP_processor_info()
59 if (m->cpuflag & CPU_BOOTPROCESSOR) in MP_processor_info()
60 bootup_cpu = " (Bootup-CPU)"; in MP_processor_info()
62 pr_info("Processor #%d%s\n", m->apicid, bootup_cpu); in MP_processor_info()
69 memcpy(str, m->bustype, 6); in mpc_oem_bus_info()
71 apic_pr_verbose("Bus #%d is %s\n", m->busid, str); in mpc_oem_bus_info()
[all …]
/linux/arch/xtensa/variants/fsf/include/variant/
H A Dcore.h8 * Copyright (C) 1999-2006 Tensilica Inc.
21 * configured, and a value of 0 otherwise. These macros are always defined.
25 /*----------------------------------------------------------------------
27 ----------------------------------------------------------------------*/
29 #define XCHAL_HAVE_BE 1 /* big-endian byte ordering */
35 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
36 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
45 #define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
67 #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
74 /*----------------------------------------------------------------------
[all …]
/linux/arch/arm/boot/dts/qcom/
H A Dqcom-msm8974.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interconnect/qcom,msm8974.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
11 #include <dt-bindings/gpio/gpio.h>
[all …]
/linux/sound/mips/
H A Dad1843.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2003 Vivien Chappelier <vivien.chappelier@linux-mips.org>
20 * AD1843 bitfield definitions. All are named as in the AD1843 data
25 * Only the bitfields we need are defined.
35 ad1843_PDNO = { 0, 14, 1 }, /* Converter Power-Down Flag */
177 w = ad1843->read(ad1843->chip, field->reg); in ad1843_read_bits()
178 return w >> field->lo_bit & ((1 << field->nbits) - 1); in ad1843_read_bits()
191 w = ad1843->read(ad1843->chip, field->reg); in ad1843_write_bits()
192 mask = ((1 << field->nbits) - 1) << field->lo_bit; in ad1843_write_bits()
193 oldval = (w & mask) >> field->lo_bit; in ad1843_write_bits()
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8976.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016-2022, AngeloGioacchino Del Regno
9 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
10 #include <dt-bindings/clock/qcom,gcc-msm8976.h>
11 #include <dt-bindings/clock/qcom,rpmcc.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/power/qcom-rpmpd.h>
18 interrupt-parent = <&intc>;
[all …]
/linux/drivers/iio/adc/
H A Dad4170-4.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Analog Devices AD4170-4 ADC driver
6 * Author: Ana-Maria Cusco <ana-maria.cusco@analog.com>
17 #include <linux/clk-provider.h>
55 * Some register names and register field names are shortened versions of
81 /* AD4170_CONFIG_A_REG - INTERFACE_CONFIG_A REGISTER */
240 * CHANNEL_SETUP and CHANNEL_MAP register are all 2 byte size each and
241 * their addresses are interleaved such that we have CHANNEL_SETUP0
246 [AD4170_CHAN_SETUP_REG(0) ... AD4170_CHAN_MAP_REG(AD4170_MAX_ADC_CHANNELS - 1)] = 2,
248 * MISC, AFE, FILTER, FILTER_FS, OFFSET, and GAIN register addresses are
[all …]
/linux/sound/soc/atmel/
H A Dmchp-i2s-mcc.c1 // SPDX-License-Identifier: GPL-2.0
3 // Driver for Microchip I2S Multi-channel controller
29 * ---- I2S Controller Register map ----
75 * ---- Control Register (Write-only) ----
86 * ---- Mode Register A (Read/Write) ----
135 /* Number of TDM Channels - 1 */
138 ((((ch) - 1) << 13) & MCHP_I2SMCC_MRA_NBCHAN_MASK)
169 * ---- Mode Register B (Read/Write) ----
171 /* all enabled I2S left channels are filled first, then I2S right channels */
175 * channel, until all channels are filled
[all …]
/linux/arch/xtensa/variants/dc232b/include/variant/
H A Dcore.h8 * Copyright (c) 1999-2007 Tensilica Inc.
21 * configured, and a value of 0 otherwise. These macros are always defined.
25 /*----------------------------------------------------------------------
27 ----------------------------------------------------------------------*/
29 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
35 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
36 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
46 #define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
68 #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
75 /*----------------------------------------------------------------------
[all …]
/linux/arch/xtensa/variants/test_mmuhifi_c3/include/variant/
H A Dcore.h7 * Copyright (c) 1999-2009 Tensilica Inc.
20 * configured, and a value of 0 otherwise. These macros are always defined.
24 /*----------------------------------------------------------------------
26 ----------------------------------------------------------------------*/
28 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
34 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
35 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
45 #define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
70 #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
81 /*----------------------------------------------------------------------
[all …]
/linux/arch/xtensa/variants/dc233c/include/variant/
H A Dcore.h2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
10 Copyright (c) 1999-2010 Tensilica Inc.
41 * configured, and a value of 0 otherwise. These macros are always defined.
45 /*----------------------------------------------------------------------
47 ----------------------------------------------------------------------*/
49 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
55 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
56 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
66 #define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
91 #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
[all …]
/linux/arch/xtensa/variants/csp/include/variant/
H A Dcore.h2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
10 Copyright (c) 1999-2015 Tensilica Inc.
41 * configured, and a value of 0 otherwise. These macros are always defined.
45 /*----------------------------------------------------------------------
47 ----------------------------------------------------------------------*/
49 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
55 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
56 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
57 #define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
68 #define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
[all …]
/linux/arch/xtensa/variants/test_kc705_be/include/variant/
H A Dcore.h2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
10 Copyright (c) 1999-2015 Tensilica Inc.
41 * configured, and a value of 0 otherwise. These macros are always defined.
45 /*----------------------------------------------------------------------
47 ----------------------------------------------------------------------*/
49 #define XCHAL_HAVE_BE 1 /* big-endian byte ordering */
55 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
56 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
57 #define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
68 #define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
[all …]

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