1b9ffc18cSHsin-Yi Wang# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2b9ffc18cSHsin-Yi Wang%YAML 1.2 3b9ffc18cSHsin-Yi Wang--- 4b9ffc18cSHsin-Yi Wang$id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml# 5b9ffc18cSHsin-Yi Wang$schema: http://devicetree.org/meta-schemas/core.yaml# 6b9ffc18cSHsin-Yi Wang 7a9d44c4cSArınç ÜNALtitle: MediaTek MT65xx Pin Controller 8b9ffc18cSHsin-Yi Wang 9b9ffc18cSHsin-Yi Wangmaintainers: 10b9ffc18cSHsin-Yi Wang - Sean Wang <sean.wang@kernel.org> 11b9ffc18cSHsin-Yi Wang 12c911ad22SArınç ÜNALdescription: 13a9d44c4cSArınç ÜNAL The MediaTek's MT65xx Pin controller is used to control SoC pins. 14b9ffc18cSHsin-Yi Wang 15b9ffc18cSHsin-Yi Wangproperties: 16b9ffc18cSHsin-Yi Wang compatible: 17b9ffc18cSHsin-Yi Wang enum: 18b9ffc18cSHsin-Yi Wang - mediatek,mt2701-pinctrl 19b9ffc18cSHsin-Yi Wang - mediatek,mt2712-pinctrl 20b9ffc18cSHsin-Yi Wang - mediatek,mt6397-pinctrl 21b9ffc18cSHsin-Yi Wang - mediatek,mt7623-pinctrl 22b9ffc18cSHsin-Yi Wang - mediatek,mt8127-pinctrl 23b9ffc18cSHsin-Yi Wang - mediatek,mt8135-pinctrl 24b9ffc18cSHsin-Yi Wang - mediatek,mt8167-pinctrl 25b9ffc18cSHsin-Yi Wang - mediatek,mt8173-pinctrl 26b9ffc18cSHsin-Yi Wang - mediatek,mt8516-pinctrl 27b9ffc18cSHsin-Yi Wang 28b9ffc18cSHsin-Yi Wang reg: 29b9ffc18cSHsin-Yi Wang maxItems: 1 30b9ffc18cSHsin-Yi Wang 31b9ffc18cSHsin-Yi Wang pins-are-numbered: 32b9ffc18cSHsin-Yi Wang $ref: /schemas/types.yaml#/definitions/flag 33c911ad22SArınç ÜNAL description: 348f7b96bdSBernhard Rosenkränzer Specify the subnodes are using numbered pinmux to specify pins. (UNUSED) 358f7b96bdSBernhard Rosenkränzer deprecated: true 36b9ffc18cSHsin-Yi Wang 37b9ffc18cSHsin-Yi Wang gpio-controller: true 38b9ffc18cSHsin-Yi Wang 39b9ffc18cSHsin-Yi Wang "#gpio-cells": 40b9ffc18cSHsin-Yi Wang const: 2 41c911ad22SArınç ÜNAL description: 42c911ad22SArınç ÜNAL Number of cells in GPIO specifier. Since the generic GPIO binding is used, 43c911ad22SArınç ÜNAL the amount of cells must be specified as 2. See the below mentioned gpio 44c911ad22SArınç ÜNAL binding representation for description of particular cells. 45b9ffc18cSHsin-Yi Wang 46b9ffc18cSHsin-Yi Wang mediatek,pctl-regmap: 47b9ffc18cSHsin-Yi Wang $ref: /schemas/types.yaml#/definitions/phandle-array 4839bd2b6aSRob Herring items: 4939bd2b6aSRob Herring maxItems: 1 50b9ffc18cSHsin-Yi Wang minItems: 1 51b9ffc18cSHsin-Yi Wang maxItems: 2 52c911ad22SArınç ÜNAL description: 53b9ffc18cSHsin-Yi Wang Should be phandles of the syscfg node. 54b9ffc18cSHsin-Yi Wang 55b9ffc18cSHsin-Yi Wang interrupt-controller: true 56b9ffc18cSHsin-Yi Wang 57b9ffc18cSHsin-Yi Wang interrupts: 58b9ffc18cSHsin-Yi Wang minItems: 1 59b9ffc18cSHsin-Yi Wang maxItems: 3 60b9ffc18cSHsin-Yi Wang 61b9ffc18cSHsin-Yi Wang "#interrupt-cells": 62b9ffc18cSHsin-Yi Wang const: 2 63b9ffc18cSHsin-Yi Wang 64b9ffc18cSHsin-Yi Wangrequired: 65b9ffc18cSHsin-Yi Wang - compatible 66b9ffc18cSHsin-Yi Wang - gpio-controller 67b9ffc18cSHsin-Yi Wang - "#gpio-cells" 68b9ffc18cSHsin-Yi Wang 69c09acbc4SRafał MiłeckiallOf: 70*6a735ad5SArınç ÜNAL - $ref: pinctrl.yaml# 71c09acbc4SRafał Miłecki 72b9ffc18cSHsin-Yi WangpatternProperties: 736c488fbbSRob Herring 'pins$': 74b9ffc18cSHsin-Yi Wang type: object 75b9ffc18cSHsin-Yi Wang additionalProperties: false 76b9ffc18cSHsin-Yi Wang patternProperties: 776c488fbbSRob Herring '(^pins|pins?$)': 78b9ffc18cSHsin-Yi Wang type: object 79b9ffc18cSHsin-Yi Wang additionalProperties: false 80c911ad22SArınç ÜNAL description: 81b9ffc18cSHsin-Yi Wang A pinctrl node should contain at least one subnodes representing the 82b9ffc18cSHsin-Yi Wang pinctrl groups available on the machine. Each subnode will list the 83b9ffc18cSHsin-Yi Wang pins it needs, and how they should be configured, with regard to muxer 84b9ffc18cSHsin-Yi Wang configuration, pullups, drive strength, input enable/disable and input 85b9ffc18cSHsin-Yi Wang schmitt. 86*6a735ad5SArınç ÜNAL $ref: /schemas/pinctrl/pincfg-node.yaml 87b9ffc18cSHsin-Yi Wang 88b9ffc18cSHsin-Yi Wang properties: 89b9ffc18cSHsin-Yi Wang pinmux: 90b9ffc18cSHsin-Yi Wang description: 91c911ad22SArınç ÜNAL Integer array, represents gpio pin number and mux setting. 92b9ffc18cSHsin-Yi Wang Supported pin number and mux varies for different SoCs, and are 9303af785eSArınç ÜNAL defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly. 94b9ffc18cSHsin-Yi Wang 95b9ffc18cSHsin-Yi Wang bias-disable: true 96b9ffc18cSHsin-Yi Wang 97b9ffc18cSHsin-Yi Wang bias-pull-up: 98c911ad22SArınç ÜNAL description: 99b9ffc18cSHsin-Yi Wang Besides generic pinconfig options, it can be used as the pull up 100b9ffc18cSHsin-Yi Wang settings for 2 pull resistors, R0 and R1. User can configure those 101b9ffc18cSHsin-Yi Wang special pins. Some macros have been defined for this usage, such 102b9ffc18cSHsin-Yi Wang as MTK_PUPD_SET_R1R0_00. See dt-bindings/pinctrl/mt65xx.h for 103b9ffc18cSHsin-Yi Wang valid arguments. 104b9ffc18cSHsin-Yi Wang 105b9ffc18cSHsin-Yi Wang bias-pull-down: true 106b9ffc18cSHsin-Yi Wang 107b9ffc18cSHsin-Yi Wang input-enable: true 108b9ffc18cSHsin-Yi Wang 109b9ffc18cSHsin-Yi Wang input-disable: true 110b9ffc18cSHsin-Yi Wang 111b9ffc18cSHsin-Yi Wang output-low: true 112b9ffc18cSHsin-Yi Wang 113b9ffc18cSHsin-Yi Wang output-high: true 114b9ffc18cSHsin-Yi Wang 115b9ffc18cSHsin-Yi Wang input-schmitt-enable: true 116b9ffc18cSHsin-Yi Wang 117b9ffc18cSHsin-Yi Wang input-schmitt-disable: true 118b9ffc18cSHsin-Yi Wang 119b9ffc18cSHsin-Yi Wang drive-strength: 120c911ad22SArınç ÜNAL description: 121b9ffc18cSHsin-Yi Wang Can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA, 122b9ffc18cSHsin-Yi Wang etc. See dt-bindings/pinctrl/mt65xx.h for valid arguments. 123b9ffc18cSHsin-Yi Wang 124b9ffc18cSHsin-Yi Wang required: 125b9ffc18cSHsin-Yi Wang - pinmux 126b9ffc18cSHsin-Yi Wang 127b9ffc18cSHsin-Yi WangadditionalProperties: false 128b9ffc18cSHsin-Yi Wang 129b9ffc18cSHsin-Yi Wangexamples: 130b9ffc18cSHsin-Yi Wang - | 131b9ffc18cSHsin-Yi Wang #include <dt-bindings/interrupt-controller/irq.h> 132b9ffc18cSHsin-Yi Wang #include <dt-bindings/interrupt-controller/arm-gic.h> 133b9ffc18cSHsin-Yi Wang #include <dt-bindings/pinctrl/mt8135-pinfunc.h> 134b9ffc18cSHsin-Yi Wang 135b9ffc18cSHsin-Yi Wang soc { 136b9ffc18cSHsin-Yi Wang #address-cells = <2>; 137b9ffc18cSHsin-Yi Wang #size-cells = <2>; 138b9ffc18cSHsin-Yi Wang 139b9ffc18cSHsin-Yi Wang syscfg_pctl_a: syscfg-pctl-a@10005000 { 140b9ffc18cSHsin-Yi Wang compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon"; 141b9ffc18cSHsin-Yi Wang reg = <0 0x10005000 0 0x1000>; 142b9ffc18cSHsin-Yi Wang }; 143b9ffc18cSHsin-Yi Wang 144b9ffc18cSHsin-Yi Wang syscfg_pctl_b: syscfg-pctl-b@1020c020 { 145b9ffc18cSHsin-Yi Wang compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon"; 146b9ffc18cSHsin-Yi Wang reg = <0 0x1020C020 0 0x1000>; 147b9ffc18cSHsin-Yi Wang }; 148b9ffc18cSHsin-Yi Wang 149b9ffc18cSHsin-Yi Wang pinctrl@1c20800 { 150b9ffc18cSHsin-Yi Wang compatible = "mediatek,mt8135-pinctrl"; 151b9ffc18cSHsin-Yi Wang reg = <0 0x1000B000 0 0x1000>; 152b9ffc18cSHsin-Yi Wang mediatek,pctl-regmap = <&syscfg_pctl_a>, <&syscfg_pctl_b>; 153b9ffc18cSHsin-Yi Wang gpio-controller; 154b9ffc18cSHsin-Yi Wang #gpio-cells = <2>; 155b9ffc18cSHsin-Yi Wang interrupt-controller; 156b9ffc18cSHsin-Yi Wang #interrupt-cells = <2>; 157b9ffc18cSHsin-Yi Wang interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 158b9ffc18cSHsin-Yi Wang <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 159b9ffc18cSHsin-Yi Wang <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 160b9ffc18cSHsin-Yi Wang 1616c488fbbSRob Herring i2c0_pins_a: i2c0-pins { 162b9ffc18cSHsin-Yi Wang pins1 { 163b9ffc18cSHsin-Yi Wang pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>, 164b9ffc18cSHsin-Yi Wang <MT8135_PIN_101_SCL0__FUNC_SCL0>; 165b9ffc18cSHsin-Yi Wang bias-disable; 166b9ffc18cSHsin-Yi Wang }; 167b9ffc18cSHsin-Yi Wang }; 168b9ffc18cSHsin-Yi Wang 1696c488fbbSRob Herring i2c1_pins_a: i2c1-pins { 170b9ffc18cSHsin-Yi Wang pins { 171b9ffc18cSHsin-Yi Wang pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>, 172b9ffc18cSHsin-Yi Wang <MT8135_PIN_196_SCL1__FUNC_SCL1>; 173b9ffc18cSHsin-Yi Wang bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 174b9ffc18cSHsin-Yi Wang }; 175b9ffc18cSHsin-Yi Wang }; 176b9ffc18cSHsin-Yi Wang 1776c488fbbSRob Herring i2c2_pins_a: i2c2-pins { 178b9ffc18cSHsin-Yi Wang pins1 { 179b9ffc18cSHsin-Yi Wang pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>; 180b9ffc18cSHsin-Yi Wang bias-pull-down; 181b9ffc18cSHsin-Yi Wang }; 182b9ffc18cSHsin-Yi Wang 183b9ffc18cSHsin-Yi Wang pins2 { 184b9ffc18cSHsin-Yi Wang pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>; 185b9ffc18cSHsin-Yi Wang bias-pull-up; 186b9ffc18cSHsin-Yi Wang }; 187b9ffc18cSHsin-Yi Wang }; 188b9ffc18cSHsin-Yi Wang 1896c488fbbSRob Herring i2c3_pins_a: i2c3-pins { 190b9ffc18cSHsin-Yi Wang pins1 { 191b9ffc18cSHsin-Yi Wang pinmux = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>, 192b9ffc18cSHsin-Yi Wang <MT8135_PIN_41_DAC_WS__FUNC_GPIO41>; 193b9ffc18cSHsin-Yi Wang bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 194b9ffc18cSHsin-Yi Wang }; 195b9ffc18cSHsin-Yi Wang 196b9ffc18cSHsin-Yi Wang pins2 { 197b9ffc18cSHsin-Yi Wang pinmux = <MT8135_PIN_35_SCL3__FUNC_SCL3>, 198b9ffc18cSHsin-Yi Wang <MT8135_PIN_36_SDA3__FUNC_SDA3>; 199b9ffc18cSHsin-Yi Wang output-low; 200b9ffc18cSHsin-Yi Wang bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 201b9ffc18cSHsin-Yi Wang }; 202b9ffc18cSHsin-Yi Wang 203b9ffc18cSHsin-Yi Wang pins3 { 204b9ffc18cSHsin-Yi Wang pinmux = <MT8135_PIN_57_JTCK__FUNC_GPIO57>, 205b9ffc18cSHsin-Yi Wang <MT8135_PIN_60_JTDI__FUNC_JTDI>; 206b9ffc18cSHsin-Yi Wang drive-strength = <32>; 207b9ffc18cSHsin-Yi Wang }; 208b9ffc18cSHsin-Yi Wang }; 209b9ffc18cSHsin-Yi Wang }; 210b9ffc18cSHsin-Yi Wang }; 211