pinmux\-node (full) in projects: freebsd

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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A D	renesas,rzn1-pinctrl.txt	1 Renesas RZ/N1 SoC Pinctrl node description. 3 Pin controller node 4 ------------------- 6 - compatible: SoC-specific compatible string "renesas,<soc-specific>-pinctrl" 7 followed by "renesas,rzn1-pinctrl" as fallback. The SoC-specific compatible 9 "renesas,r9a06g032-pinctrl" for RZ/N1D 10 "renesas,r9a06g033-pinctrl" for RZ/N1S 11 - reg: Address base and length of the memory area where the pin controller 13 - clocks: phandle for the clock, see the description of clock-names below. 14 - clock-names: Contains the name of the clock: [all …]
H A D	renesas,rza1-pinctrl.txt	`5 Pin multiplexing and GPIO configuration is performed on a per-pin basis 6 writing configuration values to per-port register sets. 11 Pin controller node 12 ------------------- 15 - compatible: should be: 16 - "renesas,r7s72100-ports": for RZ/A1H 17 - "renesas,r7s72101-ports", "renesas,r7s72100-ports": for RZ/A1M 18 - "renesas,r7s72102-ports": for RZ/A1L 20 - reg 25 Pin controller node for RZ/A1H SoC (r7s72100) [all …]`
H A D	pinctrl-mt65xx.txt	6 - compatible: value should be one of the following. 7 "mediatek,mt2701-pinctrl", compatible with mt2701 pinctrl. 8 "mediatek,mt2712-pinctrl", compatible with mt2712 pinctrl. 9 "mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl. 10 "mediatek,mt7623-pinctrl", compatible with mt7623 pinctrl. 11 "mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl. 12 "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl. 13 "mediatek,mt8167-pinctrl", compatible with mt8167 pinctrl. 14 "mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl. 15 "mediatek,mt8365-pinctrl", compatible with mt8365 pinctrl. [all …]
H A D	ralink,rt2880-pinmux.yaml	`1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/pinctrl/ralink,rt2880-pinmux.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Ralink rt2880 pinmux controller 10 - Sergio Paracuellos <sergio.paracuellos@gmail.com> 13 The rt2880 pinmux can only set the muxing of pin groups. Muxing indiviual pins 18 const: ralink,rt2880-pinmux 21 '-pins$': 24 '^(.*-)?pinmux$': [all …]`
H A D	pinmux-node.yaml	`1 # SPDX-License-Identifier: GPL-2.0-only 3 --- 4 $id: http://devicetree.org/schemas/pinctrl/pinmux-node.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Generic Pin Multiplexing Node 10 - Linus Walleij <linus.walleij@linaro.org> 50 For cases like this, the pin controller driver may use pinctrl-pin-array helper 55 #pinctrl-cells = <2>; 58 pinctrl-pin-array = < 67 Above #pinctrl-cells specifies the number of value cells in addition to the [all …]`
H A D	renesas,rzn1-pinctrl.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzn1-pinctr [all...]`
H A D	intel,lgm-io.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pinctrl/intel,lgm-io.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Intel Lightning Mountain SoC pinmux & GPIO controller 10 - Rahul Tanwar <rahul.tanwar@linux.intel.com> 13 Pinmux & GPIO controller controls pin multiplexing & configuration including 18 const: intel,lgm-io 25 '-pins$': 28 Pinctrl node's client devices use subnodes for desired pin configuration. [all …]
H A D	sophgo,cv1800-pinctrl.yaml	`1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/pinctrl/sophgo,cv1800-pinctrl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Inochi Amaoto <inochiama@outlook.com> 15 - sophgo,cv1800b-pinctrl 16 - sophgo,cv1812h-pinctrl 17 - sophgo,sg2000-pinctrl 18 - sophgo,sg2002-pinctrl 22 - description: pinctrl for system domain [all …]`
H A D	atmel,at91-pio4-pinctrl.txt	7 - compatible: 8 "atmel,sama5d2-pinctrl" 9 "microchip,sama7g5-pinctrl" 10 - reg: base address and length of the PIO controller. 11 - interrupts: interrupt outputs from the controller, one for each bank. 12 - interrupt-controller: mark the device node as an interrupt controller. 13 - #interrupt-cells: should be two. 14 - gpio-controller: mark the device node as a gpio controller. 15 - #gpio-cells: should be two. 17 Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for [all …]
H A D	fsl,mxs-pinctrl.txt	6 voltage and pull-up. 9 - compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl" 10 - reg: Should contain the register physical address and length for the 13 Please refer to pinctrl-bindings.txt in this directory for details of the 16 The node of mxs pin controller acts as a container for an arbitrary number of 20 information about pull-up. For this reason, even seemingly boolean values are 25 Those subnodes under mxs pin controller node will fall into two categories. 27 configurations, and it's called group node in the binding document. The other 29 different configuration than what is defined in group node. The binding 30 document calls this type of node config node. [all …]
H A D	renesas,rza1-ports.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pinctrl/renesas,rza1-port [all...]`
H A D	loongson,ls2k-pinctrl.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pinctrl/loongson,ls2k-pinctrl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Loongson-2 SoC Pinctrl Controller 10 - zhanghongchen <zhanghongchen@loongson.cn> 11 - Yinbo Zhu <zhuyinbo@loongson.cn> 14 - $ref: pinctrl.yaml# 18 const: loongson,ls2k-pinctrl 24 '-pins$': [all …]`
H A D	nxp,s32g2-siul2-pinctrl.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/pinctrl/nxp,s32g2-siul [all...]`
H A D	mediatek,mt65xx-pinctrl.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Sean Wang <sean.wang@kernel.org> 18 - mediatek,mt2701-pinctrl 19 - mediatek,mt2712-pinctrl 20 - mediatek,mt6397-pinctrl 21 - mediatek,mt7623-pinctrl 22 - mediatek,mt8127-pinctrl [all …]`
H A D	brcm,ns-pinmux.yaml	`1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/pinctrl/brcm,ns-pinmux.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Rafał Miłecki <rafal@milecki.pl> 23 - brcm,bcm4708-pinmux 24 - brcm,bcm4709-pinmux 25 - brcm,bcm53012-pinmux 30 reg-names: 34 '-pins$': [all …]`
H A D	canaan,k210-fpioa.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pinctrl/canaan,k210-fpio [all...]`
H A D	starfive,jh7110-sys-pinctrl.yaml	`1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-sys-pinctrl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd. 21 - Jianlong Huang <jianlong.huang@starfivetech.com> 25 const: starfive,jh7110-sys-pinctrl 39 interrupt-controller: true 41 '#interrupt-cells': 44 gpio-controller: true [all …]`
H A D	renesas,rza2-pinctrl.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pinctrl/renesas,rza2-pinctr [all...]`
H A D	starfive,jh7100-pinctrl.yaml	1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7100-pinctrl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 Bindings for the JH7100 RISC-V SoC from StarFive Ltd. 15 interesting 2-layered approach to pin muxing best illustrated by the diagram 21 LCD output -----------------\| \| 22 CMOS Camera interface ------\| \|--- PAD_GPIO[0] 23 Ethernet PHY interface -----\| MUX \|--- PAD_GPIO[1] 25 \| \|--- PAD_GPIO[63] [all …]
H A D	renesas,rza2-pinctrl.txt	`4 Pin multiplexing and GPIO configuration is performed on a per-pin basis. 9 Pin controller node 10 ------------------- 13 - compatible: shall be: 14 - "renesas,r7s9210-pinctrl": for RZ/A2M 15 - reg 18 - gpio-controller 20 - #gpio-cells 22 - gpio-ranges 25 Example: Pin controller node for RZ/A2M SoC (r7s9210) [all …]`
H A D	pinctrl-rk805.txt	`5 Please refer file <devicetree/bindings/pinctrl/pinctrl-bindings.txt> 7 including the meaning of the phrase "pin configuration node". 9 Optional Pinmux properties: 10 ------- [all...]`
H A D	xlnx,zynq-pinctrl.txt	4 - compatible: "xlnx,zynq-pinctrl" 5 - syscon: phandle to SLCR 6 - reg: Offset and length of pinctrl space in SLCR 8 Please refer to pinctrl-bindings.txt in this directory for details of the 10 phrase "pin configuration node". 16 parameters, such as pull-up, slew rate, etc. 18 Each configuration node can consist of multiple nodes describing the pinmux and 19 pinconf options. Those nodes can be pinmux nodes or pinconf nodes. 24 Required properties for pinmux nodes are: 25 - groups: A list of pinmux groups. [all …]
H A D	pinctrl-single.txt	1 One-register-per-pin type device tree based pinctrl driver 4 - compatible : "pinctrl-single" or "pinconf-single". 5 "pinctrl-single" means that pinconf isn't supported. 6 "pinconf-single" means that generic pinconf is supported. 8 - reg : offset and length of the register set for the mux registers 10 - #pinctrl-cells : number of cells in addition to the index, set to 1 11 or 2 for pinctrl-single,pins and set to 2 for pinctrl-single,bits 13 - pinctrl-single,register-width : pinmux register access width in bits 15 - pinctrl-single,function-mask : mask of allowed pinmux function bits 16 in the pinmux register [all …]
/freebsd/share/man/man4/
H A D	fdt_pinctrl.4	34 Pin multiplexing is a technology used to re-purpose a single 41 Function selection is performed by the pinmux controller, a SoC 43 Pinmux controller capabilities and register format depend 48 based systems, the pinmux controller is represented by a node in 52 Properties of such nodes are hardware-specific and handled 55 Pinmux controller device tree node 56 .Bd -literal 58 compatible = "vndr,soc1715-pinctrl"; 76 Each configuration is described by setting the pinctrl-N 78 nodes of the pinmux controller node. [all …]
/freebsd/share/man/man9/
H A D	fdt_pinctrl.9	1 .\" -- nroff -- 34 .Nd helper functions for FDT pinmux controller drivers 48 pinmux controllers and pinmux clients. 53 function to register itself as a pinmux controller. 56 is used to walk the device tree and configure pins specified by the pinctrl-0 73 described by the pinctrl-N property with index 87 It also registers each child node of the pinctrl driver's node which contains 94 every descendant node is registered. 96 as a pinmux controller for more than one pin property type 103 If the pinctrl-0 property contains references [all …]

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