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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Drenesas,rzn1-pinctrl.txt1 Renesas RZ/N1 SoC Pinctrl node description.
3 Pin controller node
4 -------------------
6 - compatible: SoC-specific compatible string "renesas,<soc-specific>-pinctrl"
7 followed by "renesas,rzn1-pinctrl" as fallback. The SoC-specific compatible
9 "renesas,r9a06g032-pinctrl" for RZ/N1D
10 "renesas,r9a06g033-pinctrl" for RZ/N1S
11 - reg: Address base and length of the memory area where the pin controller
13 - clocks: phandle for the clock, see the description of clock-names below.
14 - clock-names: Contains the name of the clock:
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H A Drenesas,rza1-pinctrl.txt5 Pin multiplexing and GPIO configuration is performed on a per-pin basis
6 writing configuration values to per-port register sets.
11 Pin controller node
12 -------------------
15 - compatible: should be:
16 - "renesas,r7s72100-ports": for RZ/A1H
17 - "renesas,r7s72101-ports", "renesas,r7s72100-ports": for RZ/A1M
18 - "renesas,r7s72102-ports": for RZ/A1L
20 - reg
25 Pin controller node for RZ/A1H SoC (r7s72100)
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H A Dpinctrl-mt65xx.txt6 - compatible: value should be one of the following.
7 "mediatek,mt2701-pinctrl", compatible with mt2701 pinctrl.
8 "mediatek,mt2712-pinctrl", compatible with mt2712 pinctrl.
9 "mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl.
10 "mediatek,mt7623-pinctrl", compatible with mt7623 pinctrl.
11 "mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
12 "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
13 "mediatek,mt8167-pinctrl", compatible with mt8167 pinctrl.
14 "mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl.
15 "mediatek,mt8365-pinctrl", compatible with mt8365 pinctrl.
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H A Dralink,rt2880-pinmux.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/ralink,rt2880-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ralink rt2880 pinmux controller
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
13 The rt2880 pinmux can only set the muxing of pin groups. Muxing indiviual pins
18 const: ralink,rt2880-pinmux
21 '-pins$':
24 '^(.*-)?pinmux$':
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H A Dpinmux-node.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinmux-node.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic Pin Multiplexing Node
10 - Linus Walleij <linus.walleij@linaro.org>
50 For cases like this, the pin controller driver may use pinctrl-pin-array helper
55 #pinctrl-cells = <2>;
58 pinctrl-pin-array = <
67 Above #pinctrl-cells specifies the number of value cells in addition to the
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H A Dsophgo,cv1800-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/sophgo,cv1800-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inochi Amaoto <inochiama@outlook.com>
15 - sophgo,cv1800b-pinctrl
16 - sophgo,cv1812h-pinctrl
17 - sophgo,sg2000-pinctrl
18 - sophgo,sg2002-pinctrl
22 - description: pinctrl for system domain
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H A Dsophgo,sg2042-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/sophgo,sg2042-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inochi Amaoto <inochiama@outlook.com>
15 - sophgo,sg2042-pinctrl
16 - sophgo,sg2044-pinctrl
22 '-cfg$':
25 A pinctrl node should contain at least one subnode representing the
31 '-pins$':
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H A Drenesas,rzn1-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzn1-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 - const: renesas,r9a06g032-pinctrl # RZ/N1D
17 - const: renesas,rzn1-pinctrl # Generic RZ/N1
21 - description: GPIO Multiplexing Level1 Register Block
22 - description: GPIO Multiplexing Level2 Register Block
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H A Dintel,lgm-io.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/intel,lgm-io.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel Lightning Mountain SoC pinmux & GPIO controller
10 - Rahul Tanwar <rahul.tanwar@linux.intel.com>
13 Pinmux & GPIO controller controls pin multiplexing & configuration including
18 const: intel,lgm-io
25 '-pins$':
28 Pinctrl node's client devices use subnodes for desired pin configuration.
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H A Dfsl,mxs-pinctrl.txt6 voltage and pull-up.
9 - compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl"
10 - reg: Should contain the register physical address and length for the
13 Please refer to pinctrl-bindings.txt in this directory for details of the
16 The node of mxs pin controller acts as a container for an arbitrary number of
20 information about pull-up. For this reason, even seemingly boolean values are
25 Those subnodes under mxs pin controller node will fall into two categories.
27 configurations, and it's called group node in the binding document. The other
29 different configuration than what is defined in group node. The binding
30 document calls this type of node config node.
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H A Datmel,at91-pio4-pinctrl.txt7 - compatible:
8 "atmel,sama5d2-pinctrl"
9 "microchip,sama7d65-pinctrl", "microchip,sama7g5-pinctrl"
10 "microchip,sama7g5-pinctrl"
11 - reg: base address and length of the PIO controller.
12 - interrupts: interrupt outputs from the controller, one for each bank.
13 - interrupt-controller: mark the device node as an interrupt controller.
14 - #interrupt-cells: should be two.
15 - gpio-controller: mark the device node as a gpio controller.
16 - #gpio-cells: should be two.
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H A Drenesas,rza1-ports.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rza1-port
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H A Dloongson,ls2k-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/loongson,ls2k-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson-2 SoC Pinctrl Controller
10 - zhanghongchen <zhanghongchen@loongson.cn>
11 - Yinbo Zhu <zhuyinbo@loongson.cn>
14 - $ref: pinctrl.yaml#
18 const: loongson,ls2k-pinctrl
24 '-pins$':
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H A Dnxp,s32g2-siul2-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/nxp,s32g2-siul
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H A Dbrcm,ns-pinmux.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/brcm,ns-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rafał Miłecki <rafal@milecki.pl>
23 - brcm,bcm4708-pinmux
24 - brcm,bcm4709-pinmux
25 - brcm,bcm53012-pinmux
30 reg-names:
34 '-pins$':
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H A Dstarfive,jh7110-sys-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-sys-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
21 - Hal Feng <hal.feng@starfivetech.com>
25 const: starfive,jh7110-sys-pinctrl
39 interrupt-controller: true
41 '#interrupt-cells':
44 gpio-controller: true
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H A Dcanaan,k210-fpioa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/canaan,k210-fpio
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H A Drenesas,rza2-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rza2-pinctr
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H A Dmediatek,mt65xx-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@kernel.org>
18 - mediatek,mt2701-pinctrl
19 - mediatek,mt2712-pinctrl
20 - mediatek,mt6397-pinctrl
21 - mediatek,mt7623-pinctrl
22 - mediatek,mt8127-pinctrl
[all …]
H A Dstarfive,jh7100-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7100-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 Bindings for the JH7100 RISC-V SoC from StarFive Ltd.
15 interesting 2-layered approach to pin muxing best illustrated by the diagram
21 LCD output -----------------| |
22 CMOS Camera interface ------| |--- PAD_GPIO[0]
23 Ethernet PHY interface -----| MUX |--- PAD_GPIO[1]
25 | |--- PAD_GPIO[63]
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H A Drenesas,rza2-pinctrl.txt4 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
9 Pin controller node
10 -------------------
13 - compatible: shall be:
14 - "renesas,r7s9210-pinctrl": for RZ/A2M
15 - reg
18 - gpio-controller
20 - #gpio-cells
22 - gpio-ranges
25 Example: Pin controller node for RZ/A2M SoC (r7s9210)
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H A Dcanaan,k230-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/canaan,k230-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ze Huang <18771902331@163.com>
15 performed on a per-pin basis.
19 const: canaan,k230-pinctrl
25 '-pins$':
29 A pinctrl node should contain at least one subnode representing the
33 '-cfg$':
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H A Dpinctrl-rk805.txt5 Please refer file <devicetree/bindings/pinctrl/pinctrl-bindings.txt>
7 including the meaning of the phrase "pin configuration node".
9 Optional Pinmux properties:
10 -------
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/freebsd/sys/arm64/apple/
H A Dapple_pinctrl.c40 #define APPLE_PIN(pinmux) ((pinmux) & 0xffff) argument
41 #define APPLE_FUNC(pinmux) ((pinmux) >> 16) argument
64 bus_read_4((sc)->sc_res[APPLE_PINCTRL_MEMRES], reg)
66 bus_write_4((sc)->sc_res[APPLE_PINCTRL_MEMRES], reg, val)
95 #define APPLE_PINCTRL_LOCK(sc) mtx_lock_spin(&(sc)->sc_mtx)
96 #define APPLE_PINCTRL_UNLOCK(sc) mtx_unlock_spin(&(sc)->sc_mtx)
97 #define APPLE_PINCTRL_LOCK_ASSERT(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED)
107 { -1, 0, 0 },
124 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) in apple_pinctrl_probe()
127 device_set_desc(dev, "Apple Pinmux Controller"); in apple_pinctrl_probe()
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/freebsd/sys/contrib/device-tree/src/arm64/renesas/
H A Dr9a09g047e57-smarc.dts1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 /dts-v1/;
27 #include <dt-bindings/gpio/gpio.h>
28 #include <dt-bindings/input/input.h>
29 #include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h>
31 #include "rzg3e-smarc-som.dtsi"
32 #include "renesas-smarc2.dtsi"
36 compatible = "renesas,smarc2-evk", "renesas,rzg3e-smarcm",
39 vqmmc_sd1_pvdd: regulator-vqmmc-sd1-pvdd {
40 compatible = "regulator-gpio";
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