| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | pinctrl-bindings.txt | 3 Hardware modules that control pin multiplexing or configuration parameters
4 such as pull-up/down, tri-state, drive-strength etc are designated as pin
5 controllers. Each pin controller must be represented as a node in device tree,
8 Hardware modules whose signals are affected by pin configuration are
12 For a client device to operate correctly, certain pin controllers must
13 set up certain specific pin configurations. Some client devices need a
14 single static pin configuration, e.g. set up during initialization. Others
15 need to reconfigure pins at run-time, for example to tri-state pins when the
21 for client device device tree nodes to map those state names to the pin
24 Note that pin controllers themselves may also be client devices of themselves.
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| H A D | samsung,pinctrl-wakeup-interrupt.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C/S5P/Exynos SoC pin controller - wake-up interrupt controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
12 - Tomasz Figa <tomasz.figa@gmail.com>
15 This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin
18 External wake-up interrupts for Samsung S3C/S5P/Exynos SoC pin controller.
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| H A D | img,pistachio-pinctrl.txt | 1 Imagination Technologies Pistachio SoC pin controllers
4 The pin controllers on Pistachio are a combined GPIO controller, (GPIO)
5 interrupt controller, and pinmux + pinconf device. The system ("east") pin
8 each. The GPIO banks are represented as sub-nodes of the pad controller node.
10 Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
11 ../interrupt-controller/interrupts.txt for generic information regarding
12 pin controller, GPIO, and interrupt bindings.
14 Required properties for pin controller node:
15 --------------------------------------------
16 - compatible: "img,pistachio-system-pinctrl".
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| H A D | brcm,nsp-gpio.txt | 4 - compatible:
5 Must be "brcm,nsp-gpio-a"
7 - reg:
11 - #gpio-cells:
12 Must be two. The first cell is the GPIO pin number (within the
13 controller's pin space) and the second cell is used for the following:
16 - gpio-controller:
19 - ngpios:
23 - interrupts:
26 - interrupt-controller:
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| H A D | cix,sky1-pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/cix,sky1-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cix Sky1 Soc Pin Controller
10 - Gary Yang <gary.yang@cixtech.com>
13 The pin-controller is used to control Soc pins. There are two pin-controllers
20 - cix,sky1-pinctrl
21 - cix,sky1-pinctrl-s5
25 - description: gpio base
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| /linux/include/linux/pinctrl/ |
| H A D | pinmux.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
20 * struct pinmux_ops - pinmux operations, to be implemented by pin controller
22 * @request: called by the core to see if a certain pin can be made
26 * @free: the reverse function of the request() callback, frees a pin after
41 * @gpio_set_direction. When the pin control core can properly determine
43 * on the pin controller. Since a single function is passed, this is
44 * only useful on pin controllers that use a specific function for GPIO,
45 * and that usually presupposes that a one-group-per-pin approach is
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| H A D | pinconf.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
20 * struct pinconf_ops - pin config operations, to be implemented by
21 * pin configuration capable drivers.
22 * @is_generic: for pin controllers that want to use the generic interface,
24 * @pin_config_get: get the config of a certain pin, if the requested config
25 * is not available on this controller this should return -ENOTSUPP
26 * and if it is available but disabled it should return -EINVAL
27 * @pin_config_set: configure an individual pin
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| H A D | machine.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
16 #include <linux/pinctrl/pinctrl-state.h>
27 * struct pinctrl_map_mux - mapping table content for MAP_TYPE_MUX_GROUP
39 * struct pinctrl_map_configs - mapping table content for MAP_TYPE_CONFIGS_*
40 * @group_or_pin: the name of the pin or group whose configuration parameters
43 * hardware. Each individual pin controller defines the format and meaning
54 * struct pinctrl_map - boards/machines shall provide this map for devices
57 * same name as the pin controllers own dev_name(), the map entry will be
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| /linux/Documentation/devicetree/bindings/watchdog/ |
| H A D | aspeed,ast2400-wdt.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/aspeed,ast2400-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Aspeed watchdog timer controllers
10 - Andrew Jeffery <andrew@codeconstruct.com.au>
15 - aspeed,ast2400-wdt
16 - aspeed,ast2500-wdt
17 - aspeed,ast2600-wdt
18 - aspeed,ast2700-wdt
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| /linux/Documentation/devicetree/bindings/usb/ |
| H A D | pxa-usb.txt | 1 PXA USB controllers
6 - compatible: Should be "marvell,pxa-ohci" for USB controllers
10 - "marvell,enable-port1", "marvell,enable-port2", "marvell,enable-port3"
12 - "marvell,port-mode" selects the mode of the ports:
16 - "marvell,power-sense-low" - power sense pin is low-active.
17 - "marvell,power-control-low" - power control pin is low-active.
18 - "marvell,no-oc-protection" - disable over-current protection.
19 - "marvell,oc-mode-perport" - enable per-port over-current protection.
20 - "marvell,power_on_delay" Power On to Power Good time - in ms.
25 compatible = "marvell,pxa-ohci";
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| H A D | usb.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
22 phy-names:
26 usb-phy:
27 $ref: /schemas/types.yaml#/definitions/phandle-array
37 Tells USB controllers that we want to configure the core to support a
38 UTMI+ PHY with an 8- or 16-bit interface if UTMI+ is selected, UTMI+ low
39 pin interface if ULPI is specified, Serial core/PHY interconnect if
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| /linux/drivers/pinctrl/intel/ |
| H A D | pinctrl-intel.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Core pinctrl/GPIO driver for Intel GPIO controllers
26 * struct intel_pingroup - Description about group of pins
27 * @grp: Generic data of the pin group (name and pins)
29 * @modes: If not %NULL this will hold mode for each pin in @pins
38 * struct intel_function - Description about a function
39 * @func: Generic data of the pin function (name and groups of pins)
48 * struct intel_padgroup - Hardware pad group information
50 * @base: Starting pin of this group
67 * enum - Special treatment for GPIO base in pad group
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| /linux/Documentation/scsi/ |
| H A D | aic79xx.rst | 1 .. SPDX-License-Identifier: GPL-2.0
28 AIC-7901A Single Channel 64-bit PCI-X 133MHz to
30 AIC-7901B Single Channel 64-bit PCI-X 133MHz to
32 AIC-7902A4 Dual Channel 64-bit PCI-X 133MHz to
34 AIC-7902B Dual Channel 64-bit PCI-X 133MHz to
41 Adaptec SCSI Card 39320 Dual Channel 64-bit PCI-X 133MHz to 7902A4/7902B
43 68-pin, two internal 68-pin)
44 Adaptec SCSI Card 39320A Dual Channel 64-bit PCI-X 133MHz to 7902B
46 68-pin, two internal 68-pin)
47 Adaptec SCSI Card 39320D Dual Channel 64-bit PCI-X 133MHz to 7902A4
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| /linux/drivers/pinctrl/samsung/ |
| H A D | pinctrl-exynos-arm.c | 1 // SPDX-License-Identifier: GPL-2.0+
20 #include <linux/soc/samsung/exynos-regs-pmu.h>
22 #include "pinctrl-samsung.h"
23 #include "pinctrl-exynos.h"
49 unsigned int *pud_val = drvdata->pud_val; in s5pv210_pud_value_init()
58 void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv; in s5pv210_retention_disable()
75 ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL); in s5pv210_retention_init()
77 return ERR_PTR(-ENOMEM); in s5pv210_retention_init()
79 np = of_find_compatible_node(NULL, NULL, "samsung,s5pv210-clock"); in s5pv210_retention_init()
83 return ERR_PTR(-ENODEV); in s5pv210_retention_init()
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| /linux/drivers/pinctrl/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
7 bool "Pin controllers"
15 bool "Support pin multiplexing controllers" if COMPILE_TEST
22 bool "Support pin configuration controllers" if COMPILE_TEST
35 bool "AMD GPIO pin control"
53 tristate "AMDISP GPIO pin control"
67 tristate "Apple SoC GPIO pin controller driver"
80 will be called pinctrl-apple-gpio.
83 bool "Axis ARTPEC-6 pin controller driver"
88 This is the driver for the Axis ARTPEC-6 pin controller. This driver
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| /linux/Documentation/driver-api/gpio/ |
| H A D | intro.rst | 17 A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
20 represents a bit connected to a particular pin, or "ball" on Ball Grid Array
23 passes such pin configuration data to drivers.
25 System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
26 non-dedicated pin can be configured as a GPIO; and most chips have at least
29 often have a few such pins to help with pin scarcity on SOCs; and there are
31 Most PC southbridges have a few dozen GPIO-capable pins (with only the BIOS
36 - Output values are writable (high=1, low=0). Some chips also have
38 value might be driven, supporting "wire-OR" and similar schemes for the
41 - Input values are likewise readable (1, 0). Some chips support readback
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| /linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | st,stm32mp25-omm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32mp25-omm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Patrice Chotard <patrice.chotard@foss.st.com>
13 The STM32 Octo Memory Manager is a low-level interface that enables an
14 efficient OCTOSPI pin assignment with a full I/O matrix (before alternate
17 - Two single/dual/quad/octal SPI interfaces
18 - Two ports for pin assignment
22 const: st,stm32mp25-omm
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| /linux/drivers/usb/common/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
13 Say Y here if you are working on a system with led-class supported
21 UTMI+ Low Pin Interface (ULPI) is specification for a commonly used
28 controllers which support ULPI register access and have ULPI PHY
46 to detect USB ID pin, and another input GPIO may be also used to detect
47 Vbus pin at the same time, it also can be used to enable/disable
48 device if an input GPIO is only used to detect Vbus pin.
51 be called usb-conn-gpio.ko
|
| /linux/Documentation/core-api/ |
| H A D | debugging-via-ohci1394.rst | 2 Using physical DMA provided by OHCI-1394 FireWire controllers for debugging
6 ------------
8 Basically all FireWire controllers which are in use today are compliant
9 to the OHCI-1394 specification which defines the controller to be a PCI
12 PCI-Bus master DMA after applying filters defined by the OHCI-1394 driver.
15 ask the OHCI-1394 controller to perform read and write requests on
25 With most FireWire controllers, memory access is limited to the low 4 GB
28 hardware such as x86, x86-64 and PowerPC.
30 At least LSI FW643e and FW643e2 controllers are known to support access to
34 Together with a early initialization of the OHCI-1394 controller for debugging,
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| /linux/Documentation/devicetree/bindings/mfd/ |
| H A D | omap-usb-host.txt | 5 - compatible: should be "ti,usbhs-host"
6 - reg: should contain one register range i.e. start and length
7 - ti,hwmods: must contain "usb_host_hs"
11 - num-ports: number of USB ports. Usually this is automatically detected
15 - portN-mode: String specifying the port mode for port N, where N can be
18 "ehci-phy",
19 "ehci-tll",
20 "ehci-hsic",
21 "ohci-phy-6pin-datse0",
22 "ohci-phy-6pin-dpdm",
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| /linux/Documentation/userspace-api/gpio/ |
| H A D | sysfs.rst | 6 been moved to Documentation/ABI/obsolete/sysfs-gpio.
16 ----------------------
27 then changing its output state, then updating the code before re-enabling
38 Please read Documentation/driver-api/gpio/drivers-on-gpio.rst
44 --------------
47 - Control interfaces used to get userspace control over GPIOs;
49 - GPIOs themselves; and
51 - GPIO controllers ("gpio_chip" instances).
55 The control interfaces are write-only:
94 If the pin can be configured as interrupt-generating interrupt
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| /linux/Documentation/networking/pse-pd/ |
| H A D | pse-pi.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 eight-pin modular jack, commonly known as the Ethernet RJ45 port. This
14 ---------------------------
19 - Section "33.2.3 PI pin assignments" covers the pin assignments for PoE
21 - Section "145.2.4 PSE PI" addresses the configuration for PoE systems that
25 -------------------------------
31 two pairs of wires, SPE operates on a simpler model due to its single-pair
32 design. As a result, the complexities of choosing between alternative pin
33 assignments for power delivery, as described in the PSE PI for multi-pair
37 --------------------
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| /linux/drivers/net/ethernet/sfc/falcon/ |
| H A D | phy.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Driver for Solarflare network controllers and boards
4 * Copyright 2007-2010 Solarflare Communications Inc.
29 #define QUAKE_LED_LINK_INPUT (6) /* Pin is an input. */
44 void falcon_txc_set_gpio_dir(struct ef4_nic *efx, int pin, int dir);
45 void falcon_txc_set_gpio_val(struct ef4_nic *efx, int pin, int val);
|
| /linux/Documentation/devicetree/bindings/gpio/ |
| H A D | ti,keystone-dsp-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/ti,keystone-dsp-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Grygorii Strashko <grygorii.strashko@ti.com>
17 For example TCI6638K2K SoC has 8 DSP GPIO controllers:
18 - 8 for C66x CorePacx CPUs 0-7
21 - each GPIO can be configured only as output pin;
22 - setting GPIO value to 1 causes IRQ generation on target DSP core;
23 - reading pin value returns 0 - if IRQ was handled or 1 - IRQ is still
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| /linux/arch/sh/include/asm/ |
| H A D | pci.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 already-configured bus numbers - to be used for buggy BIOSes
12 * A board can define one or more PCI channels that represent built-in (or
13 * external) PCI controllers.
74 * None of the SH PCI controllers support MWI, it is always treated as a
80 /* Board-specific fixup routines. */
81 int pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin);
83 #define pci_domain_nr(bus) ((struct pci_channel *)(bus)->sysdata)->index
87 struct pci_channel *hose = bus->sysdata; in pci_proc_domain()
88 return hose->need_domain_info; in pci_proc_domain()
|