| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | xilinx_axienet.txt | 2 --------------------------------------------------------
5 provides connectivity to an external ethernet PHY supporting different
15 For more details about mdio please refer phy.txt file in the same directory.
18 - compatible : Must be one of "xlnx,axi-ethernet-1.00.a",
19 "xlnx,axi-ethernet-1.01.a", "xlnx,axi-ethernet-2.01.a"
20 - reg : Address and length of the IO space, as well as the address
22 axistream-connected is specified, in which case the reg
24 - interrupts : Should be a list of 2 or 3 interrupts: TX DMA, RX DMA,
25 and optionally Ethernet core. If axistream-connected is
29 - phy-handle : Should point to the external phy device if exists. Pointing
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| H A D | xlnx,axi-ethernet.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-etherne
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| /freebsd/sys/contrib/device-tree/Bindings/phy/ |
| H A D | samsung,ufs-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC series UFS PHY
10 - Alim Akhtar <alim.akhtar@samsung.com>
13 "#phy-cells":
18 - samsung,exynos7-ufs-phy
19 - samsung,exynosautov9-ufs-phy
20 - tesla,fsd-ufs-phy
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| H A D | ti,phy-j721e-wiz.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
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| H A D | cdns,dphy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/cdns,dphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Pratyush Yadav <pratyush@kernel.org>
15 - cdns,dphy
16 - ti,j721e-dphy
23 - description: PMA state machine clock
24 - description: PLL reference clock
26 clock-names:
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| /freebsd/sys/contrib/alpine-hal/ |
| H A D | al_hal_serdes_internal_regs.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
48 * 0 - Hard reset is asserted
49 * 1 - Hard reset is de-asserted
58 * 0 - Hard reset is taken from the interface pins
59 * 1 - Hard reset is taken from registers
121 * PMA serial RX-to-TX loop-back enable (from AGC to IO Driver). Serial receive
122 * to transmit loopback: 0 - Disables loopback 1 - Transmits the untimed,
129 * PMA TX-to-RX buffered serial loop-back enable (bypasses IO Driver). Serial
130 * transmit to receive buffered loopback: 0 - Disables loopback 1 - Loops back
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| H A D | al_hal_serdes_hssp_internal_regs.h | 9 found at http://www.gnu.org/licenses/gpl-2.0.html
47 * 0 - Hard reset is asserted
48 * 1 - Hard reset is de-asserted
57 * 0 - Hard reset is taken from the interface pins
58 * 1 - Hard reset is taken from registers
120 * PMA serial RX-to-TX loop-back enable (from AGC to IO Driver). Serial receive
121 * to transmit loopback: 0 - Disables loopback 1 - Transmits the untimed,
128 * PMA TX-to-RX buffered serial loop-back enable (bypasses IO Driver). Serial
129 * transmit to receive buffered loopback: 0 - Disables loopback 1 - Loops back
136 * PMA TX-to-RX I/O serial loop-back enable (loop back done directly from TX to
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| /freebsd/sys/contrib/device-tree/Bindings/display/bridge/ |
| H A D | cdns,mhdp8546.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Swapnil Jakhade <sjakhade@cadence.com>
11 - Yuti Amonkar <yamonkar@cadence.com>
16 - cdns,mhdp8546
17 - ti,j721e-mhdp8546
22 - description:
23 Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P).
24 The AUX and PMA registers are not part of this range, they are instead
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| /freebsd/sys/arm64/rockchip/ |
| H A D | rk3568_pciephy.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
47 #include <dev/phy/phy.h>
49 #include <contrib/device-tree/include/dt-bindings/phy/phy.h>
69 {"rockchip,rk3568-pcie3-phy", 1},
93 SYSCON_WRITE_4(sc->phy_grf, control, GRF_PCIE30PHY_WR_EN); in rk3568_pciephy_bifurcate()
96 SYSCON_WRITE_4(sc->phy_grf, control, in rk3568_pciephy_bifurcate()
100 SYSCON_WRITE_4(sc->phy_grf, control, in rk3568_pciephy_bifurcate()
112 /* PHY class and methods */
121 /* Pull PHY out of reset */ in rk3568_pciephy_enable()
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| H A D | rk_typec_phy.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
29 * Rockchip PHY TYPEC
47 #include <dev/phy/phy_usb.h>
112 { "rockchip,rk3399-typec-phy", 1 },
118 { -1, 0 }
134 #define RK_TYPEC_PHY_READ(sc, reg) bus_read_4(sc->res, (reg))
135 #define RK_TYPEC_PHY_WRITE(sc, reg, val) bus_write_4(sc->res, (reg), (val))
137 /* Phy class and methods. */
139 static int rk_typec_phy_get_mode(struct phynode *phy, int *mode);
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| /freebsd/sys/dev/xilinx/ |
| H A D | if_xaereg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
8 * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
48 #define XAE_PPST 0x00030 /* PCS PMA Status register RO */
73 #define MDIO_TX_PHYAD_S 24 /* This controls the PHY address being accessed. */
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| /freebsd/sys/contrib/device-tree/src/arm64/exynos/ |
| H A D | exynos7.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/exynos7-clk.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
15 #address-cell
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| H A D | exynosautov9.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/samsung,exynosautov9.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/soc/samsung,boot-mode.h>
12 #include <dt-binding
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| /freebsd/sys/contrib/alpine-hal/eth/ |
| H A D | al_hal_eth_mac_regs.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
454 /* [0x10] PMA register file address */
456 /* [0x14] PMA register file data */
611 * [0x7c] SERDES 32-bit interface shift configuration (when swap is
616 * [0x80] SERDES 32-bit interface shift configuration (when swap is
621 * [0x84] SERDES 32-bit interface bit selection
625 * [0x88] SERDES 32-bit interface bit selection
766 * 0 - 10/100/1000
767 * 1 - 1/2.5/10G
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| /freebsd/sys/dev/qlnx/qlnxe/ |
| H A D | reg_addr.h | 2 * Copyright (c) 2017-2018 Cavium, Inc.
78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…
81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
116 … (0x1<<9) // Fast back-to-back transaction ena…
128 … (0x1<<23) // Fast back-to-back capable. Not ap…
145 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
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| /freebsd/sys/dev/cxgb/common/ |
| H A D | cxgb_ael1002.c | 2 SPDX-License-Identifier: BSD-2-Clause
4 Copyright (c) 2007-2009, Chelsio Inc.
38 PMD_RSD = 10, /* PMA/PMD receive signal detect register */
39 PCS_STAT1_X = 24, /* 10GBASE-X PCS status 1 register */
40 PCS_STAT1_R = 32, /* 10GBASE-R PCS status 1 register */
75 /* PHY module I2C device address */
81 /* PHY transceiver type */
97 static int ael2xxx_get_module_type(struct cphy *phy, int delay_ms);
99 static int set_phy_regs(struct cphy *phy, const struct reg_val *rv) in set_phy_regs() argument
103 for (err = 0; rv->mmd_addr && !err; rv++) { in set_phy_regs()
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| /freebsd/sys/contrib/device-tree/src/arm64/tesla/ |
| H A D | fsd.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Tesla Full Self-Driving SoC device tree source
5 * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2017-2022 Tesla, Inc.
11 #include <dt-bindings/clock/fsd-clk.h>
12 #include <dt-bindings/interrupt-controlle
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| /freebsd/sys/dev/bxe/ |
| H A D | bxe_elink.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved.
508 /* When this pin is active high during reset, 10GBASE-T core is power
509 * down, When it is active low the 10GBASE-T is power up
757 typedef elink_status_t (*read_sfp_module_eeprom_func_p)(struct elink_phy *phy,
774 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
936 (_phy)->def_md_devad, \
942 (_phy)->def_md_devad, \
948 static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
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| /freebsd/sys/dev/sfxge/common/ |
| H A D | efx_regs_mcdi.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright 2008-2013 Solarflare Communications Inc. All rights reserved.
32 /* Power-on reset state */
54 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
57 /* The rest of these are firmware-defined */
65 /* Values to be written to the per-port status dword in shared
94 * | | \--- Response
95 * | \------- Error
96 * \------------------------------ Resync (always set)
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| /freebsd/sys/dev/ixgbe/ |
| H A D | ixgbe_type.h | 2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
42 * - IXGBE_ERROR_INVALID_STATE
48 * - IXGBE_ERROR_POLLING
53 * - IXGBE_ERROR_CAUTION
58 * - IXGBE_ERROR_SOFTWARE
64 * - IXGBE_ERROR_ARGUMENT
69 * - IXGBE_ERROR_UNSUPPORTED
162 #define IXGBE_BY_MAC(_hw, r) ((_hw)->mvals[IXGBE_CAT(r, _IDX)])
419 (0x012300 + (((_i) - 24) * 4)))
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| /freebsd/sys/cam/scsi/ |
| H A D | scsi_all.c | 1 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
78 #define ERESTART -1 /* restart syscall */
79 #define EJUSTRETURN -2 /* don't modify regs, just return */
91 * a minimum value of 100ms. Note that this is pertinent only for SPI-
142 { 0xD8, R, "CD-DA READ" }
149 * to read CD-DA data. I'm not sure which Plextor CDROM
152 * 12-20X does. I don't know about any earlier models,
156 {T_CDROM, SIP_MEDIA_REMOVABLE, "PLEXTOR", "CD-ROM PX*", "*"},
164 * From: http://www.t10.org/lists/op-num.txt
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