Lines Matching +full:phy +full:- +full:pma
1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/exynos7-clk.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
30 arm-pmu {
31 compatible = "arm,cortex-a57-pmu";
36 interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>,
42 compatible = "fixed-clock";
43 clock-output-names = "fin_pll";
44 #clock-cells = <0>;
48 #address-cells = <1>;
49 #size-cells = <0>;
53 compatible = "arm,cortex-a57";
55 enable-method = "psci";
56 i-cache-size = <0xc000>;
57 i-cache-line-size = <64>;
58 i-cache-sets = <256>;
59 d-cache-size = <0x8000>;
60 d-cache-line-size = <64>;
61 d-cache-sets = <256>;
62 next-level-cache = <&atlas_l2>;
67 compatible = "arm,cortex-a57";
69 enable-method = "psci";
70 i-cache-size = <0xc000>;
71 i-cache-line-size = <64>;
72 i-cache-sets = <256>;
73 d-cache-size = <0x8000>;
74 d-cache-line-size = <64>;
75 d-cache-sets = <256>;
76 next-level-cache = <&atlas_l2>;
81 compatible = "arm,cortex-a57";
83 enable-method = "psci";
84 i-cache-size = <0xc000>;
85 i-cache-line-size = <64>;
86 i-cache-sets = <256>;
87 d-cache-size = <0x8000>;
88 d-cache-line-size = <64>;
89 d-cache-sets = <256>;
90 next-level-cache = <&atlas_l2>;
95 compatible = "arm,cortex-a57";
97 enable-method = "psci";
98 i-cache-size = <0xc000>;
99 i-cache-line-size = <64>;
100 i-cache-sets = <256>;
101 d-cache-size = <0x8000>;
102 d-cache-line-size = <64>;
103 d-cache-sets = <256>;
104 next-level-cache = <&atlas_l2>;
107 atlas_l2: l2-cache0 {
109 cache-level = <2>;
110 cache-unified;
111 cache-size = <0x200000>;
112 cache-line-size = <64>;
113 cache-sets = <2048>;
125 compatible = "simple-bus";
126 #address-cells = <1>;
127 #size-cells = <1>;
131 compatible = "samsung,exynos7-chipid",
132 "samsung,exynos4210-chipid";
136 gic: interrupt-controller@11001000 {
137 compatible = "arm,gic-400";
138 #interrupt-cells = <3>;
139 #address-cells = <0>;
140 interrupt-controller;
147 pdma0: dma-controller@10e10000 {
152 clock-names = "apb_pclk";
153 #dma-cells = <1>;
156 pdma1: dma-controller@10eb0000 {
161 clock-names = "apb_pclk";
162 #dma-cells = <1>;
165 clock_topc: clock-controller@10570000 {
166 compatible = "samsung,exynos7-clock-topc";
168 #clock-cells = <1>;
171 clock_top0: clock-controller@105d0000 {
172 compatible = "samsung,exynos7-clock-top0";
174 #clock-cells = <1>;
180 clock-names = "fin_pll", "dout_sclk_bus0_pll",
185 clock_top1: clock-controller@105e0000 {
186 compatible = "samsung,exynos7-clock-top1";
188 #clock-cells = <1>;
193 clock-names = "fin_pll", "dout_sclk_bus0_pll",
198 clock_ccore: clock-controller@105b0000 {
199 compatible = "samsung,exynos7-clock-ccore";
201 #clock-cells = <1>;
203 clock-names = "fin_pll", "dout_aclk_ccore_133";
206 clock_peric0: clock-controller@13610000 {
207 compatible = "samsung,exynos7-clock-peric0";
209 #clock-cells = <1>;
212 clock-names = "fin_pll", "dout_aclk_peric0_66",
216 clock_peric1: clock-controller@14c80000 {
217 compatible = "samsung,exynos7-clock-peric1";
219 #clock-cells = <1>;
233 clock-names = "fin_pll",
248 clock_peris: clock-controller@10040000 {
249 compatible = "samsung,exynos7-clock-peris";
251 #clock-cells = <1>;
253 clock-names = "fin_pll", "dout_aclk_peris_66";
256 clock_fsys0: clock-controller@10e90000 {
257 compatible = "samsung,exynos7-clock-fsys0";
259 #clock-cells = <1>;
262 clock-names = "fin_pll", "dout_aclk_fsys0_200",
266 clock_fsys1: clock-controller@156e0000 {
267 compatible = "samsung,exynos7-clock-fsys1";
269 #clock-cells = <1>;
276 clock-names = "fin_pll", "dout_aclk_fsys1_200",
283 compatible = "samsung,exynos7-uart", "samsung,exynos4210-uart";
288 clock-names = "uart", "clk_uart_baud0";
293 compatible = "samsung,exynos7-uart", "samsung,exynos4210-uart";
298 clock-names = "uart", "clk_uart_baud0";
303 compatible = "samsung,exynos7-uart", "samsung,exynos4210-uart";
308 clock-names = "uart", "clk_uart_baud0";
313 compatible = "samsung,exynos7-uart", "samsung,exynos4210-uart";
318 clock-names = "uart", "clk_uart_baud0";
323 compatible = "samsung,exynos7-pinctrl";
326 wakeup-interrupt-controller {
327 compatible = "samsung,exynos7-wakeup-eint";
328 interrupt-parent = <&gic>;
334 compatible = "samsung,exynos7-pinctrl";
340 compatible = "samsung,exynos7-pinctrl";
346 compatible = "samsung,exynos7-pinctrl";
352 compatible = "samsung,exynos7-pinctrl";
358 compatible = "samsung,exynos7-pinctrl";
364 compatible = "samsung,exynos7-pinctrl";
370 compatible = "samsung,exynos7-pinctrl";
376 compatible = "samsung,exynos7-pinctrl";
382 compatible = "samsung,exynos7-hsi2c";
385 #address-cells = <1>;
386 #size-cells = <0>;
387 pinctrl-names = "default";
388 pinctrl-0 = <&hs_i2c0_bus>;
390 clock-names = "hsi2c";
395 compatible = "samsung,exynos7-hsi2c";
398 #address-cells = <1>;
399 #size-cells = <0>;
400 pinctrl-names = "default";
401 pinctrl-0 = <&hs_i2c1_bus>;
403 clock-names = "hsi2c";
408 compatible = "samsung,exynos7-hsi2c";
411 #address-cells = <1>;
412 #size-cells = <0>;
413 pinctrl-names = "default";
414 pinctrl-0 = <&hs_i2c2_bus>;
416 clock-names = "hsi2c";
421 compatible = "samsung,exynos7-hsi2c";
424 #address-cells = <1>;
425 #size-cells = <0>;
426 pinctrl-names = "default";
427 pinctrl-0 = <&hs_i2c3_bus>;
429 clock-names = "hsi2c";
434 compatible = "samsung,exynos7-hsi2c";
437 #address-cells = <1>;
438 #size-cells = <0>;
439 pinctrl-names = "default";
440 pinctrl-0 = <&hs_i2c4_bus>;
442 clock-names = "hsi2c";
447 compatible = "samsung,exynos7-hsi2c";
450 #address-cells = <1>;
451 #size-cells = <0>;
452 pinctrl-names = "default";
453 pinctrl-0 = <&hs_i2c5_bus>;
455 clock-names = "hsi2c";
460 compatible = "samsung,exynos7-hsi2c";
463 #address-cells = <1>;
464 #size-cells = <0>;
465 pinctrl-names = "default";
466 pinctrl-0 = <&hs_i2c6_bus>;
468 clock-names = "hsi2c";
473 compatible = "samsung,exynos7-hsi2c";
476 #address-cells = <1>;
477 #size-cells = <0>;
478 pinctrl-names = "default";
479 pinctrl-0 = <&hs_i2c7_bus>;
481 clock-names = "hsi2c";
486 compatible = "samsung,exynos7-hsi2c";
489 #address-cells = <1>;
490 #size-cells = <0>;
491 pinctrl-names = "default";
492 pinctrl-0 = <&hs_i2c8_bus>;
494 clock-names = "hsi2c";
499 compatible = "samsung,exynos7-hsi2c";
502 #address-cells = <1>;
503 #size-cells = <0>;
504 pinctrl-names = "default";
505 pinctrl-0 = <&hs_i2c9_bus>;
507 clock-names = "hsi2c";
512 compatible = "samsung,exynos7-hsi2c";
515 #address-cells = <1>;
516 #size-cells = <0>;
517 pinctrl-names = "default";
518 pinctrl-0 = <&hs_i2c10_bus>;
520 clock-names = "hsi2c";
525 compatible = "samsung,exynos7-hsi2c";
528 #address-cells = <1>;
529 #size-cells = <0>;
530 pinctrl-names = "default";
531 pinctrl-0 = <&hs_i2c11_bus>;
533 clock-names = "hsi2c";
537 pmu_system_controller: system-controller@105c0000 {
538 compatible = "samsung,exynos7-pmu", "syscon";
543 compatible = "samsung,exynos7-rtc", "samsung,s3c6410-rtc";
548 clock-names = "rtc";
553 compatible = "samsung,exynos7-wdt";
557 clock-names = "watchdog";
558 samsung,syscon-phandle = <&pmu_system_controller>;
563 compatible = "samsung,exynos7-mali",
564 "samsung,exynos5433-mali", "arm,mali-t760";
569 interrupt-names = "job", "mmu", "gpu";
575 compatible = "samsung,exynos7-dw-mshc-smu";
577 #address-cells = <1>;
578 #size-cells = <0>;
582 clock-names = "biu", "ciu";
583 fifo-depth = <0x40>;
588 compatible = "samsung,exynos7-dw-mshc";
590 #address-cells = <1>;
591 #size-cells = <0>;
595 clock-names = "biu", "ciu";
596 fifo-depth = <0x40>;
601 compatible = "samsung,exynos7-dw-mshc-smu";
603 #address-cells = <1>;
604 #size-cells = <0>;
608 clock-names = "biu", "ciu";
609 fifo-depth = <0x40>;
614 compatible = "samsung,exynos7-adc";
618 clock-names = "adc";
619 #io-channel-cells = <1>;
624 compatible = "samsung,exynos7-pwm", "samsung,exynos4210-pwm";
631 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
632 #pwm-cells = <3>;
634 clock-names = "timers";
638 compatible = "samsung,exynos7-tmu";
643 clock-names = "tmu_apbif", "tmu_sclk";
644 #thermal-sensor-cells = <0>;
648 compatible = "samsung,exynos7-ufs";
653 reg-names = "hci", "vs_hci", "unipro", "ufsp";
657 clock-names = "core_clk", "sclk_unipro_main";
658 freq-table-hz = <0 0>, <0 0>;
659 pinctrl-names = "default";
660 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
662 phy-names = "ufs-phy";
666 ufs_phy: ufs-phy@15571800 {
667 compatible = "samsung,exynos7-ufs-phy";
669 reg-names = "phy-pma";
670 samsung,pmu-syscon = <&pmu_system_controller>;
671 #phy-cells = <0>;
676 clock-names = "ref_clk", "rx1_symbol_clk",
681 usbdrd_phy: phy@15500000 {
682 compatible = "samsung,exynos7-usbdrd-phy";
689 clock-names = "phy", "ref", "phy_utmi", "phy_pipe", "itp";
690 samsung,pmu-syscon = <&pmu_system_controller>;
691 #phy-cells = <1>;
695 compatible = "samsung,exynos7-dwusb3";
699 clock-names = "usbdrd30", "usbdrd30_susp_clk",
701 #address-cells = <1>;
702 #size-cells = <1>;
710 phy-names = "usb2-phy", "usb3-phy";
715 thermal-zones {
716 atlas_thermal: cluster0-thermal {
717 polling-delay-passive = <0>; /* milliseconds */
718 polling-delay = <0>; /* milliseconds */
719 thermal-sensors = <&tmuctrl_0>;
720 #include "exynos7-trip-points.dtsi"
725 compatible = "arm,armv8-timer";
737 #include "exynos7-pinctrl.dtsi"
738 #include "arm/samsung/exynos-syscon-restart.dtsi"