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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dphy-cadence-torrent.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence Torrent SD0801 PHY
10 This binding describes the Cadence SD0801 PHY (also known as Torrent PHY)
11 hardware included with the Cadence MHDP DisplayPort controller. Torrent
12 PHY also supports multilink multiprotocol combinations including protocols
16 - Swapnil Jakhade <sjakhade@cadence.com>
17 - Yuti Amonkar <yamonkar@cadence.com>
[all …]
H A Dphy-cadence-sierra.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence Sierra PHY
10 This binding describes the Cadence Sierra PHY. Sierra PHY supports multilink
14 - Swapnil Jakhade <sjakhade@cadence.com>
15 - Yuti Amonkar <yamonkar@cadence.com>
20 - cdns,sierra-phy-t0
21 - ti,sierra-phy-t0
[all …]
H A Dphy-cadence-sierra.txt1 Cadence Sierra PHY
2 -----------------------
5 - compatible: Must be "cdns,sierra-phy-t0" for Sierra in Cadence platform
6 Must be "ti,sierra-phy-t0" for Sierra in TI's J721E SoC.
7 - resets: Must contain an entry for each in reset-names.
9 - reset-names: Must include "sierra_reset" and "sierra_apb".
10 "sierra_reset" must control the reset line to the PHY.
11 "sierra_apb" must control the reset line to the APB PHY
13 - reg: register range for the PHY.
14 - #address-cells: Must be 1
[all …]
H A Dcdns,dphy.txt1 Cadence DPHY
4 Cadence DPHY block.
7 - compatible: should be set to "cdns,dphy".
8 - reg: physical base address and length of the DPHY registers.
9 - clocks: DPHY reference clocks.
10 - clock-names: must contain "psm" and "pll_ref".
11 - #phy-cells: must be set to 0.
18 clock-names = "psm", "pll_ref";
19 #phy-cells = <0>;
H A Dcdns,dphy-rx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/cdns,dphy-rx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence DPHY Rx
10 - Pratyush Yadav <pratyush@kernel.org>
15 - const: cdns,dphy-rx
20 "#phy-cells":
23 power-domains:
27 - compatible
[all …]
H A Dti,phy-j721e-wiz.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
[all...]
H A Dcdns,salvo-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/cdns,salvo-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Cadence SALVO PHY
11 - Peter Chen <peter.chen@nxp.com>
16 - nxp,salvo-phy
24 clock-names:
26 - const: salvo_phy_clk
28 power-domains:
[all …]
H A Dcdns,dphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/cdns,dphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence DPHY
10 - Pratyush Yadav <pratyush@kernel.org>
15 - cdns,dphy
16 - ti,j721e-dphy
23 - description: PMA state machine clock
24 - description: PLL reference clock
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/bridge/
H A Dcdns,mhdp8546.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence MHDP8546 bridge
10 - Swapnil Jakhade <sjakhade@cadence.com>
11 - Yuti Amonkar <yamonkar@cadence.com>
16 - cdns,mhdp8546
17 - ti,j721e-mhdp8546
22 - description:
23 Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P).
[all …]
H A Dcdns,dsi.txt1 Cadence DSI bridge
4 The Cadence DSI bridge is a DPI to DSI bridge supporting up to 4 DSI lanes.
7 - compatible: should be set to "cdns,dsi".
8 - reg: physical base address and length of the controller's registers.
9 - interrupts: interrupt line connected to the DSI bridge.
10 - clocks: DSI bridge clocks.
11 - clock-names: must contain "dsi_p_clk" and "dsi_sys_clk".
12 - phys: phandle link to the MIPI D-PHY controller.
13 - phy-names: must contain "dphy".
14 - #address-cells: must be set to 1.
[all …]
H A Dcdns,dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence DSI bridge
10 - Boris Brezillon <boris.brezillon@bootlin.com>
18 - cdns,dsi
19 - ti,j721e-dsi
24 - description:
26 - description:
31 - description: PSM clock, used by the IP
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dcdns-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/cdns-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence PCIe Core
10 - Tom Joseph <tjoseph@cadence.com>
15 One per lane if more than one in the list. If only one PHY listed it must
20 phy-names:
22 - const: pcie-phy
H A Dcdns,cdns-pcie-ep.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence PCIe EP Controller
10 - Tom Joseph <tjoseph@cadence.com>
13 - $ref: cdns-pcie-ep.yaml#
17 const: cdns,cdns-pcie-ep
22 reg-names:
24 - const: reg
[all …]
H A Dcdns,cdns-pcie-host.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence PCIe host controller
10 - Tom Joseph <tjoseph@cadence.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
14 - $ref: cdns-pcie-host.yaml#
18 const: cdns,cdns-pcie-host
23 reg-names:
[all …]
/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Dcdns,usb3.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence USBSS-DRD controller
10 - Pawel Laszczak <pawell@cadence.com>
18 - description: OTG controller registers
19 - description: XHCI Host controller registers
20 - description: DEVICE controller registers
22 reg-names:
24 - const: otg
[all …]
H A Dcdns-usb3.txt1 Binding for the Cadence USBSS-DRD controller
4 - reg: Physical base address and size of the controller's register areas.
6 - HOST registers area
7 - DEVICE registers area
8 - OTG/DRD registers area
9 - reg-names - register memory area names:
10 "xhci" - for HOST registers space
11 "dev" - for DEVICE registers space
12 "otg" - for OTG/DRD registers space
13 - compatible: Should contain: "cdns,usb3"
[all …]
/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dcdns,csi2rx.txt1 Cadence MIPI-CSI2 RX controller
4 The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI
8 - compatible: must be set to "cdns,csi2rx" and an SoC-specific compatible
9 - reg: base address and size of the memory mapped region
10 - clocks: phandles to the clocks driving the controller
11 - clock-names: must contain:
14 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
18 - phys: phandle to the external D-PHY, phy-names must be provided
19 - phy-names: must contain "dphy", if the implementation uses an
20 external D-PHY
[all …]
H A Dcdns,csi2tx.txt1 Cadence MIPI-CSI2 TX controller
4 The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to
8 - compatible: must be set to "cdns,csi2tx" or "cdns,csi2tx-1.3"
9 for version 1.3 of the controller, "cdns,csi2tx-2.1" for v2.1
10 - reg: base address and size of the memory mapped region
11 - clocks: phandles to the clocks driving the controller
12 - clock-names: must contain:
15 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
19 - phys: phandle to the D-PHY. If it is set, phy-names need to be set
20 - phy-names: must contain "dphy"
[all …]
/freebsd/sys/contrib/device-tree/Bindings/ufs/
H A Dcdns,ufshc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence Universal Flash Storage (UFS) Controller
10 - Jan Kotas <jank@cadence.com>
12 # Select only our matches, not all jedec,ufs-2.0
18 - cdns,ufshc
19 - cdns,ufshc-m31-16nm
21 - compatible
24 - $ref: ufs-common.yaml
[all …]
H A Dcdns,ufshc.txt1 * Cadence Universal Flash Storage (UFS) Controller
3 UFS nodes are defined to describe on-chip UFS host controllers.
5 Please see the ufshcd-pltfrm.txt for a list of all available properties.
8 - compatible : Compatible list, contains one of the following controllers:
9 "cdns,ufshc" - Generic CDNS HCI,
10 "cdns,ufshc-m31-16nm" - CDNS UFS HC + M31 16nm PHY
12 "jedec,ufs-2.0"
14 - reg : Address and length of the UFS register set.
15 - interrupts : One interrupt mapping.
16 - freq-table-hz : Clock frequency table.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dmacb.txt1 * Cadence MACB/GEM Ethernet controller
4 - compatible: Should be "cdns,[<chip>-]{macb|gem}"
5 Use "cdns,at91rm9200-emac" Atmel at91rm9200 SoC.
6 Use "cdns,at91sam9260-macb" for Atmel at91sam9 SoCs.
7 Use "cdns,sam9x60-macb" for Microchip sam9x60 SoC.
8 Use "cdns,np4-macb" for NP4 SoC devices.
9 Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form: "cdns,macb".
10 Use "atmel,sama5d2-gem" for the GEM IP (10/100) available on Atmel sama5d2 SoCs.
11 Use "atmel,sama5d29-gem" for GEM XL IP (10/100) available on Atmel sama5d29 SoCs.
12 Use "atmel,sama5d3-macb" for the 10/100Mbit IP available on Atmel sama5d3 SoCs.
[all …]
H A Dcdns,macb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence MACB/GEM Ethernet controller
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
16 - items:
17 - enum:
18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC
19 - const: cdns,emac # Generic
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-j721e-evm-quad-port-eth-exp.dtso1 // SPDX-License-Identifier: GPL-2.0
3 * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
6 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
9 /dts-v1/;
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/phy/phy
[all...]
/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dcdns,sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence SD/SDIO/eMMC Host Controller (SD4HC)
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
15 - enum:
16 - amd,pensando-elba-sd4hc
17 - microchip,mpfs-sd4hc
18 - socionext,uniphier-sd4hc
19 - const: cdns,sd4hc
[all …]
/freebsd/sys/arm/conf/
H A DZEDBOARD2 # ZEDBOARD -- Custom configuration for the Xilinx Zynq-7000 based
8 # https://docs.freebsd.org/en/books/handbook/kernelconfig/#kernelconfig-config
46 device phy
59 device cgem # Cadence GEM Gigabit Ethernet device
85 device axe # USB-Ethernet

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