Lines Matching +full:phy +full:- +full:cadence

1 Cadence MIPI-CSI2 TX controller
4 The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to
8   - compatible: must be set to "cdns,csi2tx" or "cdns,csi2tx-1.3"
9     for version 1.3 of the controller, "cdns,csi2tx-2.1" for v2.1
10   - reg: base address and size of the memory mapped region
11   - clocks: phandles to the clocks driving the controller
12   - clock-names: must contain:
15     * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
19   - phys: phandle to the D-PHY. If it is set, phy-names need to be set
20   - phy-names: must contain "dphy"
23   - ports: A ports node with one port child node per device input and output
25            Documentation/devicetree/bindings/media/video-interfaces.txt. The
29            -----------------------------
30            0    CSI-2 output
43 csi2tx: csi-bridge@0d0e1000 {
49 	clock-names = "p_clk", "esc_clk",
54 		#address-cells = <1>;
55 		#size-cells = <0>;
61 				remote-endpoint = <&remote_in>;
62 				clock-lanes = <0>;
63 				data-lanes = <1 2>;
71 				remote-endpoint = <&stream0_out>;
79 				remote-endpoint = <&stream1_out>;
87 				remote-endpoint = <&stream2_out>;
95 				remote-endpoint = <&stream3_out>;