| /linux/drivers/clk/hisilicon/ |
| H A D | clk-hisi-phase.c | 5 * Simple HiSilicon phase clock implementation.
30 static int hisi_phase_regval_to_degrees(struct clk_hisi_phase *phase, in hisi_phase_regval_to_degrees() argument
35 for (i = 0; i < phase->phase_num; i++) in hisi_phase_regval_to_degrees()
36 if (phase->phase_regvals[i] == regval) in hisi_phase_regval_to_degrees()
37 return phase->phase_degrees[i]; in hisi_phase_regval_to_degrees()
44 struct clk_hisi_phase *phase = to_clk_hisi_phase(hw); in hisi_clk_get_phase() local
47 regval = readl(phase->reg); in hisi_clk_get_phase()
48 regval = (regval & phase->mask) >> phase->shift; in hisi_clk_get_phase()
50 return hisi_phase_regval_to_degrees(phase, regval); in hisi_clk_get_phase()
53 static int hisi_phase_degrees_to_regval(struct clk_hisi_phase *phase, in hisi_phase_degrees_to_regval() argument
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_clock_source.h | 60 SRII(PHASE, DP_DTO, 0),\
61 SRII(PHASE, DP_DTO, 1),\
62 SRII(PHASE, DP_DTO, 2),\
63 SRII(PHASE, DP_DTO, 3),\
64 SRII(PHASE, DP_DTO, 4),\
65 SRII(PHASE, DP_DTO, 5),\
81 SRII(PHASE, DP_DTO, 0),\
82 SRII(PHASE, DP_DTO, 1),\
90 SRII(PHASE, DP_DTO, 0),\
91 SRII(PHASE, DP_DTO, 1),\
[all …]
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| /linux/drivers/clk/sunxi-ng/ |
| H A D | ccu_phase.c | 15 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_get_phase() local
22 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_get_phase()
23 delay = (reg >> phase->shift); in ccu_phase_get_phase()
24 delay &= (1 << phase->width) - 1; in ccu_phase_get_phase()
58 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_set_phase() local
110 spin_lock_irqsave(phase->common.lock, flags); in ccu_phase_set_phase()
111 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_set_phase()
112 reg &= ~GENMASK(phase->width + phase->shift - 1, phase->shift); in ccu_phase_set_phase()
113 writel(reg | (delay << phase->shift), in ccu_phase_set_phase()
114 phase->common.base + phase->common.reg); in ccu_phase_set_phase()
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| /linux/drivers/hwmon/pmbus/ |
| H A D | mp2888.c | 3 * Hardware monitoring driver for MPS Multi-phase Digital VR Controllers
83 * Obtain resolution selector for total and phase current report and protection. in mp2888_current_sense_gain_and_resolution_get()
84 * 0: original resolution; 1: half resolution (in such case phase current value should in mp2888_current_sense_gain_and_resolution_get()
94 mp2888_read_phase(struct i2c_client *client, struct mp2888_data *data, int page, int phase, u8 reg) in mp2888_read_phase() argument
98 ret = pmbus_read_word_data(client, page, phase, reg); in mp2888_read_phase()
102 if (!((phase + 1) % 2)) in mp2888_read_phase()
113 * - Rcs is the internal phase current sense resistor. This parameter depends on hardware in mp2888_read_phase()
116 * If phase current resolution bit is set to 1, READ_CSx value should be doubled. in mp2888_read_phase()
117 * Note, that current phase sensing, providing by the device is not accurate. This is in mp2888_read_phase()
128 mp2888_read_phases(struct i2c_client *client, struct mp2888_data *data, int page, int phase) in mp2888_read_phases() argument
[all …]
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| H A D | mp2975.c | 3 * Hardware monitoring driver for MPS Multi-phase Digital VR Controllers
143 mp2975_read_word_helper(struct i2c_client *client, int page, int phase, u8 reg, in mp2975_read_word_helper() argument
146 int ret = pmbus_read_word_data(client, page, phase, reg); in mp2975_read_word_helper()
210 int page, int phase, u8 reg) in mp2975_read_phase() argument
214 ret = pmbus_read_word_data(client, page, phase, reg); in mp2975_read_phase()
218 if (!((phase + 1) % MP2975_PAGE_NUM)) in mp2975_read_phase()
229 * - Rcs is the internal phase current sense resistor which is constant in mp2975_read_phase()
235 * Current phase sensing, providing by the device is not accurate in mp2975_read_phase()
238 * case phase current is represented as the maximum between the value in mp2975_read_phase()
241 ret = pmbus_read_word_data(client, page, phase, PMBUS_READ_IOUT); in mp2975_read_phase()
[all …]
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| H A D | mp2856.c | 112 mp2856_read_word_helper(struct i2c_client *client, int page, int phase, u8 reg, in mp2856_read_word_helper() argument
115 int ret = pmbus_read_word_data(client, page, phase, reg); in mp2856_read_word_helper()
122 int phase, u8 reg) in mp2856_read_vout() argument
126 ret = mp2856_read_word_helper(client, page, phase, reg, in mp2856_read_vout()
140 int page, int phase, u8 reg) in mp2856_read_phase() argument
145 ret = pmbus_read_word_data(client, page, phase, reg); in mp2856_read_phase()
149 if (!((phase + 1) % MP2856_PAGE_NUM)) in mp2856_read_phase()
163 int page, int phase) in mp2856_read_phases() argument
168 switch (phase) { in mp2856_read_phases()
170 ret = mp2856_read_phase(client, data, page, phase, in mp2856_read_phases()
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| H A D | ir35221.c | 25 int phase, int reg) in ir35221_read_word_data() argument
31 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
35 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
39 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
43 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
47 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
51 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
55 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
59 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
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| /linux/drivers/clk/sunxi/ |
| H A D | clk-mod0.c | 173 struct mmc_phase *phase = to_mmc_phase(hw); in mmc_get_phase() local
179 value = readl(phase->reg); in mmc_get_phase()
180 delay = (value >> phase->offset) & 0x3; in mmc_get_phase()
215 struct mmc_phase *phase = to_mmc_phase(hw); in mmc_set_phase() local
266 spin_lock_irqsave(phase->lock, flags); in mmc_set_phase()
267 value = readl(phase->reg); in mmc_set_phase()
268 value &= ~GENMASK(phase->offset + 3, phase->offset); in mmc_set_phase()
269 value |= delay << phase->offset; in mmc_set_phase()
270 writel(value, phase->reg); in mmc_set_phase()
271 spin_unlock_irqrestore(phase->lock, flags); in mmc_set_phase()
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| /linux/Documentation/devicetree/bindings/mmc/ |
| H A D | samsung,exynos-dw-mshc.yaml | 61 - description: CIU clock phase shift value for tx mode
64 - description: CIU clock phase shift value for rx mode
68 The value of CUI clock phase shift value in transmit mode and CIU clock
69 phase shift value in receive mode for double data rate mode operation.
75 - description: CIU clock phase shift value for tx mode
78 - description: CIU clock phase shift value for rx mode
82 The value of CIU TX and RX clock phase shift value for HS400 mode
85 - valid value for tx phase shift and rx phase shift is 0 to 7.
86 - when CIU clock divider value is set to 3, all possible 8 phase shift
89 phase shift clocks should be 0.
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| /linux/drivers/clk/meson/ |
| H A D | clk-phase.c | 11 #include "clk-phase.h"
40 struct meson_clk_phase_data *phase = meson_clk_phase_data(clk); in meson_clk_phase_get_phase() local
43 val = meson_parm_read(clk->map, &phase->ph); in meson_clk_phase_get_phase()
45 return meson_clk_degrees_from_val(val, phase->ph.width); in meson_clk_phase_get_phase()
51 struct meson_clk_phase_data *phase = meson_clk_phase_data(clk); in meson_clk_phase_set_phase() local
54 val = meson_clk_degrees_to_val(degrees, phase->ph.width); in meson_clk_phase_set_phase()
55 meson_parm_write(clk->map, &phase->ph, val); in meson_clk_phase_set_phase()
68 * The phase of mst_sclk clock output can be controlled independently
72 * If necessary, we can still control the phase in the tdm block
87 /* Get phase 0 and sync it to phase 1 and 2 */ in meson_clk_triphase_sync()
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| /linux/drivers/gpu/drm/tidss/ |
| H A D | tidss_dispc_regs.h | 120 #define DISPC_VID_FIR_COEF_H0(phase) (0x6c + (phase) * 4) argument
122 #define DISPC_VID_FIR_COEF_H0_C(phase) (0x90 + (phase) * 4) argument
125 #define DISPC_VID_FIR_COEF_H12(phase) (0xb4 + (phase) * 4) argument
127 #define DISPC_VID_FIR_COEF_H12_C(phase) (0xf4 + (phase) * 4) argument
130 #define DISPC_VID_FIR_COEF_V0(phase) (0x134 + (phase) * 4) argument
132 #define DISPC_VID_FIR_COEF_V0_C(phase) (0x158 + (phase) * 4) argument
135 #define DISPC_VID_FIR_COEF_V12(phase) (0x17c + (phase) * 4) argument
137 #define DISPC_VID_FIR_COEF_V12_C(phase) (0x1bc + (phase) * 4) argument
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn21/ |
| H A D | dcn21_dccg.c | 53 int phase; in dccg21_update_dpp_dto() local
57 * program DPP DTO phase and modulo as below in dccg21_update_dpp_dto()
58 * phase = ceiling(dpp_pipe_clk_mhz / 10) in dccg21_update_dpp_dto()
64 * ceiling phase and truncate modulo guarentees the divided in dccg21_update_dpp_dto()
67 phase = (req_dppclk + 9999) / 10000; in dccg21_update_dpp_dto()
69 if (phase > modulo) { in dccg21_update_dpp_dto()
70 /* phase > modulo result in screen corruption in dccg21_update_dpp_dto()
71 * ie phase = 30, mod = 29 for 4k@60 HDMI in dccg21_update_dpp_dto()
74 phase = modulo; in dccg21_update_dpp_dto()
78 * set phase to 10 if dpp isn't used to in dccg21_update_dpp_dto()
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| /linux/drivers/net/wwan/iosm/ |
| H A D | iosm_ipc_imem_ops.c | 19 ipc_imem_phase_get_string(ipc_imem->phase), if_id); in ipc_imem_sys_wwan_open()
21 /* The network interface is only supported in the runtime phase. */ in ipc_imem_sys_wwan_open()
23 dev_err(ipc_imem->dev, "net:%d : refused phase %s", if_id, in ipc_imem_sys_wwan_open()
24 ipc_imem_phase_get_string(ipc_imem->phase)); in ipc_imem_sys_wwan_open()
66 if (ipc_imem->phase != IPC_P_RUN) { in ipc_imem_sys_wwan_transmit()
67 dev_dbg(ipc_imem->dev, "phase %s transmit", in ipc_imem_sys_wwan_transmit()
68 ipc_imem_phase_get_string(ipc_imem->phase)); in ipc_imem_sys_wwan_transmit()
146 enum ipc_phase phase; in ipc_imem_is_channel_active() local
148 /* Update the current operation phase. */ in ipc_imem_is_channel_active()
149 phase = ipc_imem->phase; in ipc_imem_is_channel_active()
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| H A D | iosm_ipc_imem.c | 180 /* Use the TD update timer only in the runtime phase */ in ipc_imem_td_update_timer_start()
291 ipc_imem_phase_get_string(ipc_imem->phase), in ipc_imem_ipc_init_check()
404 /* Get the internal phase. */ in ipc_imem_ul_pipe_process()
468 /* Consider link power management in the runtime phase. */
487 /* Update & check the current operation phase. */ in ipc_imem_tq_startup_timer_cb()
540 return (ipc_imem->phase == IPC_P_RUN && in ipc_imem_get_exec_stage_buffered()
572 if (ipc_imem->phase != IPC_P_RUN) { in ipc_imem_run_state_worker()
645 enum ipc_phase old_phase, phase; in ipc_imem_handle_irq() local
653 /* Get the internal phase. */ in ipc_imem_handle_irq()
654 old_phase = ipc_imem->phase; in ipc_imem_handle_irq()
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| /linux/drivers/char/ |
| H A D | ppdev.c | 20 * SETPHASE set the IEEE 1284 phase of a particular mode. Not to be
37 * GETPHASE gets the current IEEE1284 phase
404 pp->saved_state.phase = info->phase; in pp_do_ioctl()
406 info->phase = pp->state.phase; in pp_do_ioctl()
435 pp->state.phase = init_phase(mode); in pp_do_ioctl()
439 pp->pdev->port->ieee1284.phase = pp->state.phase; in pp_do_ioctl()
459 int phase; in pp_do_ioctl() local
461 if (copy_from_user(&phase, argp, sizeof(phase))) in pp_do_ioctl()
464 /* FIXME: validate phase */ in pp_do_ioctl()
465 pp->state.phase = phase; in pp_do_ioctl()
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| /linux/include/linux/regulator/ |
| H A D | da9121.h | 3 * DA9121 Single-channel dual-phase 10A buck converter
4 * DA9130 Single-channel dual-phase 10A buck converter (Automotive)
5 * DA9217 Single-channel dual-phase 6A buck converter
6 * DA9122 Dual-channel single-phase 5A buck converter
7 * DA9131 Dual-channel single-phase 5A buck converter (Automotive)
8 * DA9220 Dual-channel single-phase 3A buck converter
9 * DA9132 Dual-channel single-phase 3A buck converter (Automotive)
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| /linux/drivers/media/i2c/ |
| H A D | saa711x_regs.h | 112 /* Horizontal phase scaling */
159 /* Horizontal phase scaling */
422 /* Task A: Horizontal phase scaling */
426 "Task A: Horizontal luminance phase offset"},
431 "Task A: Horizontal chrominance phase offset"},
443 "Task A: Vertical chrominance phase offset '00'"},
445 "Task A: Vertical chrominance phase offset '01'"},
447 "Task A: Vertical chrominance phase offset '10'"},
449 "Task A: Vertical chrominance phase offset '11'"},
451 "Task A: Vertical luminance phase offset '00'"},
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| /linux/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| H A D | uncore-power.json | 30 "BriefDescription": "Phase Shed 0 Cycles",
36 "PublicDescription": "Phase Shed 0 Cycles : Cycles spent in phase-shedding power state 0",
40 "BriefDescription": "Phase Shed 1 Cycles",
46 "PublicDescription": "Phase Shed 1 Cycles : Cycles spent in phase-shedding power state 1",
50 "BriefDescription": "Phase Shed 2 Cycles",
56 "PublicDescription": "Phase Shed 2 Cycles : Cycles spent in phase-shedding power state 2",
60 "BriefDescription": "Phase Shed 3 Cycles",
66 "PublicDescription": "Phase Shed 3 Cycles : Cycles spent in phase-shedding power state 3",
128 "BriefDescription": "Memory Phase Shedding Cycles",
134 …"PublicDescription": "Memory Phase Shedding Cycles : Counts the number of cycles that the PCU has …
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| /linux/tools/perf/pmu-events/arch/x86/emeraldrapids/ |
| H A D | uncore-power.json | 30 "BriefDescription": "Phase Shed 0 Cycles",
36 "PublicDescription": "Phase Shed 0 Cycles : Cycles spent in phase-shedding power state 0",
40 "BriefDescription": "Phase Shed 1 Cycles",
46 "PublicDescription": "Phase Shed 1 Cycles : Cycles spent in phase-shedding power state 1",
50 "BriefDescription": "Phase Shed 2 Cycles",
56 "PublicDescription": "Phase Shed 2 Cycles : Cycles spent in phase-shedding power state 2",
60 "BriefDescription": "Phase Shed 3 Cycles",
66 "PublicDescription": "Phase Shed 3 Cycles : Cycles spent in phase-shedding power state 3",
128 "BriefDescription": "Memory Phase Shedding Cycles",
134 …"PublicDescription": "Memory Phase Shedding Cycles : Counts the number of cycles that the PCU has …
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| /linux/Documentation/devicetree/bindings/watchdog/ |
| H A D | realtek,otto-wdt.yaml | 15 minimum duration of each phase is one tick. Each phase can trigger an
16 interrupt, although the phase 2 interrupt will occur with the system reset.
17 - Phase 1: During this phase, the WDT can be pinged to reset the timeout.
18 - Phase 2: Starts after phase 1 has timed out, and only serves to give the
20 During this phase, pinging the WDT has no effect, and a reset is
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| /linux/tools/perf/pmu-events/arch/x86/snowridgex/ |
| H A D | uncore-power.json | 28 "BriefDescription": "Phase Shed 0 Cycles",
34 "PublicDescription": "Phase Shed 0 Cycles : Cycles spent in phase-shedding power state 0",
38 "BriefDescription": "Phase Shed 1 Cycles",
44 "PublicDescription": "Phase Shed 1 Cycles : Cycles spent in phase-shedding power state 1",
48 "BriefDescription": "Phase Shed 2 Cycles",
54 "PublicDescription": "Phase Shed 2 Cycles : Cycles spent in phase-shedding power state 2",
58 "BriefDescription": "Phase Shed 3 Cycles",
64 "PublicDescription": "Phase Shed 3 Cycles : Cycles spent in phase-shedding power state 3",
126 "BriefDescription": "Memory Phase Shedding Cycles",
132 …"PublicDescription": "Memory Phase Shedding Cycles : Counts the number of cycles that the PCU has …
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| /linux/drivers/mmc/core/ |
| H A D | host.c | 222 struct mmc_clk_phase *phase) in mmc_of_parse_timing_phase() argument
228 phase->valid = !rc; in mmc_of_parse_timing_phase()
229 if (phase->valid) { in mmc_of_parse_timing_phase()
230 phase->in_deg = degrees[0]; in mmc_of_parse_timing_phase()
231 phase->out_deg = degrees[1]; in mmc_of_parse_timing_phase()
238 mmc_of_parse_timing_phase(dev, "clk-phase-legacy", in mmc_of_parse_clk_phase()
239 &map->phase[MMC_TIMING_LEGACY]); in mmc_of_parse_clk_phase()
240 mmc_of_parse_timing_phase(dev, "clk-phase-mmc-hs", in mmc_of_parse_clk_phase()
241 &map->phase[MMC_TIMING_MMC_HS]); in mmc_of_parse_clk_phase()
242 mmc_of_parse_timing_phase(dev, "clk-phase-sd-hs", in mmc_of_parse_clk_phase()
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| /linux/drivers/scsi/ |
| H A D | NCR5380.c | 74 * phase goes through the various phases as instructed by the target.
256 {BASR_PHASE_MATCH, "PHASE MATCH"},
335 * NCR5380_print_phase - show SCSI phase
338 * Print the current SCSI phase for debugging purposes
349 shost_printk(KERN_DEBUG, instance, "REQ not asserted, phase unknown.\n"); in NCR5380_print_phase()
354 shost_printk(KERN_DEBUG, instance, "phase %s\n", phases[i].name); in NCR5380_print_phase()
459 * the SCSI bus busy. Check for BUS FREE phase. If not, try to abort the
748 * Called by the interrupt handler when DMA finishes or a phase
763 p = ncmd->phase; in NCR5380_dma_complete()
787 pr_err("scsi%d: bus stuck in data phase -- probably a single byte overrun!\n", in NCR5380_dma_complete()
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| /linux/drivers/staging/iio/Documentation/ |
| H A D | sysfs-bus-iio-dds | 36 Stores phase into Y.
38 allows for pin controlled PSK Phase Shift Keying
40 control the desired phase Y which is added to the phase
48 the desired value in rad. If shared across all phase registers
56 Specifies the active phase Y which is added to the phase
68 phase is controlled by the respective phase and frequency
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| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-driver-zynqmp-fpga | 57 Phase 0 = 000
58 Phase 1 = 001
59 Phase 2 = 011
60 Phase 3 = 010
61 Phase 4 = 110
62 Phase 5 = 111
63 Phase 6 = 101
64 Phase 7 = 100
|