| /linux/drivers/clk/hisilicon/ |
| H A D | clk-hisi-phase.c | 5 * Simple HiSilicon phase clock implementation.
30 static int hisi_phase_regval_to_degrees(struct clk_hisi_phase *phase, in hisi_phase_regval_to_degrees() argument
35 for (i = 0; i < phase->phase_num; i++) in hisi_phase_regval_to_degrees()
36 if (phase->phase_regvals[i] == regval) in hisi_phase_regval_to_degrees()
37 return phase->phase_degrees[i]; in hisi_phase_regval_to_degrees()
44 struct clk_hisi_phase *phase = to_clk_hisi_phase(hw); in hisi_clk_get_phase() local
47 regval = readl(phase->reg); in hisi_clk_get_phase()
48 regval = (regval & phase->mask) >> phase->shift; in hisi_clk_get_phase()
50 return hisi_phase_regval_to_degrees(phase, regval); in hisi_clk_get_phase()
53 static int hisi_phase_degrees_to_regval(struct clk_hisi_phase *phase, in hisi_phase_degrees_to_regval() argument
[all …]
|
| /linux/drivers/clk/sunxi-ng/ |
| H A D | ccu_phase.c | 15 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_get_phase() local
22 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_get_phase()
23 delay = (reg >> phase->shift); in ccu_phase_get_phase()
24 delay &= (1 << phase->width) - 1; in ccu_phase_get_phase()
58 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_set_phase() local
110 spin_lock_irqsave(phase->common.lock, flags); in ccu_phase_set_phase()
111 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_set_phase()
112 reg &= ~GENMASK(phase->width + phase->shift - 1, phase->shift); in ccu_phase_set_phase()
113 writel(reg | (delay << phase->shift), in ccu_phase_set_phase()
114 phase->common.base + phase->common.reg); in ccu_phase_set_phase()
[all …]
|
| /linux/drivers/clk/sunxi/ |
| H A D | clk-mod0.c | 173 struct mmc_phase *phase = to_mmc_phase(hw); in mmc_get_phase() local
179 value = readl(phase->reg); in mmc_get_phase()
180 delay = (value >> phase->offset) & 0x3; in mmc_get_phase()
215 struct mmc_phase *phase = to_mmc_phase(hw); in mmc_set_phase() local
266 spin_lock_irqsave(phase->lock, flags); in mmc_set_phase()
267 value = readl(phase->reg); in mmc_set_phase()
268 value &= ~GENMASK(phase->offset + 3, phase->offset); in mmc_set_phase()
269 value |= delay << phase->offset; in mmc_set_phase()
270 writel(value, phase->reg); in mmc_set_phase()
271 spin_unlock_irqrestore(phase->lock, flags); in mmc_set_phase()
[all …]
|
| /linux/drivers/net/wwan/iosm/ |
| H A D | iosm_ipc_imem_ops.c | 19 ipc_imem_phase_get_string(ipc_imem->phase), if_id); in ipc_imem_sys_wwan_open()
21 /* The network interface is only supported in the runtime phase. */ in ipc_imem_sys_wwan_open()
23 dev_err(ipc_imem->dev, "net:%d : refused phase %s", if_id, in ipc_imem_sys_wwan_open()
24 ipc_imem_phase_get_string(ipc_imem->phase)); in ipc_imem_sys_wwan_open()
66 if (ipc_imem->phase != IPC_P_RUN) { in ipc_imem_sys_wwan_transmit()
67 dev_dbg(ipc_imem->dev, "phase %s transmit", in ipc_imem_sys_wwan_transmit()
68 ipc_imem_phase_get_string(ipc_imem->phase)); in ipc_imem_sys_wwan_transmit()
146 enum ipc_phase phase; in ipc_imem_is_channel_active() local
148 /* Update the current operation phase. */ in ipc_imem_is_channel_active()
149 phase = ipc_imem->phase; in ipc_imem_is_channel_active()
[all …]
|
| H A D | iosm_ipc_imem.c | 180 /* Use the TD update timer only in the runtime phase */ in ipc_imem_td_update_timer_start()
291 ipc_imem_phase_get_string(ipc_imem->phase), in ipc_imem_ipc_init_check()
404 /* Get the internal phase. */ in ipc_imem_ul_pipe_process()
468 /* Consider link power management in the runtime phase. */
487 /* Update & check the current operation phase. */ in ipc_imem_tq_startup_timer_cb()
540 return (ipc_imem->phase == IPC_P_RUN && in ipc_imem_get_exec_stage_buffered()
572 if (ipc_imem->phase != IPC_P_RUN) { in ipc_imem_run_state_worker()
645 enum ipc_phase old_phase, phase; in ipc_imem_handle_irq() local
653 /* Get the internal phase. */ in ipc_imem_handle_irq()
654 old_phase = ipc_imem->phase; in ipc_imem_handle_irq()
[all …]
|
| H A D | iosm_ipc_imem.h | 254 * respond to any requests. So while introducing new phase
259 * driver call the device power mode D3hot. In this phase
262 * @IPC_P_OFF_REQ: The intermediate phase between cleanup activity starts
264 * @IPC_P_CRASH: The phase indicating CP crash
265 * @IPC_P_CD_READY: The phase indicating CP core dump is ready
269 * @IPC_P_PSI: Primary signed image download phase
271 * @IPC_P_RUN: The phase after flashing to RAM is the RUNTIME phase.
309 * @enter_runtime: 1 means the transition to runtime phase was
317 * @phase: Operating phase like runtime.
363 enum ipc_phase phase; member
[all …]
|
| /linux/drivers/hwmon/pmbus/ |
| H A D | mp2975.c | 3 * Hardware monitoring driver for MPS Multi-phase Digital VR Controllers
142 mp2975_read_word_helper(struct i2c_client *client, int page, int phase, u8 reg, in mp2975_read_word_helper() argument
145 int ret = pmbus_read_word_data(client, page, phase, reg); in mp2975_read_word_helper()
204 int page, int phase, u8 reg) in mp2975_read_phase() argument
208 ret = pmbus_read_word_data(client, page, phase, reg); in mp2975_read_phase()
212 if (!((phase + 1) % MP2975_PAGE_NUM)) in mp2975_read_phase()
223 * - Rcs is the internal phase current sense resistor which is constant in mp2975_read_phase()
229 * Current phase sensing, providing by the device is not accurate in mp2975_read_phase()
232 * case phase current is represented as the maximum between the value in mp2975_read_phase()
235 ret = pmbus_read_word_data(client, page, phase, PMBUS_READ_IOUT); in mp2975_read_phase()
[all …]
|
| /linux/Documentation/netlink/specs/ |
| H A D | dpll.yaml | 216 doc: pin connected, active input of phase locked loop
244 doc: pin signal failed qualification (e.g. frequency or phase monitor)
270 name: phase-offset-divider
273 phase offset divider allows userspace to calculate a value of
274 measured signal phase difference between a pin and dpll device
277 integer part of a measured phase offset value.
279 fractional part of a measured phase offset value.
362 name: phase-offset-monitor
365 doc: Receive or request state of phase offset monitor feature.
367 available inputs for changes of their phase offset against the
[all …]
|
| /linux/drivers/gpu/drm/imx/dcss/ |
| H A D | dcss-scaler.c | 169 * @phase0_identity: whether to override phase 0 coefficients with identity filter
179 int phase; in dcss_scaler_gaussian_filter() local
184 for (phase = 0; phase < PSC_STORED_PHASES; phase++) { in dcss_scaler_gaussian_filter()
185 coef[phase][0] = 0; in dcss_scaler_gaussian_filter()
186 coef[phase][PSC_NUM_TAPS - 1] = 0; in dcss_scaler_gaussian_filter()
226 /* override phase 0 with identity filter if specified */ in dcss_scaler_gaussian_filter()
233 for (phase = 0; phase < PSC_STORED_PHASES; phase++) { in dcss_scaler_gaussian_filter()
238 sum += coef[phase][i]; in dcss_scaler_gaussian_filter()
240 ll_temp = coef[phase][i]; in dcss_scaler_gaussian_filter()
244 coef[phase][i] = (int)ll_temp; in dcss_scaler_gaussian_filter()
[all …]
|
| /linux/include/linux/regulator/ |
| H A D | da9121.h | 3 * DA9121 Single-channel dual-phase 10A buck converter
4 * DA9130 Single-channel dual-phase 10A buck converter (Automotive)
5 * DA9217 Single-channel dual-phase 6A buck converter
6 * DA9122 Dual-channel single-phase 5A buck converter
7 * DA9131 Dual-channel single-phase 5A buck converter (Automotive)
8 * DA9220 Dual-channel single-phase 3A buck converter
9 * DA9132 Dual-channel single-phase 3A buck converter (Automotive)
|
| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn21/ |
| H A D | dcn21_dccg.c | 53 int phase; in dccg21_update_dpp_dto() local
57 * program DPP DTO phase and modulo as below in dccg21_update_dpp_dto()
58 * phase = ceiling(dpp_pipe_clk_mhz / 10) in dccg21_update_dpp_dto()
64 * ceiling phase and truncate modulo guarentees the divided in dccg21_update_dpp_dto()
67 phase = (req_dppclk + 9999) / 10000; in dccg21_update_dpp_dto()
69 if (phase > modulo) { in dccg21_update_dpp_dto()
70 /* phase > modulo result in screen corruption in dccg21_update_dpp_dto()
71 * ie phase = 30, mod = 29 for 4k@60 HDMI in dccg21_update_dpp_dto()
74 phase = modulo; in dccg21_update_dpp_dto()
78 * set phase to 10 if dpp isn't used to in dccg21_update_dpp_dto()
[all …]
|
| /linux/drivers/char/ |
| H A D | ppdev.c | 20 * SETPHASE set the IEEE 1284 phase of a particular mode. Not to be
37 * GETPHASE gets the current IEEE1284 phase
404 pp->saved_state.phase = info->phase; in pp_do_ioctl()
406 info->phase = pp->state.phase; in pp_do_ioctl()
435 pp->state.phase = init_phase(mode); in pp_do_ioctl()
439 pp->pdev->port->ieee1284.phase = pp->state.phase; in pp_do_ioctl()
459 int phase; in pp_do_ioctl() local
461 if (copy_from_user(&phase, argp, sizeof(phase))) in pp_do_ioctl()
464 /* FIXME: validate phase */ in pp_do_ioctl()
465 pp->state.phase = phase; in pp_do_ioctl()
[all …]
|
| /linux/drivers/media/i2c/ |
| H A D | saa711x_regs.h | 112 /* Horizontal phase scaling */
159 /* Horizontal phase scaling */
422 /* Task A: Horizontal phase scaling */
426 "Task A: Horizontal luminance phase offset"},
431 "Task A: Horizontal chrominance phase offset"},
443 "Task A: Vertical chrominance phase offset '00'"},
445 "Task A: Vertical chrominance phase offset '01'"},
447 "Task A: Vertical chrominance phase offset '10'"},
449 "Task A: Vertical chrominance phase offset '11'"},
451 "Task A: Vertical luminance phase offset '00'"},
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| H A D | uncore-power.json | 30 "BriefDescription": "Phase Shed 0 Cycles",
36 "PublicDescription": "Phase Shed 0 Cycles : Cycles spent in phase-shedding power state 0",
40 "BriefDescription": "Phase Shed 1 Cycles",
46 "PublicDescription": "Phase Shed 1 Cycles : Cycles spent in phase-shedding power state 1",
50 "BriefDescription": "Phase Shed 2 Cycles",
56 "PublicDescription": "Phase Shed 2 Cycles : Cycles spent in phase-shedding power state 2",
60 "BriefDescription": "Phase Shed 3 Cycles",
66 "PublicDescription": "Phase Shed 3 Cycles : Cycles spent in phase-shedding power state 3",
128 "BriefDescription": "Memory Phase Shedding Cycles",
134 …"PublicDescription": "Memory Phase Shedding Cycles : Counts the number of cycles that the PCU has …
|
| /linux/tools/perf/pmu-events/arch/x86/emeraldrapids/ |
| H A D | uncore-power.json | 30 "BriefDescription": "Phase Shed 0 Cycles",
36 "PublicDescription": "Phase Shed 0 Cycles : Cycles spent in phase-shedding power state 0",
40 "BriefDescription": "Phase Shed 1 Cycles",
46 "PublicDescription": "Phase Shed 1 Cycles : Cycles spent in phase-shedding power state 1",
50 "BriefDescription": "Phase Shed 2 Cycles",
56 "PublicDescription": "Phase Shed 2 Cycles : Cycles spent in phase-shedding power state 2",
60 "BriefDescription": "Phase Shed 3 Cycles",
66 "PublicDescription": "Phase Shed 3 Cycles : Cycles spent in phase-shedding power state 3",
128 "BriefDescription": "Memory Phase Shedding Cycles",
134 …"PublicDescription": "Memory Phase Shedding Cycles : Counts the number of cycles that the PCU has …
|
| /linux/Documentation/devicetree/bindings/watchdog/ |
| H A D | realtek,otto-wdt.yaml | 15 minimum duration of each phase is one tick. Each phase can trigger an
16 interrupt, although the phase 2 interrupt will occur with the system reset.
17 - Phase 1: During this phase, the WDT can be pinged to reset the timeout.
18 - Phase 2: Starts after phase 1 has timed out, and only serves to give the
20 During this phase, pinging the WDT has no effect, and a reset is
|
| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-driver-zynqmp-fpga | 57 Phase 0 = 000
58 Phase 1 = 001
59 Phase 2 = 011
60 Phase 3 = 010
61 Phase 4 = 110
62 Phase 5 = 111
63 Phase 6 = 101
64 Phase 7 = 100
|
| /linux/tools/perf/pmu-events/arch/x86/snowridgex/ |
| H A D | uncore-power.json | 28 "BriefDescription": "Phase Shed 0 Cycles",
34 "PublicDescription": "Phase Shed 0 Cycles : Cycles spent in phase-shedding power state 0",
38 "BriefDescription": "Phase Shed 1 Cycles",
44 "PublicDescription": "Phase Shed 1 Cycles : Cycles spent in phase-shedding power state 1",
48 "BriefDescription": "Phase Shed 2 Cycles",
54 "PublicDescription": "Phase Shed 2 Cycles : Cycles spent in phase-shedding power state 2",
58 "BriefDescription": "Phase Shed 3 Cycles",
64 "PublicDescription": "Phase Shed 3 Cycles : Cycles spent in phase-shedding power state 3",
126 "BriefDescription": "Memory Phase Shedding Cycles",
132 …"PublicDescription": "Memory Phase Shedding Cycles : Counts the number of cycles that the PCU has …
|
| /linux/drivers/staging/iio/Documentation/ |
| H A D | sysfs-bus-iio-dds | 36 Stores phase into Y.
38 allows for pin controlled PSK Phase Shift Keying
40 control the desired phase Y which is added to the phase
48 the desired value in rad. If shared across all phase registers
56 Specifies the active phase Y which is added to the phase
68 phase is controlled by the respective phase and frequency
|
| /linux/tools/perf/pmu-events/arch/x86/icelakex/ |
| H A D | uncore-power.json | 29 "BriefDescription": "Phase Shed 0 Cycles",
35 "PublicDescription": "Phase Shed 0 Cycles : Cycles spent in phase-shedding power state 0",
39 "BriefDescription": "Phase Shed 1 Cycles",
45 "PublicDescription": "Phase Shed 1 Cycles : Cycles spent in phase-shedding power state 1",
49 "BriefDescription": "Phase Shed 2 Cycles",
55 "PublicDescription": "Phase Shed 2 Cycles : Cycles spent in phase-shedding power state 2",
59 "BriefDescription": "Phase Shed 3 Cycles",
65 "PublicDescription": "Phase Shed 3 Cycles : Cycles spent in phase-shedding power state 3",
127 "BriefDescription": "Memory Phase Shedding Cycles",
133 …"PublicDescription": "Memory Phase Shedding Cycles : Counts the number of cycles that the PCU has …
|
| /linux/drivers/mmc/host/ |
| H A D | dw_mmc-rockchip.c | 54 /* Constant signal, no measurable phase shift */ in rockchip_mmc_get_internal_phase()
100 * MMC host to the card, which expects the phase clock inherits in rockchip_mmc_set_internal_phase()
182 struct mmc_clk_phase phase = host->phase_map.phase[ios->timing]; in dw_mci_rk3288_set_ios() local
220 sample_phase = phase.valid ? phase.in_deg : priv->default_sample_phase; in dw_mci_rk3288_set_ios()
222 } else if (phase.valid) { in dw_mci_rk3288_set_ios()
223 rockchip_mmc_set_phase(host, true, phase.in_deg); in dw_mci_rk3288_set_ios()
228 * Set the drive phase offset based on speed mode to achieve hold times. in dw_mci_rk3288_set_ios()
255 * In almost all cases a 90 degree phase offset will provide in dw_mci_rk3288_set_ios()
266 * bus width is 8 we need to double the phase offset in dw_mci_rk3288_set_ios()
286 /* Use out phase from phase map first */ in dw_mci_rk3288_set_ios()
[all …]
|
| /linux/tools/testing/selftests/sched_ext/ |
| H A D | peek_dsq.bpf.c | 117 /* Phase 1: Simple insert-then-peek test (only on first task) */ in BPF_STRUCT_OPS()
119 bpf_printk("peek_dsq_enqueue beginning phase 1 peek test on cpu %d", cpu); in BPF_STRUCT_OPS()
130 /* Still in phase 1, use real DSQ */ in BPF_STRUCT_OPS()
133 /* Phase 2: Random DSQ insertion for stress testing */ in BPF_STRUCT_OPS()
144 /* Phase 1: Complete the simple peek test if we inserted a task but in BPF_STRUCT_OPS()
150 bpf_printk("peek_dsq_dispatch completing phase 1 peek test on cpu %d", cpu); in BPF_STRUCT_OPS()
161 /* Mark phase 1 as complete */ in BPF_STRUCT_OPS()
163 bpf_printk("Phase 1 complete, starting phase 2 stress testing"); in BPF_STRUCT_OPS()
165 /* Still in phase in BPF_STRUCT_OPS()
[all...] |
| /linux/drivers/scsi/pcmcia/ |
| H A D | nsp_cs.c | 231 scsi_pointer->phase = PH_UNDETERMINED; in nsp_queuecommand_lck()
239 SCp.phase : current state of the command */ in nsp_queuecommand_lck()
361 * Start selection phase
371 unsigned char phase, arbit; in nsphw_start_selection() local
375 phase = nsp_index_read(base, SCSIBUSMON); in nsphw_start_selection()
376 if(phase != BUSMON_BUS_FREE) { in nsphw_start_selection()
383 scsi_pointer->phase = PH_ARBSTART; in nsphw_start_selection()
403 scsi_pointer->phase = PH_SELSTART; in nsphw_start_selection()
512 * wait for bus phase change
548 unsigned char phase, i_src; in nsp_expect_signal() local
[all …]
|
| /linux/include/trace/events/ |
| H A D | clk.h | 200 TP_PROTO(struct clk_core *core, int phase),
202 TP_ARGS(core, phase),
206 __field( int, phase )
211 __entry->phase = phase;
214 TP_printk("%s %d", __get_str(name), (int)__entry->phase)
219 TP_PROTO(struct clk_core *core, int phase),
221 TP_ARGS(core, phase)
226 TP_PROTO(struct clk_core *core, int phase),
228 TP_ARGS(core, phase)
[all...] |
| /linux/Documentation/driver-api/ |
| H A D | dpll.rst | 10 PLL - Phase Locked Loop is an electronic circuit which syntonizes clock
14 DPLL - Digital Phase Locked Loop is an integrated circuit which in
15 addition to plain PLL behavior incorporates a digital phase detector
192 Phase offset measurement and adjustment
195 Device may provide ability to measure a phase difference between signals
196 on a pin and its parent dpll device. If pin-dpll phase offset measurement
198 attribute for each parent dpll device. The reported phase offset may be
205 where `curr_avg` is the current reported phase offset, `prev_avg` is the
212 ``DPLL_A_PHASE_OFFSET_AVG_FACTOR`` attr configured value of phase offset
216 Device may also provide ability to adjust a signal phase on a pin.
[all …]
|