| /linux/drivers/iio/common/inv_sensors/ |
| H A D | inv_sensors_timestamp.c | 46 /* save chip parameters and compute min and max clock period */ in inv_sensors_timestamp_init()
51 /* current multiplier and period values after reset */ in inv_sensors_timestamp_init()
53 ts->period = chip->init_period; in inv_sensors_timestamp_init()
55 /* use theoretical value for chip period */ in inv_sensors_timestamp_init()
61 uint32_t period, bool fifo) in inv_sensors_timestamp_update_odr() argument
69 mult = period / ts->chip.clock_period; in inv_sensors_timestamp_update_odr()
81 static bool inv_validate_period(struct inv_sensors_timestamp *ts, uint32_t period) in inv_validate_period() argument
85 /* check that period is acceptable */ in inv_validate_period()
88 if (period > period_min && period < period_max) in inv_validate_period()
95 uint32_t period) in inv_update_chip_period() argument
[all …]
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| /linux/drivers/gpu/drm/tegra/ |
| H A D | mipi-phy.c | 17 unsigned long period) in mipi_dphy_timing_get_default() argument
20 timing->clkpost = 70 + 52 * period; in mipi_dphy_timing_get_default()
30 timing->hsprepare = 65 + 5 * period; in mipi_dphy_timing_get_default()
31 timing->hszero = 145 + 5 * period; in mipi_dphy_timing_get_default()
32 timing->hssettle = 85 + 6 * period; in mipi_dphy_timing_get_default()
39 * T_HS-TRAIL = max(n * 8 * period, 60 + n * 4 * period) in mipi_dphy_timing_get_default()
43 * not parameterize on anything other that period, so this code will in mipi_dphy_timing_get_default()
46 timing->hstrail = max(4 * 8 * period, 60 + 4 * 4 * period); in mipi_dphy_timing_get_default()
63 unsigned long period) in mipi_dphy_timing_validate() argument
68 if (timing->clkpost < (60 + 52 * period)) in mipi_dphy_timing_validate()
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| /linux/drivers/pwm/ |
| H A D | pwm-microchip-core.c | 17 * As setting the period/duty cycle takes 4 register writes, there is a window
18 * in which this races against the start of a new period.
23 * period. Therefore to get a 0% waveform, the output is set the max high/low
25 * If the duty cycle is 0%, and the requested period is less than the
26 * available period resolution, this will manifest as a ~100% waveform (with
28 * - The PWM period is set for the whole IP block not per channel. The driver
29 * will only change the period if no other PWM output is enabled.
59 struct mutex lock; /* protects the shared period */
71 bool enable, u64 period) in mchp_core_pwm_enable() argument
94 * applied to the waveform at the beginning of the next period in mchp_core_pwm_enable()
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| H A D | pwm-visconti.c | 15 * running period is completed. This way the hardware switches atomically
17 * - Disabling the hardware completes the currently running period and keeps
49 u32 period, duty_cycle, pwmc0; in visconti_pwm_apply() local
57 * The biggest period the hardware can provide is in visconti_pwm_apply()
62 if (state->period > (0xffff << 3) * 1000) in visconti_pwm_apply()
63 period = (0xffff << 3) * 1000; in visconti_pwm_apply()
65 period = state->period; in visconti_pwm_apply()
67 if (state->duty_cycle > period) in visconti_pwm_apply()
68 duty_cycle = period; in visconti_pwm_apply()
77 period /= 1000; in visconti_pwm_apply()
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| H A D | pwm-ntxec.c | 16 * - The period and duty cycle can't be changed together in one atomic action.
44 * The time base used in the EC is 8MHz, or 125ns. Period and duty cycle are
57 int period, int duty) in ntxec_pwm_set_raw_period_and_duty_cycle() argument
62 * Changes to the period and duty cycle take effect as soon as the in ntxec_pwm_set_raw_period_and_duty_cycle()
64 * to an inconsistent state after the period is written and before the in ntxec_pwm_set_raw_period_and_duty_cycle()
66 * is longer than the new period, the EC may output 100% for a moment. in ntxec_pwm_set_raw_period_and_duty_cycle()
68 * To minimize the time between the changes to period and duty cycle in ntxec_pwm_set_raw_period_and_duty_cycle()
73 { NTXEC_REG_PERIOD_HIGH, ntxec_reg8(period >> 8) }, in ntxec_pwm_set_raw_period_and_duty_cycle()
75 { NTXEC_REG_PERIOD_LOW, ntxec_reg8(period) }, in ntxec_pwm_set_raw_period_and_duty_cycle()
86 unsigned int period, duty; in ntxec_pwm_apply() local
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| H A D | pwm-intel-lgm.c | 6 * - The hardware supports fixed period & configures only 2-wire mode.
9 * keep track of running period.
11 * and new setting for the first period. From second period, the output is
46 u32 period; member
70 /* The hardware only supports normal polarity and fixed period. */ in lgm_pwm_apply()
71 if (state->polarity != PWM_POLARITY_NORMAL || state->period < pc->period) in lgm_pwm_apply()
77 duty_cycle = min_t(u64, state->duty_cycle, pc->period); in lgm_pwm_apply()
78 val = duty_cycle * LGM_PWM_MAX_DUTY_CYCLE / pc->period; in lgm_pwm_apply()
97 state->period = pc->period; /* fixed period */ in lgm_pwm_get_state()
101 state->duty_cycle = DIV_ROUND_UP(duty * pc->period, LGM_PWM_MAX_DUTY_CYCLE); in lgm_pwm_get_state()
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| H A D | pwm-bcm2835.c | 21 #define PERIOD(x) (((x) * 0x10) + 0x10) macro
71 * period_cycles must be a 32 bit value, so period * rate / NSEC_PER_SEC in bcm2835_pwm_apply()
73 * multiplication period * rate doesn't overflow. in bcm2835_pwm_apply()
74 * To calculate the maximal possible period that guarantees the in bcm2835_pwm_apply()
77 * round(period * rate / NSEC_PER_SEC) <= U32_MAX in bcm2835_pwm_apply()
78 * <=> period * rate / NSEC_PER_SEC < U32_MAX + 0.5 in bcm2835_pwm_apply()
79 * <=> period * rate < (U32_MAX + 0.5) * NSEC_PER_SEC in bcm2835_pwm_apply()
80 * <=> period < ((U32_MAX + 0.5) * NSEC_PER_SEC) / rate in bcm2835_pwm_apply()
81 * <=> period < ((U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC/2) / rate in bcm2835_pwm_apply()
82 * <=> period <= ceil((U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC/2) / rate) - 1 in bcm2835_pwm_apply()
[all …]
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| H A D | pwm-imx-tpm.c | 6 * - The TPM counter and period counter are shared between
7 * multiple channels, so all channels should use same period
10 * next period start.
11 * - Changing period and duty cycle together isn't atomic,
12 * with the wrong timing it might happen that a period is
13 * produced with old duty cycle but new period settings.
97 tmp = (u64)state->period * rate; in pwm_imx_tpm_round_state()
113 /* calculate real period HW can support */ in pwm_imx_tpm_round_state()
116 real_state->period = DIV_ROUND_CLOSEST_ULL(tmp, rate); in pwm_imx_tpm_round_state()
129 p->val = DIV64_U64_ROUND_CLOSEST(tmp, real_state->period); in pwm_imx_tpm_round_state()
[all …]
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| H A D | pwm-fsl-ftm.c | 47 struct fsl_pwm_periodcfg period; member
120 rate = clk_get_rate(fpc->clk[fpc->period.clk_select]); in fsl_pwm_ticks_to_ns()
123 do_div(exval, rate >> fpc->period.clk_ps); in fsl_pwm_ticks_to_ns()
190 unsigned int period = fpc->period.mod_period + 1; in fsl_pwm_calculate_duty() local
191 unsigned int period_ns = fsl_pwm_ticks_to_ns(fpc, period); in fsl_pwm_calculate_duty()
193 duty = (unsigned long long)duty_ns * period; in fsl_pwm_calculate_duty()
234 if (!fsl_pwm_calculate_period(fpc, newstate->period, &periodcfg)) { in fsl_pwm_apply_config()
235 dev_err(pwmchip_parent(chip), "failed to calculate new period\n"); in fsl_pwm_apply_config()
242 * The Freescale FTM controller supports only a single period for in fsl_pwm_apply_config()
243 * all PWM channels, therefore verify if the newly computed period in fsl_pwm_apply_config()
[all …]
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| H A D | pwm-rockchip.c | 41 unsigned long period; member
80 tmp = readl_relaxed(pc->base + pc->data->regs.period); in rockchip_pwm_get_state()
82 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); in rockchip_pwm_get_state()
106 unsigned long period, duty; in rockchip_pwm_config() local
113 * Since period and duty cycle registers have a width of 32 in rockchip_pwm_config()
114 * bits, every possible input period can be obtained using the in rockchip_pwm_config()
117 div = clk_rate * state->period; in rockchip_pwm_config()
118 period = DIV_ROUND_CLOSEST_ULL(div, in rockchip_pwm_config()
125 * Lock the period and duty of previous configuration, then in rockchip_pwm_config()
126 * change the duty and period, that would not be effective. in rockchip_pwm_config()
[all …]
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| H A D | pwm-dwc-core.c | 48 * Calculate width of low and high period in terms of input clock in __dwc_pwm_configure_timer()
57 tmp = DIV_ROUND_CLOSEST_ULL(state->period - state->duty_cycle, in __dwc_pwm_configure_timer()
74 * width of low period and latter the width of high period in terms in __dwc_pwm_configure_timer()
76 * Width = ((Count + 1) * input clock period). in __dwc_pwm_configure_timer()
91 * Enable timer. Output starts from low period. in __dwc_pwm_configure_timer()
124 u64 duty, period; in dwc_pwm_get_state() local
141 period = (ld2 + 1) * dwc->clk_ns; in dwc_pwm_get_state()
142 period += duty; in dwc_pwm_get_state()
145 period = duty * 2; in dwc_pwm_get_state()
149 state->period = period; in dwc_pwm_get_state()
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| H A D | pwm-mtk-disp.c | 73 u32 clk_div, period, high_width, value; in mtk_disp_pwm_apply() local
108 * Find period, high_width and clk_div to suit duty_ns and period_ns. in mtk_disp_pwm_apply()
109 * Calculate proper div value to keep period value in the bound. in mtk_disp_pwm_apply()
111 * period_ns = 10^9 * (clk_div + 1) * (period + 1) / PWM_CLK_RATE in mtk_disp_pwm_apply()
114 * period = (PWM_CLK_RATE * period_ns) / (10^9 * (clk_div + 1)) - 1 in mtk_disp_pwm_apply()
118 clk_div = mul_u64_u64_div_u64(state->period, rate, NSEC_PER_SEC) >> in mtk_disp_pwm_apply()
129 period = mul_u64_u64_div_u64(state->period, rate, div); in mtk_disp_pwm_apply()
130 if (period > 0) in mtk_disp_pwm_apply()
131 period--; in mtk_disp_pwm_apply()
134 value = period | (high_width << PWM_HIGH_WIDTH_SHIFT); in mtk_disp_pwm_apply()
[all …]
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| /linux/Documentation/RCU/Design/Expedited-Grace-Periods/ |
| H A D | Expedited-Grace-Periods.rst | 17 Expedited Grace Period Design
23 grace period.
32 state, the expedited grace period has completed.
43 expedited grace period is shown in the following diagram:
54 Otherwise, the expedited grace period will use
72 block the current expedited grace period until it resumes and finds its
75 the CPU is no longer blocking the grace period.
86 | Why not just have the expedited grace period check the state of all |
116 the handling of a given CPU by an RCU-sched expedited grace period is
137 Expedited Grace Period and CPU Hotplug
[all …]
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| /linux/Documentation/RCU/Design/Memory-Ordering/ |
| H A D | Tree-RCU-Memory-Ordering.rst | 2 A Tour Through TREE_RCU's Grace-Period Memory Ordering
13 grace-period memory ordering guarantee is provided.
15 What Is Tree RCU's Grace Period Memory Ordering Guarantee?
20 Any code that happens after the end of a given RCU grace period is guaranteed
22 period that are within RCU read-side critical sections.
24 period is guaranteed to not see the effects of all accesses following the end
25 of that grace period that are within RCU read-side critical sections.
34 two phases, one of which is executed before the grace period and
35 the other of which is executed after the grace period.
46 Tree RCU Grace Period Memory Ordering Building Blocks
[all …]
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| /linux/lib/ |
| H A D | flex_proportions.c | 3 * Floating proportions with flexible aging period
14 * Where x_{i,j} is j's number of events in i-th last time period and x_i is
15 * total number of events in i-th last time period.
26 * When a new period is declared, we could do:
33 * occurs. This can bit trivially implemented by remembering last period in
42 p->period = 0; in fprop_global_init()
57 * Declare @periods new periods. It is upto the caller to make sure period
79 p->period += periods; in fprop_new_period()
98 pl->period = 0; in fprop_local_init_percpu()
111 unsigned int period = p->period; in fprop_reflect_period_percpu() local
[all …]
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| /linux/Documentation/scheduler/ |
| H A D | sched-bwc.rst | 12 The bandwidth allowed for a group is specified using a quota and period. Within
13 each given "period" (microseconds), a task group is allocated up to "quota"
18 period when the quota is replenished.
21 cfs_quota units at each period boundary. As threads consume this bandwidth it
70 Quota, period and burst are managed within the cpu subsystem via cgroupfs.
77 - cpu.cfs_quota_us: run-time replenished within a period (in microseconds)
78 - cpu.cfs_period_us: the length of a period (in microseconds)
95 period is 1ms. There is also an upper bound on the period length of 1s.
155 a. it fully consumes its own quota within a period
156 b. a parent's quota is fully consumed within its period
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| H A D | sched-rt-group.rst | 27 system when the period is smaller than either the available hrtimer
53 in a given period. We allocate this "run time" for each real-time group which
61 frames a second, which yields a period of 0.04s per frame. Now say it will also
66 This way the graphics group will have a 0.04s period with a 0.032s run time
69 0.00015s. So this group can be scheduled with a period of 0.005s and a run time
90 The scheduling period that is equivalent to 100% CPU bandwidth.
104 * A run time of -1 specifies runtime == period, ie. no limit.
107 runtime/period in /sys/kernel/debug/sched/fair_server/cpuX/
120 period from /proc/sys/kernel/sched_rt_period_us and a run time of 0. If you
156 There is work in progress to make the scheduling period for each group
[all …]
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| /linux/drivers/watchdog/ |
| H A D | booke_wdt.c | 22 * Also, the wdt_period sets the watchdog timer period timeout.
50 /* For the specified period, determine the number of seconds
55 * 2.5 * (2^(63-period+1)) / timebase_freq
57 * In order to simplify things, we assume that period is
60 static unsigned long long period_to_sec(unsigned int period) in period_to_sec() argument
62 unsigned long long tmp = 1ULL << (64 - period); in period_to_sec()
75 * This procedure will find the highest period which will give a timeout
81 unsigned int period; in sec_to_period() local
82 for (period = 63; period > 0; period--) { in sec_to_period()
83 if (period_to_sec(period) >= secs) in sec_to_period()
[all …]
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| /linux/include/linux/ |
| H A D | pwm.h | 19 * period
22 * period
31 * @period: reference period
43 u64 period; member
54 * @period_length_ns: PWM period
56 * @duty_offset_ns: offset of the rising edge from the period's start
61 * PWM_POLARITY_NORMAL) and period - duty_cycle (.polarity =
79 * @period: PWM period (in nanoseconds)
89 u64 period; member
148 return state.period; in pwm_get_period()
[all …]
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| H A D | flex_proportions.h | 3 * Floating proportions with flexible aging period
19 * bound on the number of events per period like
29 /* Number of events in the current period */
31 /* Current period */
32 unsigned int period; member
33 /* Synchronization with period transitions */
47 /* Period in which we last updated events */
48 unsigned int period; member
49 raw_spinlock_t lock; /* Protect period and numerator */
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| /linux/arch/m68k/amiga/ |
| H A D | amisound.c | 31 * The minimum period for audio may be modified by the frame buffer
42 * Current period (set by dmasound.c)
84 unsigned long period = (clock_constant / hz); in amiga_mksound() local
86 if (period < amiga_audio_min_period) in amiga_mksound()
87 period = amiga_audio_min_period; in amiga_mksound()
88 if (period > MAX_PERIOD) in amiga_mksound()
89 period = MAX_PERIOD; in amiga_mksound()
91 /* setup pointer to data, period, length and volume */ in amiga_mksound()
94 custom.aud[2].audper = (unsigned short)period; in amiga_mksound()
116 /* restore period to previous value after beeping */ in nosound()
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| /linux/drivers/media/cec/core/ |
| H A D | cec-pin-priv.h | 42 /* Generate a start bit period that is too short */
44 /* Generate a start bit period that is too long */
54 /* Generate a bit period that is too short */
56 /* Generate a bit period that is too long */
62 /* Generate a bit period that is too short */
64 /* Generate a bit period that is too long */
71 /* Wait for end of bit period after sampling */
73 /* Generate a bit period that is too short */
75 /* Generate a bit period that is too long */
96 /* Wait for earliest end of bit period after sampling */
[all …]
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| /linux/drivers/net/wireless/mediatek/mt76/ |
| H A D | mt76x02_dfs.c | 256 /* reported period */ in mt76x02_dfs_get_hw_pulse()
257 pulse->period = mt76_rr(dev, MT_BBP(DFS, 19)); in mt76x02_dfs_get_hw_pulse()
272 if (!pulse->period || !pulse->w1) in mt76x02_dfs_check_hw_pulse()
287 ret = (pulse->period >= 2900 && in mt76x02_dfs_check_hw_pulse()
288 (pulse->period <= 4700 || in mt76x02_dfs_check_hw_pulse()
289 pulse->period >= 6400) && in mt76x02_dfs_check_hw_pulse()
290 (pulse->period <= 6800 || in mt76x02_dfs_check_hw_pulse()
291 pulse->period >= 10200) && in mt76x02_dfs_check_hw_pulse()
292 pulse->period <= 61600); in mt76x02_dfs_check_hw_pulse()
294 ret = (pulse->period >= 2900 && in mt76x02_dfs_check_hw_pulse()
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| /linux/tools/perf/tests/ |
| H A D | hists_output.c | 54 struct perf_sample sample = { .period = 100, }; in add_hist_entries()
183 !strcmp(SYM(he), "main") && he->stat.period == 200); in test1()
189 !strcmp(SYM(he), "page_fault") && he->stat.period == 100); in test1()
195 !strcmp(SYM(he), "main") && he->stat.period == 100); in test1()
201 !strcmp(SYM(he), "xmalloc") && he->stat.period == 100); in test1()
207 !strcmp(SYM(he), "page_fault") && he->stat.period == 100); in test1()
213 !strcmp(SYM(he), "schedule") && he->stat.period == 100); in test1()
219 !strcmp(SYM(he), "free") && he->stat.period == 100); in test1()
225 !strcmp(SYM(he), "malloc") && he->stat.period == 100); in test1()
231 !strcmp(SYM(he), "cmd_record") && he->stat.period in test1()
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| /linux/Documentation/devicetree/bindings/input/ |
| H A D | rotary-encoder.yaml | 49 rotary-encoder,steps-per-period:
54 Number of steps (stable states) per period.
56 1: Full-period mode (default)
57 2: Half-period mode
58 4: Quarter-period mode
67 rotary-encoder,half-period:
71 Makes the driver work on half-period mode.
72 This property is deprecated. Instead, a 'steps-per-period ' value should
73 be used, such as "rotary-encoder,steps-per-period = <2>".
|