Lines Matching full:period
41 unsigned long period; member
80 tmp = readl_relaxed(pc->base + pc->data->regs.period); in rockchip_pwm_get_state()
82 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); in rockchip_pwm_get_state()
106 unsigned long period, duty; in rockchip_pwm_config() local
113 * Since period and duty cycle registers have a width of 32 in rockchip_pwm_config()
114 * bits, every possible input period can be obtained using the in rockchip_pwm_config()
117 div = clk_rate * state->period; in rockchip_pwm_config()
118 period = DIV_ROUND_CLOSEST_ULL(div, in rockchip_pwm_config()
125 * Lock the period and duty of previous configuration, then in rockchip_pwm_config()
126 * change the duty and period, that would not be effective. in rockchip_pwm_config()
134 writel(period, pc->base + pc->data->regs.period); in rockchip_pwm_config()
147 * the configuration of duty, period and polarity in rockchip_pwm_config()
148 * would be effective together at next period. in rockchip_pwm_config()
235 .period = 0x08,
248 .period = 0x04,
262 .period = 0x04,
276 .period = 0x04,