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/freebsd/lib/libpmc/pmu-events/arch/x86/broadwellde/
H A D	frontend.json	12 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 17 …Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed th… 32 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", 52 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 58 … uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.… 63 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 69 … uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.… 80 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", 91 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", 96 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/broadwell/
H A D	frontend.json	12 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 17 …Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed th… 32 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", 52 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 58 … uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.… 63 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 69 … uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.… 80 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", 91 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", 96 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/broadwellx/
H A D	frontend.json	12 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 17 …Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed th… 32 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", 52 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 58 … uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.… 63 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 69 … uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.… 80 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", 91 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", 96 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", [all …]
/freebsd/sys/contrib/openzfs/module/zfs/
H A D	dmu_zfetch.c	1 // SPDX-License-Identifier: CDDL-1.0 10 * or https://opensource.org/licenses/CDDL-1.0. 50 /* max # of streams per zfetch / 52 / min time before stream reclaim / 54 / max time before stream delete / 57 / min bytes to prefetch per stream (default 2MB) / 59 / max bytes to prefetch per stream (default 8MB) / 62 / min bytes to prefetch per stream (default 4MB) / 64 / max bytes to prefetch per stream (default 64MB) / 67 / max bytes to prefetch indirects for per stream (default 128MB) */ [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/haswell/
H A D	frontend.json	8 "PublicDescription": "Number of front end re-steers due to BPU misprediction.", 13 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 31 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", 40 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", 59 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 70 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 103 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.… 113 …tion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", 170 … event counts cycles during which the microcode sequencer assisted the Front-end in delivering uop… 175 …"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered … [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/haswellx/
H A D	frontend.json	8 "PublicDescription": "Number of front end re-steers due to BPU misprediction.", 13 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 31 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", 40 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", 59 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 70 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 103 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.… 113 …tion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", 170 … event counts cycles during which the microcode sequencer assisted the Front-end in delivering uop… 175 …"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered … [all …]
/freebsd/share/man/man4/
H A D	sctp.4	32 .Nd Internet Stream Control Transmission Protocol 47 protocol provides reliable, flow-controlled, two-way 57 Internet address format and, in addition, provides a per-host 105 third leg of the four-way handshake. 116 protocol directly supports multi-homing. 129 transport protocol is also multi-streamed. 130 Multi-streaming refers to the ability to send sub-ordered flows of 132 A user performs this by specifying a specific stream in one of the 137 of data i.e., a message loss in stream 1 will not block the delivery 138 of messages sent in stream 2. [all …]
/freebsd/usr.bin/clang/llvm-pdbutil/
H A D	llvm-pdbutil.1	`4 .nr rst2man-indent-level 0 7 \\$1 \\n[an-margin] 8 level \\n[rst2man-indent-level] 9 level margin: \\n[rst2man-indent\\n[rst2man-indent-level]] 10 - 11 \\n[rst2man-indent0] 12 \\n[rst2man-indent1] 13 \\n[rst2man-indent2] 18 . nr rst2man-indent\\n[rst2man-indent-level] \\n[an-margin] 19 . nr rst2man-indent-level +1 [all …]`
/freebsd/lib/libpmc/pmu-events/arch/x86/jaketown/
H A D	frontend.json	12 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.", 21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 26 …Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline. It excludes… 31 …"BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exce… 40 …"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stre… 77 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.", 87 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.", 117 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.… 127 …tion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.… 179 …-end in delivering uops. Microcode assists are used for complex instructions or scenarios that ca… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/sandybridge/
H A D	frontend.json	12 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.", 21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 26 …Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline. It excludes… 31 …"BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exce… 40 …"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stre… 77 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.", 87 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.", 117 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.… 127 …tion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.… 179 …-end in delivering uops. Microcode assists are used for complex instructions or scenarios that ca… [all …]
/freebsd/usr.sbin/inetd/
H A D	inetd.8	`34 .Dq super-server 70 .Bl -tag -width indent 92 a TCP-based service would need two entries, 106 May be overridden on a per-service basis with the 107 "max-connections-per-ip-per-minute" parameter. 112 May be overridden on a per-service basis with the "max-child" 128 May be overridden on a per-service basis with the "max-child-per-ip" 156 .Bd -unfilled -offset indent -compact 157 service-name 158 socket-type [all …]`
/freebsd/sys/contrib/device-tree/Bindings/media/
H A D	cdns,csi2rx.txt	1 Cadence MIPI-CSI2 RX controller 4 The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI 8 - compatible: must be set to "cdns,csi2rx" and an SoC-specific compatible 9 - reg: base address and size of the memory mapped region 10 - clocks: phandles to the clocks driving the controller 11 - clock-names: must contain: 14 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream 18 - phys: phandle to the external D-PHY, phy-names must be provided 19 - phy-names: must contain "dphy", if the implementation uses an 20 external D-PHY [all …]
H A D	cdns,csi2tx.txt	1 Cadence MIPI-CSI2 TX controller 4 The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to 8 - compatible: must be set to "cdns,csi2tx" or "cdns,csi2tx-1.3" 9 for version 1.3 of the controller, "cdns,csi2tx-2.1" for v2.1 10 - reg: base address and size of the memory mapped region 11 - clocks: phandles to the clocks driving the controller 12 - clock-names: must contain: 15 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream 19 - phys: phandle to the D-PHY. If it is set, phy-names need to be set 20 - phy-names: must contain "dphy" [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/skylake/
H A D	frontend.json	8 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch… 13 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 18 …ber of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Dec… 23 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 28 …Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed th… 41 …unts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-… 55 …d a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means st… 101 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", 109 …er an interval where the front-end delivered no uops for a period of at least 1 cycle which was no… 115 …after an interval where the front-end delivered no uops for a period of 128 cycles which was not i… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/cascadelakex/
H A D	frontend.json	8 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch… 13 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 18 …ber of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Dec… 23 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 28 …Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed th… 41 …unts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-… 55 …d a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means st… 101 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", 109 …er an interval where the front-end delivered no uops for a period of at least 1 cycle which was no… 115 …after an interval where the front-end delivered no uops for a period of 128 cycles which was not i… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/skylakex/
H A D	frontend.json	8 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch… 13 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 18 …ber of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Dec… 23 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 28 …Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed th… 41 …unts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-… 55 …d a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means st… 101 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", 109 …er an interval where the front-end delivered no uops for a period of at least 1 cycle which was no… 115 …after an interval where the front-end delivered no uops for a period of 128 cycles which was not i… [all …]
/freebsd/lib/libc/nls/
H A D	ca_ES.ISO8859-1.msg	2 $ Message catalog for ca_ES.ISO8859-1 locale 56 25 L'ioctl no �s adecuat per al dispositiu 88 41 Tipus de protocol incorrecte per al socket 100 47 Fam�lia d'adreces no suportada per la fam�lia de protocols 116 55 No hi ha prou espai per a la memoria interm�dia (buffer) 158 76 Procediment erroni per al programa 174 84 Valor massa gran per a �sser emmagatzemat en el tipus de dades 186 90 No hi ha recursos de tipus STREAM 188 91 No �s un STREAM 190 92 Temps d'espera esgotat en el ioctl STREAM [all …]
/freebsd/sys/contrib/dev/iwlwifi/fw/api/
H A D	rs.h	`1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause / 3 Copyright (C) 2012-2014, 2018-2022, 2024 Intel Corporation 12 * enum iwl_tlc_mng_cfg_flags - options for TLC config flags 20 * stream 36 * enum iwl_tlc_mng_cfg_cw - channe [all...]`
/freebsd/lib/libpmc/pmu-events/arch/x86/ivybridge/
H A D	frontend.json	8 "PublicDescription": "Number of front end re-steers due to BPU misprediction.", 13 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 23 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles", 33 …"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stre… 53 …"BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB… 58 …"PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTL… 73 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 84 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 117 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", 123 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/ivytown/
H A D	frontend.json	8 "PublicDescription": "Number of front end re-steers due to BPU misprediction.", 13 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 23 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles", 33 …"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stre… 53 …"BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB… 58 …"PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTL… 73 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 84 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 117 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", 123 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.… [all …]
/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a65/
H A D	cache.json	111 … prefetch. Counts any linefills from the prefetcher which cause an allocation into the L1 D-cache", 114 …o prefetch. Counts any linefills from the prefetcher which cause an allocation into the L1 D-cache" 117 …per-core L2 cache: This event does not count. +//0 If the core is configured without a per-core L2… 120 …per-core L2 cache: This event does not count. +//0 If the core is configured without a per-core L2… 123 …less of whether they allocate. If either the core is configured without a per-core L2 or the clust… 126 …less of whether they allocate. If either the core is configured without a per-core L2 or the clust… 129 "PublicDescription": "L1D entering write stream mode", 132 "BriefDescription": "L1D entering write stream mode" 135 "PublicDescription": "L1D is in write stream mode", 138 "BriefDescription": "L1D is in write stream mode" [all …]
/freebsd/sys/contrib/openzfs/man/man8/
H A D	zfs-send.8	`1 .\" SPDX-License-Identifier: CDDL-1.0 10 .\" or https://opensource.org/licenses/CDDL-1.0. 39 .Nm zfs-send 40 .Nd generate backup stream of ZFS dataset 55 .Fl -redact Ar redaction_bookmark 74 .Bl -tag -width "" 83 Creates a stream representation of the second 90 By default, a full stream is generated. 91 .Bl -tag -width "-D" 92 .It Fl D , -dedup [all …]`
H A D	zfs-redact.8	`1 .\" SPDX-License-Identifier: CDDL-1.0 10 .\" or https://opensource.org/licenses/CDDL-1.0. 35 .Dt ZFS-SEND 8 39 .Nm zfs-send 40 .Nd generate backup stream of ZFS dataset 55 .Fl -redact Ar redaction_bookmark 74 .Bl -tag -widt [all...]`
/freebsd/sys/contrib/device-tree/Bindings/dma/xilinx/
H A D	xilinx_dma.txt	`6 Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream 11 Xilinx AXI CDMA engine, it does transfers between memory-mapped source 12 address and a memory-mapped destination address. 14 Xilinx AXI MCDMA engine, it does transfer between memory and AXI4 stream 19 - compatible: Should be one of- 20 "xlnx,axi-vdma-1.00.a" 21 "xlnx,axi-dma-1.0 [all...]`
/freebsd/contrib/llvm-project/llvm/tools/llvm-mca/Views/
H A D	ResourcePressureView.h	`1 //===---------- [all...]`

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