per\-cpu\-cluster (full) in projects: linux

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Searched +full:per +full:- +full:cpu +full:- +full:cluster (Results 1 – 25 of 113) sorted by relevance

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/linux/Documentation/devicetree/bindings/cpufreq/
H A D	apple,cluster-cpufreq.yaml	1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/cpufreq/apple,cluster-cpufreq.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Apple SoC cluster cpufreq device 10 - Hector Martin <marcan@marcan.st> 13 Apple SoCs (e.g. M1) have a per-cpu-cluster DVFS controller that is part of 14 the cluster management register block. This binding uses the standard 15 operating-points-v2 table to define the CPU performance states, with the 16 opp-level property specifying the hardware p-state index for that level. [all …]
/linux/drivers/clk/mvebu/
H A D	ap-cpu-clk.c	`1 // SPDX-License-Identifier: GPL-2.0+ 3 * Marvell Armada AP CPU Clock Controller 11 #define pr_fmt(fmt) "ap-cpu-clk: " fmt 13 #include <linux/clk-provider.h> 33 * struct cpu_dfs_regs: CPU DFS register mapping 34 * @divider_reg: full integer ratio from PLL frequency to CPU clock frequency 53 /* AP806 CPU DFS register mapping/ 91 / AP807 CPU DFS register mapping / 127 struct ap806_clk: CPU cluster clock controller instance 128 * @cluster: Cluster clock controller index [all …]`
/linux/arch/x86/kernel/apic/
H A D	x2apic_cluster.c	1 // SPDX-License-Identifier: GPL-2.0 17 * Using per cpu variable would cost one cache line per cpu. 29 static void x2apic_send_IPI(int cpu, int vector) in x2apic_send_IPI() argument 31 u32 dest = x86_cpu_to_logical_apicid[cpu]; in x2apic_send_IPI() 41 unsigned int cpu, clustercpu; in __x2apic_send_IPI_mask() local 52 /* If IPI should not be sent to self, clear current CPU / in __x2apic_send_IPI_mask() 56 / Collapse cpus in a cluster so a single IPI per cluster is sent / in __x2apic_send_IPI_mask() 57 for_each_cpu(cpu, tmpmsk) { in __x2apic_send_IPI_mask() 58 struct cpumask cmsk = per_cpu(cluster_masks, cpu); in __x2apic_send_IPI_mask() 68 /* Remove cluster CPUs from tmpmask */ in __x2apic_send_IPI_mask() [all …]
/linux/Documentation/devicetree/bindings/cpu/
H A D	cpu-topology.txt	`2 CPU topology binding description 6 1 - Introduction 12 - socket 13 - cluster 14 - core 15 - thread 18 symmetric multi-threading (SMT) is supported or not. 20 For instance in a system where CPUs support SMT, "cpu" nodes represent all 22 In systems where SMT is not supported "cpu" nodes represent all cores present 25 CPU topology bindings allow one to associate cpu nodes with hierarchical groups [all …]`
/linux/Documentation/admin-guide/pm/
H A D	intel_uncore_frequency_scaling.rst	1 .. SPDX-License-Identifier: GPL-2.0 8 :Copyright: \|copy\| 2022-2023 Intel Corporation 13 ------------ 22 the scaling min/max frequencies via cpufreq sysfs to improve CPU performance. 30 --------------- 33 `/sys/devices/system/cpu/intel_uncore_frequency/`. 36 uncore scaling control is per die in multiple die/package SoCs or per 37 package for single die per package SoCs. The name represents the 45 This is a read-only attribute. If users adjust max_freq_khz, 50 This is a read-only attribute. If users adjust min_freq_khz, [all …]
/linux/arch/arm/mach-versatile/
H A D	spc.c	`1 // SPDX-License-Identifier: GPL-2.0-only 12 #include <linux/clk-provider.h> 14 #include <linux/cpu.h> 28 #define SPCLOG "vexpress-spc: " 39 /* SPC wake-up IRQs status and mask / 46 / SPC per-CPU mailboxes / 50 / SPC CPU/cluster reset statue / 52 #define STANDBYWFI_STAT_A15_CPU_MASK(cpu) (1 << (cpu)) argument 53 #define STANDBYWFI_STAT_A7_CPU_MASK(cpu) (1 << (3 + (cpu))) argument 68 / wake-up interrupt masks */ [all …]`
/linux/arch/mips/kernel/
H A D	cacheinfo.c	`1 // SPDX-License-Identifier: GPL-2.0-only 10 leaf->type = c_type; \ 11 leaf->level = c_level; \ 12 leaf->coherency_line_size = c->cache.linesz; \ 13 leaf->number_of_sets = c->cache.sets; \ 14 leaf->ways_of_associativity = c->cache.ways; \ 15 leaf->size = c->cache.linesz * c->cache.sets * \ 16 c->cache.ways; \ 20 int init_cache_level(unsigned int cpu) in init_cache_level() argument 23 struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); in init_cache_level() [all …]`
/linux/tools/perf/tests/shell/
H A D	stat+json_output.sh	`3 # SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause) 7 set -e 19 rm -f "${stat_output}" 21 trap - EXIT TERM INT 33 [ "$(id -u)" != 0 ] && [ "$(cat /proc/sys/kernel/perf_event_paranoid)" -g [all...]`
/linux/tools/perf/Documentation/
H A D	perf-stat.txt	`1 perf-stat(1) 5 ---- 6 perf-stat - Run a command and gather performance counter statistics 9 -------- 11 'perf stat' [-e <EVENT> \| --event=EVENT] [-a] <command> 12 'perf stat' [-e <EVENT> \| --event=EVENT] [-a] \-- <command> [<options>] 13 'perf stat' [-e <EVENT> \| --event=EVENT] [-a] record [-o file] \-- <command> [<options>] 14 'perf stat' report [-i file] 17 ----------- 23 ------- [all …]`
/linux/Documentation/devicetree/bindings/arm/marvell/
H A D	ap80x-system-controller.txt	`6 registers giving access to numerous features: clocks, pin-muxing and 11 - compatible: must be: "syscon", "simple-mfd"; 12 - reg: register area of the AP80x system controller 18 ------- 24 - 0: reference clock of CPU cluster 0 25 - 1: reference clock of CPU cluster 1 26 - 2: fixed PLL at 1200 Mhz 27 - 3: MSS clock, derived from the fixed PLL 31 - compatible: must be one of: 32 * "marvell,ap806-clock" [all …]`
/linux/arch/arm/include/asm/
H A D	mcpm.h	1 /* SPDX-License-Identifier: GPL-2.0-only / 6 Copyright: (C) 2012-2013 Linaro Limited 13 * Maximum number of possible clusters / CPUs per cluster. 39 * This is used to indicate where the given CPU from given cluster should 40 * branch once it is ready to re-enter the kernel using ptr, or NULL if it 41 * should be gated. A gated CPU is held in a WFE loop until its vector 44 void mcpm_set_entry_vector(unsigned cpu, unsigned cluster, void ptr); 48 from very early assembly code before the CPU is ungated. The 51 void mcpm_set_early_poke(unsigned cpu, unsigned cluster, 55 * CPU/cluster power operations API for higher subsystems to use. [all …]
/linux/tools/perf/tests/shell/lib/
H A D	stat_output.sh	`2 # SPDX-License-Identifier: GPL-2.0 7 [ "$(id -u)" != 0 ] && [ "$(cat /proc/sys/kernel/perf_event_paranoid)" -gt $1 ] 13 echo -n "Checking $1 output: no args " 15 commachecker --no-args 21 echo - [all...]`
/linux/include/linux/
H A D	swap.h	1 /* SPDX-License-Identifier: GPL-2.0 / 15 #include <linux/page-flags.h> 29 #define SWAP_FLAG_DISCARD_ONCE 0x20000 / discard swap area at swapon-time / 30 #define SWAP_FLAG_DISCARD_PAGES 0x40000 / discard page-clusters after use / 39 return current->flags & PF_KSWAPD; in current_is_kswapd() 47 on 32-bit-pgoff_t architectures. And that assumes that the architecture packs 70 * device memory that is unaddressable (inaccessible) by CPU, so that we can 73 * When a page is migrated from CPU to device, we set the CPU page table entry 76 * When a page is mapped by the device for exclusive access we set the CPU page 118 ((1 << MAX_SWAPFILES_SHIFT) - SWP_DEVICE_NUM - \ [all …]
H A D	cpu_pm.h	1 /* SPDX-License-Identifier: GPL-2.0-only / 16 When a CPU goes to a low power state that turns off power to the CPU's 25 * The notifications are split into two classes: CPU notifications and CPU 26 * cluster notifications. 28 * CPU notifications apply to a single CPU and must be called on the affected 29 * CPU. They are used to save per-cpu context for affected blocks. 31 * CPU cluster notifications apply to all CPUs in a single power domain. They 41 /* A single cpu is entering a low power state / 44 / A single cpu failed to enter a low power state / 47 / A single cpu is exiting a low power state */ [all …]
/linux/Documentation/ABI/stable/
H A D	sysfs-devices-system-cpu	`1 What: /sys/devices/system/cpu/dscr_default 2 Date: 13-May-2014 6 /sys/devices/system/cpu/cpuN/dscr on all CPUs. 9 all per-CPU defaults at the same time. 12 What: /sys/devices/system/cpu/cpu[0-9]+/dscr 13 Date: 13-May-2014 17 a CPU. 22 on any CPU where it executes (overriding the value described 27 What: /sys/devices/system/cpu/cpuX/topology/physical_package_id 33 What: /sys/devices/system/cpu/cpuX/topology/die_id [all …]`
/linux/arch/x86/kvm/svm/
H A D	avic.c	1 // SPDX-License-Identifier: GPL-2.0-only 3 * Kernel-based Virtual Machine driver for Linux 19 #include <linux/amd-iommu.h> 60 static_assert(__AVIC_GATAG(AVIC_VM_ID_MASK, AVIC_VCPU_ID_MASK) == -1u); 81 struct list_head node; /* Used by SVM for per-vcpu ir_list / 87 struct vmcb vmcb = svm->vmcb01.ptr; in avic_activate_vmcb() 89 vmcb->control.int_ctl &= ~(AVIC_ENABLE_MASK \| X2APIC_MODE_MASK); in avic_activate_vmcb() 90 vmcb->control.avic_physical_id &= ~AVIC_PHYSICAL_MAX_INDEX_MASK; in avic_activate_vmcb() 92 vmcb->control.int_ctl \|= AVIC_ENABLE_MASK; in avic_activate_vmcb() 95 * Note: KVM supports hybrid-AVIC mode, where KVM emulates x2APIC MSR in avic_activate_vmcb() [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/
H A D	l1d_cache.json	4 …ns that missed in the level 1 data cache. This event only counts one event per cache line. This ev… 8 …fied memory structures, for example refill buffers, write buffers, and write-back buffers, are als… 12 …-backs of dirty data from the L1 data cache to the L2 cache. This occurs when either a dirty cache… 28 … read operation misses in the level 1 data cache. This event only counts one event per cache line." 32 …write operation misses in the level 1 data cache. This event only counts one event per cache line." 36 …cache refills where the cache line data came from caches inside the immediate cluster of the core." 40 …he refills for which the cache line data came from outside the immediate cluster of the core, like… 48 …cDescription": "Counts write-backs from the level 1 data cache that are a result of a coherency op… 52 …- Cache Maintenance Operations (CMO) that operate by a virtual address.\n- Broadcast cache coheren…
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/
H A D	l1d_cache.json	4 …ns that missed in the level 1 data cache. This event only counts one event per cache line. This ev… 8 …fied memory structures, for example refill buffers, write buffers, and write-back buffers, are als… 12 …-backs of dirty data from the L1 data cache to the L2 cache. This occurs when either a dirty cache… 24 … read operation misses in the level 1 data cache. This event only counts one event per cache line." 28 …write operation misses in the level 1 data cache. This event only counts one event per cache line." 32 …cache refills where the cache line data came from caches inside the immediate cluster of the core." 36 …he refills for which the cache line data came from outside the immediate cluster of the core, like… 44 …cDescription": "Counts write-backs from the level 1 data cache that are a result of a coherency op… 48 …- Cache Maintenance Operations (CMO) that operate by a virtual address.\n- Broadcast cache coheren…
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/
H A D	l1d_cache.json	4 …ns that missed in the level 1 data cache. This event only counts one event per cache line. This ev… 8 …fied memory structures, for example refill buffers, write buffers, and write-back buffers, are als… 12 …-backs of dirty data from the L1 data cache to the L2 cache. This occurs when either a dirty cache… 28 … read operation misses in the level 1 data cache. This event only counts one event per cache line." 32 …write operation misses in the level 1 data cache. This event only counts one event per cache line." 36 …cache refills where the cache line data came from caches inside the immediate cluster of the core." 40 …he refills for which the cache line data came from outside the immediate cluster of the core, like… 48 …cDescription": "Counts write-backs from the level 1 data cache that are a result of a coherency op… 52 …- Cache Maintenance Operations (CMO) that operate by a virtual address.\n- Broadcast cache coheren…
/linux/Documentation/admin-guide/perf/
H A D	qcom_l2_pmu.rst	2 Qualcomm Technologies Level-2 Cache Performance Monitoring Unit (PMU) 7 own PMU. Each cluster has one or more CPUs associated with it. 17 Events can be envisioned as a 2-dimensional array. Each column represents 23 the code (array row) and G specifies the group (column) 0-7. 29 consisting of one CPU per cluster which will be used to handle all the PMU 30 events on that cluster. 34 perf stat -e l2cache_0/config=0x001/,l2cache_0/config=0x042/ -a sleep 1 36 perf stat -e l2cache_0/config=0xfe/ -C 2 sleep 1 39 not work. Per-task perf sessions are not supported.
/linux/tools/perf/pmu-events/arch/x86/sierraforest/
H A D	srf-metrics.json	3 "BriefDescription": "C1 residency percent per core", 4 "MetricExpr": "cstate_core@c1\\-residency@ / TSC", 10 "BriefDescription": "C6 residency percent per core", 11 "MetricExpr": "cstate_core@c6\\-residency@ / TSC", 17 "BriefDescription": "C6 residency percent per module", 18 "MetricExpr": "cstate_module@c6\\-residency@ / TSC", 24 "BriefDescription": "C6 residency percent per package", 25 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", 31 …"BriefDescription": "Cycles per instruction retired; indicating how much time each executed instru… 37 "BriefDescription": "CPU operating frequency (in GHz)", [all …]
/linux/tools/perf/pmu-events/arch/x86/grandridge/
H A D	grr-metrics.json	3 "BriefDescription": "C1 residency percent per core", 4 "MetricExpr": "cstate_core@c1\\-residency@ / TSC", 10 "BriefDescription": "C6 residency percent per core", 11 "MetricExpr": "cstate_core@c6\\-residency@ / TSC", 17 "BriefDescription": "C6 residency percent per module", 18 "MetricExpr": "cstate_module@c6\\-residency@ / TSC", 24 "BriefDescription": "C6 residency percent per package", 25 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", 31 …"BriefDescription": "Cycles per instruction retired; indicating how much time each executed instru… 37 "BriefDescription": "CPU operating frequency (in GHz)", [all …]
/linux/Documentation/devicetree/bindings/remoteproc/
H A D	ti,k3-r5f-rproc.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Suman Anna <s-anna@ti.com> 13 The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F 14 processor subsystems/clusters (R5FSS). The dual core cluster can be used 20 AM64x SoCs do not support LockStep mode, but rather a new non-safety mode 21 called "Single-CPU" mode, where only Core0 is used, but with ability to use 27 Each Dual-Core R5F sub-system is represented as a single DTS node [all …]
/linux/Documentation/devicetree/bindings/arm/
H A D	arm,cci-400.yaml	`1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/arm/arm,cci-400.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> 13 ARM multi-cluster systems maintain intra-cluster coherency through a cache 19 space and multiple sets of interface control registers, one per slave 24 pattern: "^cci(@[0-9a-f]+)?$" 28 - arm,cci-400 29 - arm,cci-500 [all …]`
/linux/tools/perf/
H A D	builtin-stat.c	1 // SPDX-License-Identifier: GPL-2.0-only 3 * builtin-stat.c 6 * overview about any workload, CPU or specific PID. 16 1708.761321 task-clock # 11.037 CPUs utilized 17 41,190 context-switches # 0.024 M/sec 18 6,735 CPU-migration 170 bool node, socket, die, cluster, cache, core, thread, no_aggr; global() member 282 struct perf_cpu cpu = perf_cpu_map__cpu(evsel__cpus(counter), cpu_map_idx); evsel__write_stat_event() local 1172 cpu__get_cache_id_from_map(struct perf_cpu cpu,char * map) cpu__get_cache_id_from_map() argument 1199 cpu__get_cache_details(struct perf_cpu cpu,struct perf_cache * cache) cpu__get_cache_details() argument 1270 aggr_cpu_id__cache(struct perf_cpu cpu,void * data) aggr_cpu_id__cache() argument 1303 perf_stat__get_socket(struct perf_stat_config * config __maybe_unused,struct perf_cpu cpu) perf_stat__get_socket() argument 1309 perf_stat__get_die(struct perf_stat_config * config __maybe_unused,struct perf_cpu cpu) perf_stat__get_die() argument 1315 perf_stat__get_cache_id(struct perf_stat_config * config __maybe_unused,struct perf_cpu cpu) perf_stat__get_cache_id() argument 1321 perf_stat__get_cluster(struct perf_stat_config * config __maybe_unused,struct perf_cpu cpu) perf_stat__get_cluster() argument 1327 perf_stat__get_core(struct perf_stat_config * config __maybe_unused,struct perf_cpu cpu) perf_stat__get_core() argument 1333 perf_stat__get_node(struct perf_stat_config * config __maybe_unused,struct perf_cpu cpu) perf_stat__get_node() argument 1339 perf_stat__get_global(struct perf_stat_config * config __maybe_unused,struct perf_cpu cpu) perf_stat__get_global() argument 1345 perf_stat__get_cpu(struct perf_stat_config * config __maybe_unused,struct perf_cpu cpu) perf_stat__get_cpu() argument 1351 perf_stat__get_aggr(struct perf_stat_config * config,aggr_get_id_t get_id,struct perf_cpu cpu) perf_stat__get_aggr() argument 1367 perf_stat__get_socket_cached(struct perf_stat_config * config,struct perf_cpu cpu) perf_stat__get_socket_cached() argument 1373 perf_stat__get_die_cached(struct perf_stat_config * config,struct perf_cpu cpu) perf_stat__get_die_cached() argument 1379 perf_stat__get_cluster_cached(struct perf_stat_config * config,struct perf_cpu cpu) perf_stat__get_cluster_cached() argument 1385 perf_stat__get_cache_id_cached(struct perf_stat_config * config,struct perf_cpu cpu) perf_stat__get_cache_id_cached() argument 1391 perf_stat__get_core_cached(struct perf_stat_config * config,struct perf_cpu cpu) perf_stat__get_core_cached() argument 1397 perf_stat__get_node_cached(struct perf_stat_config * config,struct perf_cpu cpu) perf_stat__get_node_cached() argument 1403 perf_stat__get_global_cached(struct perf_stat_config * config,struct perf_cpu cpu) perf_stat__get_global_cached() argument 1409 perf_stat__get_cpu_cached(struct perf_stat_config * config,struct perf_cpu cpu) perf_stat__get_cpu_cached() argument 1525 perf_env__get_socket_aggr_by_cpu(struct perf_cpu cpu,void * data) perf_env__get_socket_aggr_by_cpu() argument 1536 perf_env__get_die_aggr_by_cpu(struct perf_cpu cpu,void * data) perf_env__get_die_aggr_by_cpu() argument 1554 perf_env__get_cache_id_for_cpu(struct perf_cpu cpu,struct perf_env * env,u32 cache_level,struct aggr_cpu_id * id) perf_env__get_cache_id_for_cpu() argument 1591 perf_env__get_cache_aggr_by_cpu(struct perf_cpu cpu,void * data) perf_env__get_cache_aggr_by_cpu() argument 1608 perf_env__get_cluster_aggr_by_cpu(struct perf_cpu cpu,void * data) perf_env__get_cluster_aggr_by_cpu() argument 1623 perf_env__get_core_aggr_by_cpu(struct perf_cpu cpu,void * data) perf_env__get_core_aggr_by_cpu() argument 1642 perf_env__get_cpu_aggr_by_cpu(struct perf_cpu cpu,void * data) perf_env__get_cpu_aggr_by_cpu() argument 1662 perf_env__get_node_aggr_by_cpu(struct perf_cpu cpu,void * data) perf_env__get_node_aggr_by_cpu() argument 1681 perf_stat__get_socket_file(struct perf_stat_config * config __maybe_unused,struct perf_cpu cpu) perf_stat__get_socket_file() argument 1686 perf_stat__get_die_file(struct perf_stat_config * config __maybe_unused,struct perf_cpu cpu) perf_stat__get_die_file() argument 1692 perf_stat__get_cluster_file(struct perf_stat_config * config __maybe_unused,struct perf_cpu cpu) perf_stat__get_cluster_file() argument 1698 perf_stat__get_cache_file(struct perf_stat_config * config __maybe_unused,struct perf_cpu cpu) perf_stat__get_cache_file() argument 1704 perf_stat__get_core_file(struct perf_stat_config * config __maybe_unused,struct perf_cpu cpu) perf_stat__get_core_file() argument 1710 perf_stat__get_cpu_file(struct perf_stat_config * config __maybe_unused,struct perf_cpu cpu) perf_stat__get_cpu_file() argument 1716 perf_stat__get_node_file(struct perf_stat_config * config __maybe_unused,struct perf_cpu cpu) perf_stat__get_node_file() argument 1722 perf_stat__get_global_file(struct perf_stat_config * config __maybe_unused,struct perf_cpu cpu) perf_stat__get_global_file() argument [all...]

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