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/linux/drivers/clk/mvebu/
H A Dap-cpu-clk.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Marvell Armada AP CPU Clock Controller
11 #define pr_fmt(fmt) "ap-cpu-clk: " fmt
13 #include <linux/clk-provider.h>
33 * struct cpu_dfs_regs: CPU DFS register mapping
34 * @divider_reg: full integer ratio from PLL frequency to CPU clock frequency
53 /* AP806 CPU DFS register mapping*/
91 /* AP807 CPU DFS register mapping */
127 * struct ap806_clk: CPU cluster clock controller instance
128 * @cluster: Cluster clock controller index
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/linux/arch/x86/kernel/apic/
H A Dx2apic_cluster.c1 // SPDX-License-Identifier: GPL-2.0
17 * Using per cpu variable would cost one cache line per cpu.
29 static void x2apic_send_IPI(int cpu, int vector) in x2apic_send_IPI() argument
31 u32 dest = x86_cpu_to_logical_apicid[cpu]; in x2apic_send_IPI()
41 unsigned int cpu, clustercpu; in __x2apic_send_IPI_mask() local
52 /* If IPI should not be sent to self, clear current CPU */ in __x2apic_send_IPI_mask()
56 /* Collapse cpus in a cluster so a single IPI per cluster is sent */ in __x2apic_send_IPI_mask()
57 for_each_cpu(cpu, tmpmsk) { in __x2apic_send_IPI_mask()
58 struct cpumask *cmsk = per_cpu(cluster_masks, cpu); in __x2apic_send_IPI_mask()
68 /* Remove cluster CPUs from tmpmask */ in __x2apic_send_IPI_mask()
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/linux/Documentation/admin-guide/pm/
H A Dintel_uncore_frequency_scaling.rst1 .. SPDX-License-Identifier: GPL-2.0
8 :Copyright: |copy| 2022-2023 Intel Corporation
13 ------------
22 the scaling min/max frequencies via cpufreq sysfs to improve CPU performance.
30 ---------------
33 `/sys/devices/system/cpu/intel_uncore_frequency/`.
36 uncore scaling control is per die in multiple die/package SoCs or per
37 package for single die per package SoCs. The name represents the
45 This is a read-only attribute. If users adjust max_freq_khz,
50 This is a read-only attribute. If users adjust min_freq_khz,
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/linux/arch/mips/kernel/
H A Dcacheinfo.c1 // SPDX-License-Identifier: GPL-2.0-only
10 leaf->type = c_type; \
11 leaf->level = c_level; \
12 leaf->coherency_line_size = c->cache.linesz; \
13 leaf->number_of_sets = c->cache.sets; \
14 leaf->ways_of_associativity = c->cache.ways; \
15 leaf->size = c->cache.linesz * c->cache.sets * \
16 c->cache.ways; \
20 int init_cache_level(unsigned int cpu) in init_cache_level() argument
23 struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); in init_cache_level()
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H A Dsmp-cps.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/cpu.h>
19 #include <asm/mips-cps.h>
22 #include <asm/pm-cps.h>
26 #include <asm/smp-cps.h>
44 static void power_up_other_cluster(unsigned int cluster) in power_up_other_cluster() argument
49 mips_cm_lock_other(cluster, CM_GCR_Cx_OTHER_CORE_CM, 0, in power_up_other_cluster()
60 mips_cm_lock_other(cluster, 0, 0, CM_GCR_Cx_OTHER_BLOCK_GLOBAL); in power_up_other_cluster()
67 mips_cm_lock_other(cluster, CM_GCR_Cx_OTHER_CORE_CM, 0, in power_up_other_cluster()
78 timeout--; in power_up_other_cluster()
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/linux/tools/perf/tests/shell/
H A Dstat+json_output.sh3 # SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause)
7 set -e
19 rm -f "${stat_output}"
21 trap - EXIT TERM INT
33 [ "$(id -u)" != 0 ] && [ "$(cat /proc/sys/kernel/perf_event_paranoid)" -gt $1 ]
38 echo -n "Checking json output: no args "
39 perf stat -j -o "${stat_output}" true
40 $PYTHON $pythonchecker --no-args --file "${stat_output}"
46 echo -n "Checking json output: system wide "
52 perf stat -j -a -o "${stat_output}" true
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/linux/tools/perf/Documentation/
H A Dperf-stat.txt1 perf-stat(1)
5 ----
6 perf-stat - Run a command and gather performance counter statistics
9 --------
11 'perf stat' [-e <EVENT> | --event=EVENT] [-a] <command>
12 'perf stat' [-e <EVENT> | --event=EVENT] [-a] \-- <command> [<options>]
13 'perf stat' [-e <EVENT> | --event=EVENT] [-a] record [-o file] \-- <command> [<options>]
14 'perf stat' report [-i file]
17 -----------
23 -------
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/linux/arch/arm/include/asm/
H A Dmcpm.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * Copyright: (C) 2012-2013 Linaro Limited
13 * Maximum number of possible clusters / CPUs per cluster.
39 * This is used to indicate where the given CPU from given cluster should
40 * branch once it is ready to re-enter the kernel using ptr, or NULL if it
41 * should be gated. A gated CPU is held in a WFE loop until its vector
44 void mcpm_set_entry_vector(unsigned cpu, unsigned cluster, void *ptr);
48 * from very early assembly code before the CPU is ungated. The
51 void mcpm_set_early_poke(unsigned cpu, unsigned cluster,
55 * CPU/cluster power operations API for higher subsystems to use.
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/linux/tools/perf/tests/shell/lib/
H A Dstat_output.sh2 # SPDX-License-Identifier: GPL-2.0
7 [ "$(id -u)" != 0 ] && [ "$(cat /proc/sys/kernel/perf_event_paranoid)" -gt $1 ]
13 echo -n "Checking $1 output: no args "
15 commachecker --no-args
21 echo -n "Checking $1 output: system wide "
27 perf stat -a $2 true
28 commachecker --system-wide
34 echo -n "Checking $1 output: system wide no aggregation "
40 perf stat -A -a --no-merge $2 true
41 commachecker --system-wide-no-aggr
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H A Dperf_json_output_lint.py2 # SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause)
10 ap.add_argument('--no-args', action='store_true')
11 ap.add_argument('--interval', action='store_true')
12 ap.add_argument('--system-wide-no-aggr', action='store_true')
13 ap.add_argument('--system-wide', action='store_true')
14 ap.add_argument('--event', action='store_true')
15 ap.add_argument('--per-core', action='store_true')
16 ap.add_argument('--per-thread', action='store_true')
17 ap.add_argument('--per-cache', action='store_true')
18 ap.add_argument('--per-cluster', action='store_true')
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/linux/include/linux/
H A Dswap.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #include <linux/page-flags.h>
28 #define SWAP_FLAG_DISCARD_ONCE 0x20000 /* discard swap area at swapon-time */
29 #define SWAP_FLAG_DISCARD_PAGES 0x40000 /* discard page-clusters after use */
38 return current->flags & PF_KSWAPD; in current_is_kswapd()
46 * on 32-bit-pgoff_t architectures. And that assumes that the architecture packs
69 * device memory that is unaddressable (inaccessible) by CPU, so that we can
72 * When a page is migrated from CPU to device, we set the CPU page table entry
75 * When a page is mapped by the device for exclusive access we set the CPU page
116 ((1 << MAX_SWAPFILES_SHIFT) - SWP_DEVICE_NUM - \
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H A Dcpu_pm.h1 /* SPDX-License-Identifier: GPL-2.0-only */
16 * When a CPU goes to a low power state that turns off power to the CPU's
25 * The notifications are split into two classes: CPU notifications and CPU
26 * cluster notifications.
28 * CPU notifications apply to a single CPU and must be called on the affected
29 * CPU. They are used to save per-cpu context for affected blocks.
31 * CPU cluster notifications apply to all CPUs in a single power domain. They
41 /* A single cpu is entering a low power state */
44 /* A single cpu failed to enter a low power state */
47 /* A single cpu is exiting a low power state */
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/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/
H A Dl1d_cache.json4 …ns that missed in the level 1 data cache. This event only counts one event per cache line. This ev…
8 …fied memory structures, for example refill buffers, write buffers, and write-back buffers, are als…
12 …-backs of dirty data from the L1 data cache to the L2 cache. This occurs when either a dirty cache…
24 … read operation misses in the level 1 data cache. This event only counts one event per cache line."
28 …write operation misses in the level 1 data cache. This event only counts one event per cache line."
32 …cache refills where the cache line data came from caches inside the immediate cluster of the core."
36 …he refills for which the cache line data came from outside the immediate cluster of the core, like…
44 …cDescription": "Counts write-backs from the level 1 data cache that are a result of a coherency op…
48 …- Cache Maintenance Operations (CMO) that operate by a virtual address.\n- Broadcast cache coheren…
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/
H A Dl1d_cache.json4 …ns that missed in the level 1 data cache. This event only counts one event per cache line. This ev…
8 …fied memory structures, for example refill buffers, write buffers, and write-back buffers, are als…
12 …-backs of dirty data from the L1 data cache to the L2 cache. This occurs when either a dirty cache…
28 … read operation misses in the level 1 data cache. This event only counts one event per cache line."
32 …write operation misses in the level 1 data cache. This event only counts one event per cache line."
36 …cache refills where the cache line data came from caches inside the immediate cluster of the core."
40 …he refills for which the cache line data came from outside the immediate cluster of the core, like…
48 …cDescription": "Counts write-backs from the level 1 data cache that are a result of a coherency op…
52 …- Cache Maintenance Operations (CMO) that operate by a virtual address.\n- Broadcast cache coheren…
/linux/Documentation/admin-guide/perf/
H A Dqcom_l2_pmu.rst2 Qualcomm Technologies Level-2 Cache Performance Monitoring Unit (PMU)
7 own PMU. Each cluster has one or more CPUs associated with it.
17 Events can be envisioned as a 2-dimensional array. Each column represents
23 the code (array row) and G specifies the group (column) 0-7.
29 consisting of one CPU per cluster which will be used to handle all the PMU
30 events on that cluster.
34 perf stat -e l2cache_0/config=0x001/,l2cache_0/config=0x042/ -a sleep 1
36 perf stat -e l2cache_0/config=0xfe/ -C 2 sleep 1
39 not work. Per-task perf sessions are not supported.
/linux/drivers/irqchip/
H A Dirq-mips-gic.c6 * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
10 #define pr_fmt(fmt) "irq-mips-gic: " fmt
26 #include <asm/mips-cps.h>
30 #include <dt-bindings/interrupt-controller/mips-gic.h>
35 /* Add 2 to convert GIC CPU pin to core interrupt */
44 #define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE)
47 #define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE)
71 unsigned int cpu; in __gic_with_next_online_cpu() local
73 /* Discover the next online CPU */ in __gic_with_next_online_cpu()
74 cpu = cpumask_next(prev, cpu_online_mask); in __gic_with_next_online_cpu()
[all …]
H A Dirq-apple-aic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Based on irq-lpc32xx:
6 * Copyright 2015-2016 Vladimir Zapolskiy <vz@mleia.com>
7 * Based on irq-bcm2836:
14 * - 896 level-triggered hardware IRQs
15 * - Single mask bit per IRQ
16 * - Per-IRQ affinity setting
17 * - Automatic masking on event delivery (auto-ack)
18 * - Software triggering (ORed with hw line)
19 * - 2 per-CPU IPIs (meant as "self" and "other", but they are
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/linux/Documentation/devicetree/bindings/arm/
H A Darm,cci-400.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,cci-400.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 ARM multi-cluster systems maintain intra-cluster coherency through a cache
19 space and multiple sets of interface control registers, one per slave
24 pattern: "^cci(@[0-9a-f]+)?$"
28 - arm,cci-400
29 - arm,cci-500
[all …]
H A Dpsci.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
15 processors") can be used by Linux to initiate various CPU-centric power
18 Issue A of the specification describes functions for CPU suspend, hotplug
25 r0 => 32-bit Function ID / return value
26 {r1 - r3} => Parameters
40 - description:
44 - description:
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/linux/tools/perf/
H A Dbuiltin-stat.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * builtin-stat.c
6 * overview about any workload, CPU or specific PID.
16 1708.761321 task-clock # 11.037 CPUs utilized
17 41,190 context-switches # 0.024 M/sec
18 6,735 CPU-migrations # 0.004 M/sec
19 17,318 page-faults # 0.010 M/sec
21 3,856,436,920 stalled-cycles-frontend # 74.09% frontend cycles idle
22 1,600,790,871 stalled-cycles-backend # 30.75% backend cycles idle
23 2,603,501,247 instructions # 0.50 insns per cycle
[all …]
/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,k3-r5f-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F
14 processor subsystems/clusters (R5FSS). The dual core cluster can be used
20 AM64x SoCs do not support LockStep mode, but rather a new non-safety mode
21 called "Single-CPU" mode, where only Core0 is used, but with ability to use
27 Each Dual-Core R5F sub-system is represented as a single DTS node
[all …]
H A Dxlnx,zynqmp-r5fss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ben Levinsky <ben.levinsky@amd.com>
11 - Tanmay Shah <tanmay.shah@amd.com>
14 The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
15 real-time processing based on the Cortex-R5F processor core from ARM.
16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a
17 floating-point unit that implements the Arm VFPv3 instruction set.
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/linux/arch/x86/kvm/svm/
H A Davic.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
19 #include <linux/amd-iommu.h>
65 static_assert(__AVIC_GATAG(AVIC_VM_ID_MASK, AVIC_VCPU_IDX_MASK) == -1u);
67 #define AVIC_AUTO_MODE -1
72 *(int *)kp->arg = AVIC_AUTO_MODE; in avic_param_set()
133 * Note! Always intercept LVTT, as TSC-deadline timer mode in avic_set_x2apic_msr_interception()
134 * isn't virtualized by hardware, and the CPU will generate a in avic_set_x2apic_msr_interception()
148 if (intercept == svm->x2avic_msrs_intercepted) in avic_set_x2apic_msr_interception()
155 svm_set_intercept_for_msr(&svm->vcpu, x2avic_passthrough_msrs[i], in avic_set_x2apic_msr_interception()
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dapple,aic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
19 - Level-triggered hardware IRQs wired to SoC blocks
20 - Single mask bit per IRQ
21 - Per-IRQ affinity setting
22 - Automatic masking on event delivery (auto-ack)
23 - Software triggering (ORed with hw line)
[all …]
/linux/Documentation/devicetree/bindings/opp/
H A Dopp-v2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2
22 - |
24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
28 #address-cells = <1>;
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