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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A D	riscv,imsics.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,imsics.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: RISC-V Incoming MSI Controller (IMSIC) 10 - Anup Patel <anup@brainfault.org> 13 The RISC-V advanced interrupt architecture (AIA) defines a per-CPU incoming 14 MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V 15 AIA specification can be found at https://github.com/riscv/riscv-aia. 17 The IMSIC is a per-CPU (or per-HART) device with separate interrupt file [all …]
/linux/drivers/irqchip/
H A D	irq-riscv-intc.c	1 // SPDX-License-Identifier: GPL-2.0 4 * Copyright (C) 2017-2018 SiFive 8 #define pr_fmt(fmt) "riscv-intc: " fmt 31 unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; in riscv_intc_irq() 46 * On RISC-V systems local interrupts are masked or unmasked by writing 48 * on the local hart, these functions can only be called on the hart that 54 if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG) in riscv_intc_irq_mask() 55 csr_clear(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); in riscv_intc_irq_mask() 57 csr_clear(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_mask() 62 if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG) in riscv_intc_irq_unmask() [all …]
H A D	irq-riscv-imsic-state.c	1 // SPDX-License-Identifier: GPL-2.0 7 #define pr_fmt(fmt) "riscv-imsic: " fmt 22 #include "irq-riscv-imsic-state.h" 63 return imsic ? &imsic->global : NULL; in imsic_get_global_config() 74 imask = BIT(id & (__riscv_xlen - 1)); in __imsic_eix_read_clear() 102 * are XLEN-wide and we must not touch IDs which in __imsic_eix_update() 106 for (i = id & (__riscv_xlen - 1); id < last_id && i < __riscv_xlen; i++) { in __imsic_eix_update() 133 lockdep_assert_held(&lpriv->lock); in __imsic_local_sync() 135 for_each_set_bit(i, lpriv->dirty_bitmap, imsic->global.nr_ids + 1) { in __imsic_local_sync() 138 vec = &lpriv->vectors[i]; in __imsic_local_sync() [all …]
H A D	irq-riscv-imsic-platform.c	1 // SPDX-License-Identifier: GPL-2.0 7 #define pr_fmt(fmt) "riscv-imsic: " fmt 23 #include "irq-riscv-imsic-state.h" 31 global = &imsic->global; in imsic_cpu_page_phys() 32 local = per_cpu_ptr(global->local, cpu); in imsic_cpu_page_phys() 34 if (BIT(global->guest_index_bits) <= guest_index) in imsic_cpu_page_phys() 38 out_msi_pa = local->msi_pa + (guest_index IMSIC_MMIO_PAGE_SZ); in imsic_cpu_page_phys() 59 return -ENOENT; in imsic_irq_retrigger() 61 local = per_cpu_ptr(imsic->global.local, vec->cpu); in imsic_irq_retrigger() 62 writel_relaxed(vec->local_id, local->msi_va); in imsic_irq_retrigger() [all …]
/linux/arch/riscv/mm/
H A D	cacheflush.c	1 // SPDX-License-Identifier: GPL-2.0-only 35 * Performs an icache flush for the given MM context. RISC-V has no direct 39 * single-hart processes on a many-hart machine, ie 'make -j') we avoid the 42 * execution resumes on each hart. 51 /* Mark every hart's icache as needing a flush for this MM. / in flush_icache_mm() 52 mask = &mm->context.icache_stale_mask; in flush_icache_mm() 54 / Flush this hart's I$ now, and mark it as flushed. / in flush_icache_mm() 65 if (mm == current->active_mm && local) { in flush_icache_mm() 68 performed on this hart between setting a hart's cpumask bit in flush_icache_mm() 69 * and scheduling this MM context on that hart. Sending an SBI in flush_icache_mm() [all …]
/linux/include/linux/irqchip/
H A D	riscv-imsic.h	`1 /* SPDX-License-Identifier: GPL-2.0-only / 50 XLEN-1 12 0 52 * ------------------------------------------------------------- 53 * \|xxxxxx\|Group Index\|xxxxxxxxxxx\|HART Index\|Guest Index\| 0 \| 54 * ------------------------------------------------------------- 57 /* Bits representing Guest index, HART index, and Group index / 72 / Per-CPU IMSIC addresses */`
/linux/arch/riscv/kernel/
H A D	kexec_relocate.S	1 /* SPDX-License-Identifier: GPL-2.0 / 3 Copyright (C) 2019 FORTH-ICS/CARV 19 * s3: (const) The hartid of the current hart 50 * With C-extension, here we get 42 Bytes and the next 59 REG_L t0, 0(s0) /* t0 = image->entry / 60 addi s0, s0, RISCV_SZPTR /* image->entry++ / 62 / IND_DESTINATION entry ? -> save destination address / 69 / IND_INDIRECTION entry ? -> update next entry ptr (PA) / 77 / IND_DONE entry ? -> jump to done label / 84 IND_SOURCE entry ? -> copy page word by word to the [all …]
H A D	cpufeature.c	1 // SPDX-License-Identifier: GPL-2.0-only 29 #define NUM_ALPHA_EXTS ('z' - 'a' + 1) 36 /* Per-cpu ISA extensions. / 40 riscv_isa_extension_base() - Get base extension word 56 * __riscv_isa_extension_available() - Check whether given extension 80 pr_err("Zicbom detected in ISA string, disabling as no cbom-block-size found\n"); in riscv_ext_zicbom_validate() 81 return -EINVAL; in riscv_ext_zicbom_validate() 84 pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n"); in riscv_ext_zicbom_validate() 85 return -EINVAL; in riscv_ext_zicbom_validate() 94 pr_err("Zicboz detected in ISA string, disabling as no cboz-block-size found\n"); in riscv_ext_zicboz_validate() [all …]
/linux/Documentation/devicetree/bindings/timer/
H A D	sifive,clint.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Palmer Dabbelt <palmer@dabbelt.com> 11 - Anup Patel <anup.patel@wdc.com> 14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive 15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor 16 interrupts. It directly connects to the timer and inter-processor interrupt 17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local 19 The clock frequency of CLINT is specified via "timebase-frequency" DT [all …]
/linux/Documentation/arch/riscv/
H A D	boot.rst	`1 .. SPDX-License-Identifier: GPL-2.0 4 RISC-V Kernel Boot Requirements and Constraints 10 This document describes what the RISC-V kernel expects from bootloaders and 16 Pre-kernel Requirements and Constraints 19 The RISC-V kernel expects the following of bootloaders and platform firmware: 22 -------------- 24 The RISC-V kernel expects: 30 --------- 32 The RISC-V kernel expects: 37 ------------------------------------- [all …]`
/linux/scripts/gdb/linux/
H A D	cpus.py	`4 # per-cpu tools 6 # Copyright (c) Siemens AG, 2011-2013 27 return gdb.selected_thread().num - 1 36 if cpu == -1: 77 entry = -1 129 super(LxCpus, self).__init__("lx-cpus", gdb.COMMAND_DATA) 142 """Return per-cpu variable. 144 $lx_per_cpu("VAR"[, CPU]): Return the per [all...]`
/linux/drivers/cpuidle/
H A D	cpuidle-riscv-sbi.c	1 // SPDX-License-Identifier: GPL-2.0-only 3 * RISC-V SBI CPU idle driver. 9 #define pr_fmt(fmt) "cpuidle-riscv-sbi: " fmt 52 data->available = true; in sbi_set_domain_state() 53 data->state = state; in sbi_set_domain_state() 60 return data->state; in sbi_get_domain_state() 67 data->available = false; in sbi_clear_domain_state() 74 return data->available; in sbi_is_domain_state_available() 95 u32 states = data->states; in __sbi_enter_domain_idle_state() 96 struct device pd_dev = data->dev; in __sbi_enter_domain_idle_state() [all …]
/linux/Documentation/timers/
H A D	highres.rst	`8 https://www.kernel.org/doc/ols/2006/ols2006v1-pages-333-346.pdf 11 http://www.cs.columbia.edu/~nahum/w6998/papers/ols2006-hrtimers-slides.pdf 23 - hrtimer base infrastructure 24 - timeofday and clock source management 25 - clock event management 26 - high resolution timer functionality 27 - dynamic ticks 31 --------------------------- 40 - time ordered enqueueing into a rb-tree 41 - independent of ticks (the processing is based on nanoseconds) [all …]`
/linux/arch/riscv/
H A D	Kconfig	1 # SPDX-License-Identifier: GPL-2.0-only 4 # see Documentation/kbuild/kconfig-language.rst. 63 # LLD >= 14: https://github.com/llvm/llvm-project/issues/50505 216 # -Zsanitizer=shadow-call-stack flag. 226 depends on $(cc-option,-fpatchable-function-entry=8) 229 def_bool $(cc-option,-fsanitize=shadow-call-stack) 230 …# https://github.com/riscv-non-isa/riscv-elf-psabi-doc/commit/a484e843e6eeb51f0cb7b8819e50da6d2444… 231 depends on $(ld-option,--no-relax-gp) 235 # https://github.com/llvm/llvm-project/commit/6611d58f5bbcbec77262d392e2923e1d680f6985 238 # https://github.com/llvm/llvm-project/commit/bbc0f99f3bc96f1db16f649fc21dd18e5b0918f6 [all …]
/linux/arch/riscv/kvm/
H A D	aia.c	1 // SPDX-License-Identifier: GPL-2.0 13 #include <linux/irqchip/riscv-imsic.h> 38 raw_spin_lock_irqsave(&hgctrl->lock, flags); in aia_find_hgei() 40 hgei = -1; in aia_find_hgei() 42 if (hgctrl->owners[i] == owner) { in aia_find_hgei() 48 raw_spin_unlock_irqrestore(&hgctrl->lock, flags); in aia_find_hgei() 71 struct kvm_vcpu_aia_csr *csr = &vcpu->arch.aia_context.guest_csr; in kvm_riscv_vcpu_aia_flush_interrupts() 77 if (READ_ONCE(vcpu->arch.irqs_pending_mask[1])) { in kvm_riscv_vcpu_aia_flush_interrupts() 78 mask = xchg_acquire(&vcpu->arch.irqs_pending_mask[1], 0); in kvm_riscv_vcpu_aia_flush_interrupts() 79 val = READ_ONCE(vcpu->arch.irqs_pending[1]) & mask; in kvm_riscv_vcpu_aia_flush_interrupts() [all …]
/linux/drivers/clocksource/
H A D	Kconfig	1 # SPDX-License-Identifier: GPL-2.0-only 60 bool "OMAP dual-mode timer driver" if ARCH_K3 \|\| COMPILE_TEST 64 Enables the support for the TI dual-mode timer driver. 190 Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture, 213 32-bit free running decrementing counters. 248 bool "Integrator-AP timer driver" if COMPILE_TEST 251 Enables support for the Integrator-AP timer. 276 available on many OMAP-like platforms. 295 bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST 299 These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores [all …]
/linux/Documentation/process/
H A D	embargoed-hardware-issues.rst	7 ----- 23 ------- 31 Linux kernel security team (:ref:`Documentation/admin-guide/ 34 The team can be contacted by email at <hardware-security@kernel.org>. This 43 - PGP: https://www.kernel.org/static/files/hardware-security.asc 44 - S/MIME: https://www.kernel.org/static/files/hardware-security.crt 55 - Linus Torvalds (Linux Foundation Fellow) 56 - Greg Kroah-Hartman (Linux Foundation Fellow) 57 - Thomas Gleixner (Linux Foundation Fellow) 59 Operation of mailing-lists [all …]
/linux/Documentation/RCU/
H A D	RTFP.txt	4 This document describes RCU-related publications, and is followed by 19 with short-lived threads, such as the K42 research operating system. 20 However, Linux has long-lived tasks, so more is needed. 23 serialization, which is an RCU-like mechanism that relies on the presence 27 that these overheads were not so expensive in the mid-80s. Nonetheless, 28 passive serialization appears to be the first deferred-destruction 30 has lapsed, so this approach may be used in non-GPL software, if desired. 34 In 1987, Rashid et al. described lazy TLB-flush [RichardRashid87a]. 36 this paper helped inspire the update-side batching used in the later 38 a description of Argus that noted that use of out-of-date values can [all …]
/linux/include/acpi/
H A D	actbl2.h	1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 / 4 Name: actbl2.h - ACPI Table Definitions (tables not in ACPI spec) 6 * Copyright (C) 2000 - 2023, Intel Corp. 52 #define ACPI_SIG_RHCT "RHCT" /* RISC-V Hart Capabilities Table / 60 All tables must be byte-packed to match the ACPI specification, since 70 * essentially useless for dealing with packed data in on-disk formats or 79 * AEST - Arm Error Source Table 90 /* Common Subtable header - one per Node Structure (Subtable) / 323 AGDI - Arm Generic Diagnostic Dump and Reset Device Interface 343 * APMT - ARM Performance Monitoring Unit Table [all …]
/linux/
H A D	MAINTAINERS	5 --------------------------------------------------- 21 W: Web-page with status/info 23 B: URI for where to file bugs. A web-page with detailed bug 28 patches to the given subsystem. This is either an in-tree file, 29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst 38 One pattern per line. Multiple F: lines acceptable. 46 N: [^a-z]tegra all files whose path contains tegra 48 One pattern per line. Multiple N: lines acceptable. 61 One regex pattern per line. Multiple K: lines acceptable. 64 ---------------- [all …]