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/linux/drivers/irqchip/
H A Dirq-riscv-intc.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2017-2018 SiFive
8 #define pr_fmt(fmt) "riscv-intc: " fmt
31 unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; in riscv_intc_irq()
46 * On RISC-V systems local interrupts are masked or unmasked by writing
48 * on the local hart, these functions can only be called on the hart that
54 if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG) in riscv_intc_irq_mask()
55 csr_clear(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); in riscv_intc_irq_mask()
57 csr_clear(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_mask()
62 if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG) in riscv_intc_irq_unmask()
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H A Dirq-riscv-imsic-state.c1 // SPDX-License-Identifier: GPL-2.0
7 #define pr_fmt(fmt) "riscv-imsic: " fmt
22 #include "irq-riscv-imsic-state.h"
63 return imsic ? &imsic->global : NULL; in imsic_get_global_config()
74 imask = BIT(id & (__riscv_xlen - 1)); in __imsic_eix_read_clear()
102 * are XLEN-wide and we must not touch IDs which in __imsic_eix_update()
106 for (i = id & (__riscv_xlen - 1); id < last_id && i < __riscv_xlen; i++) { in __imsic_eix_update()
134 lockdep_assert_held(&lpriv->lock); in __imsic_local_sync()
136 for_each_set_bit(i, lpriv->dirty_bitmap, imsic->global.nr_ids + 1) { in __imsic_local_sync()
139 vec = &lpriv->vectors[i]; in __imsic_local_sync()
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H A Dirq-riscv-aplic-direct.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/irqchip/riscv-aplic.h>
20 #include "irq-riscv-aplic-main.h"
61 cpu = cpumask_first_and(&direct->lmask, mask_val); in aplic_direct_set_affinity()
63 cpu = cpumask_first_and_and(&direct->lmask, mask_val, cpu_online_mask); in aplic_direct_set_affinity()
66 return -EINVAL; in aplic_direct_set_affinity()
69 target = priv->regs + APLIC_TARGET_BASE + (d->hwirq - 1) * sizeof(u32); in aplic_direct_set_affinity()
70 val = FIELD_PREP(APLIC_TARGET_HART_IDX, idc->hart_index); in aplic_direct_set_affinity()
81 .name = "APLIC-DIRECT",
97 struct aplic_priv *priv = d->host_data; in aplic_direct_irqdomain_translate()
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H A Dirq-riscv-imsic-platform.c1 // SPDX-License-Identifier: GPL-2.0
7 #define pr_fmt(fmt) "riscv-imsic: " fmt
23 #include <linux/irqchip/irq-msi-lib.h>
24 #include "irq-riscv-imsic-state.h"
32 global = &imsic->global; in imsic_cpu_page_phys()
33 local = per_cpu_ptr(global->local, cpu); in imsic_cpu_page_phys()
35 if (BIT(global->guest_index_bits) <= guest_index) in imsic_cpu_page_phys()
39 *out_msi_pa = local->msi_pa + (guest_index * IMSIC_MMIO_PAGE_SZ); in imsic_cpu_page_phys()
60 return -ENOENT; in imsic_irq_retrigger()
62 local = per_cpu_ptr(imsic->global.local, vec->cpu); in imsic_irq_retrigger()
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/linux/arch/riscv/mm/
H A Dcacheflush.c1 // SPDX-License-Identifier: GPL-2.0-only
30 * the IPI. The RISC-V spec states that a hart must execute a data fence in flush_icache_all()
34 * IPIs on RISC-V are triggered by MMIO writes to either CLINT or in flush_icache_all()
35 * S-IMSIC, so the fence ensures previous data writes "happen before" in flush_icache_all()
48 * Performs an icache flush for the given MM context. RISC-V has no direct
52 * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
55 * execution resumes on each hart.
64 /* Mark every hart's icache as needing a flush for this MM. */ in flush_icache_mm()
65 mask = &mm->context.icache_stale_mask; in flush_icache_mm()
67 /* Flush this hart's I$ now, and mark it as flushed. */ in flush_icache_mm()
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/linux/include/linux/irqchip/
H A Driscv-imsic.h1 /* SPDX-License-Identifier: GPL-2.0-only */
50 * XLEN-1 12 0
52 * -------------------------------------------------------------
53 * |xxxxxx|Group Index|xxxxxxxxxxx|HART Index|Guest Index| 0 |
54 * -------------------------------------------------------------
57 /* Bits representing Guest index, HART index, and Group index */
72 /* Per-CPU IMSIC addresses */
/linux/arch/riscv/kernel/
H A Dkexec_relocate.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2019 FORTH-ICS/CARV
19 * s3: (const) The hartid of the current hart
50 * With C-extension, here we get 42 Bytes and the next
59 REG_L t0, 0(s0) /* t0 = *image->entry */
60 addi s0, s0, RISCV_SZPTR /* image->entry++ */
62 /* IND_DESTINATION entry ? -> save destination address */
69 /* IND_INDIRECTION entry ? -> update next entry ptr (PA) */
77 /* IND_DONE entry ? -> jump to done label */
84 * IND_SOURCE entry ? -> copy page word by word to the
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H A Dcpufeature.c1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <asm/text-patching.h>
32 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
43 /* Per-cpu ISA extensions. */
49 * riscv_isa_extension_base() - Get base extension word
63 * __riscv_isa_extension_available() - Check whether given extension
89 return -EPROBE_DEFER; in riscv_ext_f_depends()
96 pr_err("Zicbom detected in ISA string, disabling as no cbom-block-size found\n"); in riscv_ext_zicbom_validate()
97 return -EINVAL; in riscv_ext_zicbom_validate()
100 pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n"); in riscv_ext_zicbom_validate()
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/linux/Documentation/devicetree/bindings/timer/
H A Dsifive,clint.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
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/linux/Documentation/arch/riscv/
H A Dboot.rst1 .. SPDX-License-Identifier: GPL-2.0
4 RISC-V Kernel Boot Requirements and Constraints
10 This document describes what the RISC-V kernel expects from bootloaders and
16 Pre-kernel Requirements and Constraints
19 The RISC-V kernel expects the following of bootloaders and platform firmware:
22 --------------
24 The RISC-V kernel expects:
30 ---------
32 The RISC-V kernel expects:
37 -------------------------------------
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/linux/scripts/gdb/linux/
H A Dcpus.py4 # per-cpu tools
6 # Copyright (c) Siemens AG, 2011-2013
27 return gdb.selected_thread().num - 1
36 if cpu == -1:
77 entry = -1
129 super(LxCpus, self).__init__("lx-cpus", gdb.COMMAND_DATA)
142 """Return per-cpu variable.
144 $lx_per_cpu(VAR[, CPU]): Return the per-cpu variable called VAR for the
151 def invoke(self, var, cpu=-1):
159 """Return per-cpu pointer.
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/linux/drivers/cpuidle/
H A Dcpuidle-riscv-sbi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * RISC-V SBI CPU idle driver.
9 #define pr_fmt(fmt) "cpuidle-riscv-sbi: " fmt
52 data->available = true; in sbi_set_domain_state()
53 data->state = state; in sbi_set_domain_state()
60 return data->state; in sbi_get_domain_state()
67 data->available = false; in sbi_clear_domain_state()
74 return data->available; in sbi_is_domain_state_available()
95 u32 *states = data->states; in __sbi_enter_domain_idle_state()
96 struct device *pd_dev = data->dev; in __sbi_enter_domain_idle_state()
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/linux/Documentation/timers/
H A Dhighres.rst8 https://www.kernel.org/doc/ols/2006/ols2006v1-pages-333-346.pdf
11 http://www.cs.columbia.edu/~nahum/w6998/papers/ols2006-hrtimers-slides.pdf
23 - hrtimer base infrastructure
24 - timeofday and clock source management
25 - clock event management
26 - high resolution timer functionality
27 - dynamic ticks
31 ---------------------------
40 - time ordered enqueueing into a rb-tree
41 - independent of ticks (the processing is based on nanoseconds)
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/linux/arch/riscv/kvm/
H A Daia.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/irqchip/riscv-imsic.h>
50 struct kvm_vcpu_aia_csr *csr = &vcpu->arch.aia_context.guest_csr; in kvm_riscv_vcpu_aia_flush_interrupts()
56 if (READ_ONCE(vcpu->arch.irqs_pending_mask[1])) { in kvm_riscv_vcpu_aia_flush_interrupts()
57 mask = xchg_acquire(&vcpu->arch.irqs_pending_mask[1], 0); in kvm_riscv_vcpu_aia_flush_interrupts()
58 val = READ_ONCE(vcpu->arch.irqs_pending[1]) & mask; in kvm_riscv_vcpu_aia_flush_interrupts()
60 csr->hviph &= ~mask; in kvm_riscv_vcpu_aia_flush_interrupts()
61 csr->hviph |= val; in kvm_riscv_vcpu_aia_flush_interrupts()
67 struct kvm_vcpu_aia_csr *csr = &vcpu->arch.aia_context.guest_csr; in kvm_riscv_vcpu_aia_sync_interrupts()
70 csr->vsieh = ncsr_read(CSR_VSIEH); in kvm_riscv_vcpu_aia_sync_interrupts()
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/linux/drivers/clocksource/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
60 bool "OMAP dual-mode timer driver" if ARCH_K3 || COMPILE_TEST
64 Enables the support for the TI dual-mode timer driver.
198 Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
221 32-bit free running decrementing counters.
256 bool "Integrator-AP timer driver" if COMPILE_TEST
259 Enables support for the Integrator-AP timer.
284 available on many OMAP-like platforms.
303 bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST
307 These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
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/linux/Documentation/process/
H A Dembargoed-hardware-issues.rst7 -----
23 -------
31 Linux kernel security team (:ref:`Documentation/admin-guide/
34 The team can be contacted by email at <hardware-security@kernel.org>. This
43 - PGP: https://www.kernel.org/static/files/hardware-security.asc
44 - S/MIME: https://www.kernel.org/static/files/hardware-security.crt
55 - Linus Torvalds (Linux Foundation Fellow)
56 - Greg Kroah-Hartman (Linux Foundation Fellow)
57 - Thomas Gleixner (Linux Foundation Fellow)
59 Operation of mailing-lists
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/linux/kernel/futex/
H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0-or-later
16 * PI-futex support started by Ingo Molnar and Thomas Gleixner
23 * Requeue-PI support by Darren Hart <dvhltc@us.ibm.com>
29 * Kirkwood for proof-of-concept implementation.
42 #include <linux/fault-inject.h>
115 debugfs_create_bool("ignore-private", mode, dir, in fail_futex_debugfs()
140 * futexes -- see comment with union futex_key. in futex_key_is_private()
142 return !(key->both.offset & (FUT_OFF_INODE | FUT_OFF_MMSHARED)); in futex_key_is_private()
153 wake_up_var(fph->mm); in futex_private_hash_put()
157 * futex_hash_get - Get an additional reference for the local hash.
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/linux/drivers/platform/x86/
H A Dwmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ACPI-WMI mapping driver
5 * Copyright (C) 2007-2008 Carlos Corbacho <carlos@strangeworlds.co.uk>
9 * Copyright (c) 2001-2007 Anton Altaparmakov
12 * WMI bus infrastructure by Andrew Lutomirski and Darren Hart:
37 MODULE_DESCRIPTION("ACPI-WMI Mapping Driver");
117 id = wdriver->id_table; in find_guid_context()
121 while (*id->guid_string) { in find_guid_context()
122 if (guid_parse_and_compare(id->guid_string, &wblock->gblock.guid)) in find_guid_context()
123 return id->context; in find_guid_context()
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/linux/include/acpi/
H A Dactbl2.h1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
4 * Name: actbl2.h - ACPI Table Definitions
6 * Copyright (C) 2000 - 2025, Intel Corp.
54 #define ACPI_SIG_RHCT "RHCT" /* RISC-V Hart Capabilities Table */
55 #define ACPI_SIG_RIMT "RIMT" /* RISC-V IO Mapping Table */
64 * All tables must be byte-packed to match the ACPI specification, since
74 * essentially useless for dealing with packed data in on-disk formats or
83 * AEST - Arm Error Source Table
94 /* Common Subtable header - one per Node Structure (Subtable) */
327 * AGDI - Arm Generic Diagnostic Dump and Reset Device Interface
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