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/linux/drivers/pinctrl/
H A Dpinctrl-da9062.c1 // SPDX-License-Identifier: GPL-2.0
7 * - add pinmux and pinctrl support (gpio alternate mode)
10 * [1] https://www.dialog-semiconductor.com/sites/default/files/da9062_datasheet_3v6.pdf
18 #include <linux/regmap.h>
30 #define DA9062_PIN_GPO_OD 0x02 /* gpio out open-drain */
31 #define DA9062_PIN_GPO_PP 0x03 /* gpio out push-pull */
40 static int da9062_pctl_get_pin_mode(struct da9062_pctl *pctl, in da9062_pctl_get_pin_mode() argument
43 struct regmap *regmap = pctl->da9062->regmap; in da9062_pctl_get_pin_mode() local
46 ret = regmap_read(regmap, DA9062AA_GPIO_0_1 + (offset >> 1), &val); in da9062_pctl_get_pin_mode()
56 static int da9062_pctl_set_pin_mode(struct da9062_pctl *pctl, in da9062_pctl_set_pin_mode() argument
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H A Dpinctrl-sx150x.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * The handling of the 4-bit chips (SX1501/SX1504/SX1507) is untested.
14 #include <linux/regmap.h>
26 #include <linux/pinctrl/pinconf-generic.h>
30 #include "pinctrl-utils.h"
101 struct regmap *regmap; member
359 return -ENOTSUPP; in sx150x_pinctrl_get_group_pins()
372 static bool sx150x_pin_is_oscio(struct sx150x_pinctrl *pctl, unsigned int pin) in sx150x_pin_is_oscio() argument
374 if (pin >= pctl->data->npins) in sx150x_pin_is_oscio()
378 if (pctl->data->model != SX150X_789) in sx150x_pin_is_oscio()
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H A Dpinctrl-axp209.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
6 * Copyright (C) 2017 Quentin Schulz <quentin.schulz@free-electrons.com>
19 #include <linux/regmap.h>
23 #include <linux/pinctrl/pinconf-generic.h>
69 struct regmap *regmap; member
124 return -EINVAL; in axp20x_gpio_get_reg()
129 struct axp20x_pctl *pctl = gpiochip_get_data(chip); in axp20x_gpio_get() local
135 ret = regmap_read(pctl->regmap, AXP20X_GPIO3_CTRL, &val); in axp20x_gpio_get()
141 ret = regmap_read(pctl->regmap, AXP20X_GPIO20_SS, &val); in axp20x_gpio_get()
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H A Dpinctrl-apple-gpio.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Based on: pinctrl-pistachio.c
13 #include <dt-bindings/pinctrl/apple.h>
24 #include <linux/regmap.h>
29 #include "pinctrl-utils.h"
38 struct regmap *map;
80 /* No locking needed to mask/unmask IRQs as the interrupt mode is per pin-register. */
81 static void apple_gpio_set_reg(struct apple_gpio_pinctrl *pctl, in apple_gpio_set_reg() argument
84 regmap_update_bits(pctl->map, REG_GPIO(pin), mask, value); in apple_gpio_set_reg()
87 static u32 apple_gpio_get_reg(struct apple_gpio_pinctrl *pctl, in apple_gpio_get_reg() argument
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H A Dpinctrl-st.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include <linux/regmap.h>
100 * (direction, retime-type, retime-clk, retime-delay)
102 * +----------------+
103 *[31:28]| reserved-3 |
104 * +----------------+-------------
106 * +----------------+ v
108 * +----------------+ ^
110 * +----------------+-------------
111 *[24] | reserved-2 |
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H A Dpinctrl-single.c25 #include <linux/pinctrl/pinconf-generic.h>
30 #include <linux/platform_data/pinctrl-single.h>
37 #define DRIVER_NAME "pinctrl-single"
41 * struct pcs_func_vals - mux function register offset and value pair
53 * struct pcs_conf_vals - pinconf parameter, pinconf register offset
70 * struct pcs_conf_type - pinconf property name, pinconf param pair
80 * struct pcs_function - pinctrl function
98 * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
112 * struct pcs_data - wrapper for data needed by pinctrl framework
126 * struct pcs_soc_data - SoC specific settings
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H A Dpinctrl-ocelot.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 * Author: <alexandre.belloni@free-electrons.com>
16 #include <linux/regmap.h>
21 #include <linux/pinctrl/pinconf-generic.h>
327 struct pinctrl_dev *pctl; member
329 struct regmap *map;
330 struct regmap *pincfg;
1157 *groups = info->func[function].groups; in ocelot_get_function_groups()
1158 *num_groups = info->func[function].ngroups; in ocelot_get_function_groups()
1166 struct ocelot_pin_caps *p = info->desc->pins[pin].drv_data; in ocelot_pin_function_idx()
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/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mtk-common.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/pinctrl/pinconf-generic.h>
21 #include <linux/regmap.h>
26 #include <dt-bindings/pinctrl/mt65xx.h>
30 #include "../pinctrl-utils.h"
31 #include "mtk-eint.h"
32 #include "pinctrl-mtk-common.h"
50 static struct regmap *mtk_get_regmap(struct mtk_pinctrl *pctl, in mtk_get_regmap() argument
53 if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end) in mtk_get_regmap()
54 return pctl->regmap2; in mtk_get_regmap()
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/linux/drivers/pinctrl/mvebu/
H A Dpinctrl-mvebu.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
15 #include <linux/regmap.h>
24 #include "pinctrl-mvebu.h"
64 *config = (readl(data->base + off) >> shift) & MVEBU_MPP_MASK; in mvebu_mmio_mpp_ctrl_get()
76 reg = readl(data->base + off) & ~(MVEBU_MPP_MASK << shift); in mvebu_mmio_mpp_ctrl_set()
77 writel(reg | (config << shift), data->base + off); in mvebu_mmio_mpp_ctrl_set()
83 struct mvebu_pinctrl *pctl, unsigned pid) in mvebu_pinctrl_find_group_by_pid() argument
86 for (n = 0; n < pctl->num_groups; n++) { in mvebu_pinctrl_find_group_by_pid()
87 if (pid >= pctl->groups[n].pins[0] && in mvebu_pinctrl_find_group_by_pid()
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/linux/drivers/pinctrl/stm32/
H A Dpinctrl-stm32.c1 // SPDX-License-Identifier: GPL-2.0
21 #include <linux/regmap.h>
28 #include <linux/pinctrl/pinconf-generic.h>
35 #include "../pinctrl-utils.h"
36 #include "pinctrl-stm32.h"
114 struct regmap *regmap; member
149 return function - 1; in stm32_gpio_get_alt()
160 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL); in stm32_gpio_backup_value()
161 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL; in stm32_gpio_backup_value()
167 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK | in stm32_gpio_backup_mode()
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmediatek,mt65xx-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@kernel.org>
18 - mediatek,mt2701-pinctrl
19 - mediatek,mt2712-pinctrl
20 - mediatek,mt6397-pinctrl
21 - mediatek,mt7623-pinctrl
22 - mediatek,mt8127-pinctrl
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H A Dmediatek,mt8365-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8365-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Zhiyong Tao <zhiyong.tao@mediatek.com>
11 - Bernhard Rosenkränzer <bero@baylibre.com>
18 const: mediatek,mt8365-pinctrl
23 mediatek,pctl-regmap:
24 $ref: /schemas/types.yaml#/definitions/phandle-array
32 gpio-controller: true
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/linux/drivers/pinctrl/nuvoton/
H A Dpinctrl-ma35.c1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Shan-Chun Hung <schung@nuvoton.com>
18 #include <linux/regmap.h>
24 #include "pinctrl-ma35.h"
59 /* GPIO pull-up and pull-down selection control */
66 * The MA35_GP_REG_INTEN bits 0 ~ 15 control low-level or falling edge trigger,
67 * while bits 16 ~ 31 control high-level or rising edge trigger.
84 /* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */
85 #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
86 #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))
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/linux/drivers/pinctrl/spear/
H A Dpinctrl-spear.c8 * - U300 Pinctl drivers
9 * - Tegra Pinctl drivers
29 #include "pinctrl-spear.h"
31 #define DRIVER_NAME "spear-pinmux"
42 val = pmx_readl(pmx, muxreg->reg); in muxregs_endisable()
43 val &= ~muxreg->mask; in muxregs_endisable()
46 temp = muxreg->val; in muxregs_endisable()
48 temp = ~muxreg->val; in muxregs_endisable()
50 val |= muxreg->mask & temp; in muxregs_endisable()
51 pmx_writel(pmx, val, muxreg->reg); in muxregs_endisable()
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H A Dpinctrl-spear.h18 #include <linux/regmap.h>
26 * struct spear_pmx_mode - SPEAr pmx mode
42 * struct spear_muxreg - SPEAr mux reg configuration
92 * struct spear_modemux - SPEAr mode mux configuration
104 * struct spear_pingroup - SPEAr pin group configurations
123 * struct spear_function - SPEAr pinctrl mux function
135 * struct spear_pinctrl_machdata - SPEAr pin controller machine driver
172 * struct spear_pmx - SPEAr pinctrl mux
174 * @pctl: pointer to struct pinctrl_dev
176 * @regmap: regmap of pinmux controller
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/linux/arch/arm/boot/dts/mediatek/
H A Dmt8135.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt8135-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/mt8135-resets.h>
12 #include <dt-bindings/pinctrl/mt8135-pinfunc.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
18 interrupt-parent = <&sysirq>;
20 cpu-map {
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H A Dmt2701.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt2701-clk.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/mt2701-power.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/memory/mt2701-larb-port.h>
14 #include <dt-bindings/reset/mt2701-resets.h>
15 #include "mt2701-pinfunc.h"
18 #address-cells = <2>;
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H A Dmt7623.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2017-2018 MediaTek Inc.
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/clock/mt2701-clk.h>
13 #include <dt-bindings/pinctrl/mt7623-pinfunc.h>
14 #include <dt-bindings/power/mt2701-power.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/phy/phy.h>
17 #include <dt-bindings/reset/mt2701-resets.h>
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/linux/drivers/pinctrl/cirrus/
H A Dpinctrl-lochnagar.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2017-2018 Cirrus Logic, Inc. and
17 #include <linux/regmap.h>
20 #include <linux/pinctrl/pinconf-generic.h>
29 #include <dt-bindings/pinctrl/lochnagar.h>
31 #include "../pinctrl-utils.h"
35 #define LN_CDC_AIF1_STR "codec-aif1"
36 #define LN_CDC_AIF2_STR "codec-aif2"
37 #define LN_CDC_AIF3_STR "codec-aif3"
38 #define LN_DSP_AIF1_STR "dsp-aif1"
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/linux/drivers/pinctrl/bcm/
H A Dpinctrl-bcm281xx.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2013-2017 Broadcom
9 #include <linux/regmap.h>
13 #include <linux/pinctrl/pinconf-generic.h>
19 #include "../pinctrl-utils.h"
56 * bcm281xx_pin_type - types of pin register
70 * bcm281xx_pin_function- define pin function
79 * bcm281xx_pinctrl_data - Broadcom-specific pinctrl data
80 * @reg_base - base of pinctrl registers
92 struct regmap *regmap; member
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/linux/drivers/pinctrl/aspeed/
H A Dpinctrl-aspeed.c1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include "pinctrl-aspeed.h"
18 return pdata->pinmux.ngroups; in aspeed_pinctrl_get_groups_count()
26 return pdata->pinmux.groups[group].name; in aspeed_pinctrl_get_group_name()
35 *pins = &pdata->pinmux.groups[group].pins[0]; in aspeed_pinctrl_get_group_pins()
36 *npins = pdata->pinmux.groups[group].npins; in aspeed_pinctrl_get_group_pins()
44 seq_printf(s, " %s", dev_name(pctldev->dev)); in aspeed_pinctrl_pin_dbg_show()
51 return pdata->pinmux.nfunctions; in aspeed_pinmux_get_fn_count()
59 return pdata->pinmux.functions[function].name; in aspeed_pinmux_get_fn_name()
69 *groups = pdata->pinmux.functions[function].groups; in aspeed_pinmux_get_fn_groups()
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/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8167.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt8167-clk.h>
9 #include <dt-bindings/memory/mt8167-larb-port.h>
10 #include <dt-bindings/power/mt8167-power.h>
12 #include "mt8167-pinfunc.h"
21 compatible = "mediatek,mt8167-topckgen", "syscon";
23 #clock-cells = <1>;
27 compatible = "mediatek,mt8167-infracfg", "syscon";
29 #clock-cells = <1>;
33 compatible = "mediatek,mt8167-apmixedsys", "syscon";
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H A Dmt8516.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt8516-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/phy/phy.h>
13 #include "mt8516-pinfunc.h"
17 interrupt-parent = <&sysirq>;
18 #address-cells = <2>;
19 #size-cells = <2>;
21 cluster0_opp: opp-table-0 {
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/linux/drivers/rtc/
H A Drtc-stm32.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk-provider.h>
18 #include <linux/pinctrl/pinconf-generic.h>
22 #include <linux/regmap.h>
169 struct regmap *dbp;
189 const struct stm32_rtc_registers *regs = &rtc->data->regs; in stm32_rtc_wpr_unlock()
191 writel_relaxed(RTC_WPR_1ST_KEY, rtc->base + regs->wpr); in stm32_rtc_wpr_unlock()
192 writel_relaxed(RTC_WPR_2ND_KEY, rtc->base + regs->wpr); in stm32_rtc_wpr_unlock()
197 const struct stm32_rtc_registers *regs = &rtc->data->regs; in stm32_rtc_wpr_lock()
199 writel_relaxed(RTC_WPR_WRONG_KEY, rtc->base + regs->wpr); in stm32_rtc_wpr_lock()
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/linux/drivers/net/ethernet/mediatek/
H A Dmtk_eth_soc.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
15 #include <linux/regmap.h>
24 #include <linux/pcs/pcs-mtk-lynxi.h>
34 static int mtk_msg_level = -1;
36 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
294 __raw_writel(val, eth->base + reg); in mtk_w32()
299 return __raw_readl(eth->base + reg); in mtk_r32()
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