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/linux/drivers/pci/controller/
H A Dpcie-altera.c6 * Description: Altera PCIe host controller driver
45 #define S10_RP_CFG_ADDR(pcie, reg) \ argument
46 (((pcie)->hip_base) + (reg) + (1 << 20))
47 #define S10_RP_SECONDARY(pcie) \ argument
48 readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
59 #define TLP_CFG_DW0(pcie, cfg) \ argument
62 #define TLP_CFG_DW1(pcie, tag, be) \ argument
63 (((PCI_DEVID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
81 #define AGLX_RP_CFG_ADDR(pcie, reg) (((pcie)->hip_base) + (reg)) argument
82 #define AGLX_RP_SECONDARY(pcie) \ argument
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H A Dpcie-xilinx-nwl.c3 * PCIe host controller driver for NWL PCIe Bridge
4 * Based on pcie-xilinx.c, pci-tegra.c
163 phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base */
176 static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off) in nwl_bridge_readl() argument
178 return readl(pcie->breg_base + off); in nwl_bridge_readl()
181 static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off) in nwl_bridge_writel() argument
183 writel(val, pcie->breg_base + off); in nwl_bridge_writel()
186 static bool nwl_pcie_link_up(struct nwl_pcie *pcie) in nwl_pcie_link_up() argument
188 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT) in nwl_pcie_link_up()
193 static bool nwl_phy_link_up(struct nwl_pcie *pcie) in nwl_phy_link_up() argument
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H A Dpci-aardvark.c3 * Driver for the Aardvark PCIe controller, used on Marvell Armada
32 /* PCIe core registers */
125 /* PCIe window configuration */
216 /* PCIe core controller registers */
224 /* PCIe Central Interrupts Registers */
292 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) in advk_writel() argument
294 writel(val, pcie->base + reg); in advk_writel()
297 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg) in advk_readl() argument
299 return readl(pcie->base + reg); in advk_readl()
302 static u8 advk_pcie_ltssm_state(struct advk_pcie *pcie) in advk_pcie_ltssm_state() argument
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H A Dpcie-rcar-host.c3 * PCIe driver for Renesas R-Car SoCs
7 * arch/sh/drivers/pci/pcie-sh7786.c
36 #include "pcie-rcar.h"
47 /* Structure representing the PCIe interface */
49 struct rcar_pcie pcie; member
67 * Test if the PCIe controller received PM_ENTER_L1 DLLP and in rcar_pcie_wakeup()
68 * the PCIe controller is not in L1 link state. If true, apply in rcar_pcie_wakeup()
92 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where) in rcar_read_conf() argument
95 u32 val = rcar_pci_read_reg(pcie, where & ~3); in rcar_read_conf()
117 static int rcar_pci_write_reg_workaround(struct rcar_pcie *pcie, u32 val, in rcar_pci_write_reg_workaround() argument
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H A DKconfig11 tristate "Aardvark PCIe controller"
18 Add support for Aardvark 64bit PCIe Host Controller. This
23 tristate "Altera PCIe controller"
26 Say Y here if you want to enable PCIe controller support on Altera
30 tristate "Altera PCIe MSI feature"
35 Say Y here if you want PCIe MSI support for the Altera FPGA.
44 tristate "Apple PCIe controller"
51 Say Y here if you want to enable PCIe controller support on Apple
62 bool "ASPEED PCIe controller"
68 Enable this option to support the PCIe controller found on ASPEED
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H A Dpcie-rcar.c3 * PCIe driver for Renesas R-Car SoCs
12 #include "pcie-rcar.h"
14 void rcar_pci_write_reg(struct rcar_pcie *pcie, u32 val, unsigned int reg) in rcar_pci_write_reg() argument
16 writel(val, pcie->base + reg); in rcar_pci_write_reg()
19 u32 rcar_pci_read_reg(struct rcar_pcie *pcie, unsigned int reg) in rcar_pci_read_reg() argument
21 return readl(pcie->base + reg); in rcar_pci_read_reg()
24 void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data) in rcar_rmw32() argument
27 u32 val = rcar_pci_read_reg(pcie, where & ~3); in rcar_rmw32()
31 rcar_pci_write_reg(pcie, val, where & ~3); in rcar_rmw32()
34 int rcar_pcie_wait_for_phyrdy(struct rcar_pcie *pcie) in rcar_pcie_wait_for_phyrdy() argument
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H A Dpcie-iproc-bcma.c15 #include "pcie-iproc.h"
28 struct iproc_pcie *pcie = dev->sysdata; in iproc_bcma_pcie_map_irq() local
29 struct bcma_device *bdev = container_of(pcie->dev, struct bcma_device, dev); in iproc_bcma_pcie_map_irq()
37 struct iproc_pcie *pcie; in iproc_bcma_pcie_probe() local
41 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); in iproc_bcma_pcie_probe()
45 pcie = pci_host_bridge_priv(bridge); in iproc_bcma_pcie_probe()
47 pcie->dev = dev; in iproc_bcma_pcie_probe()
49 pcie->type = IPROC_PCIE_PAXB_BCMA; in iproc_bcma_pcie_probe()
50 pcie->base = bdev->io_addr; in iproc_bcma_pcie_probe()
51 if (!pcie->base) { in iproc_bcma_pcie_probe()
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/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,sc8280xp-qmp-pcie-phy.yaml4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
7 title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
19 - qcom,glymur-qmp-gen4x2-pcie-phy
20 - qcom,glymur-qmp-gen5x4-pcie-phy
21 - qcom,kaanapali-qmp-gen3x2-pcie-phy
22 - qcom,qcs615-qmp-gen3x1-pcie-phy
23 - qcom,qcs8300-qmp-gen4x2-pcie-phy
24 - qcom,sa8775p-qmp-gen4x2-pcie-phy
25 - qcom,sa8775p-qmp-gen4x4-pcie-phy
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/linux/drivers/pci/controller/dwc/
H A Dpcie-visconti.c3 * DWC PCIe RC driver for Toshiba Visconti ARM SoC
24 #include "pcie-designware.h"
96 /* Access registers in PCIe ulreg */
97 static void visconti_ulreg_writel(struct visconti_pcie *pcie, u32 val, u32 reg) in visconti_ulreg_writel() argument
99 writel_relaxed(val, pcie->ulreg_base + reg); in visconti_ulreg_writel()
102 static u32 visconti_ulreg_readl(struct visconti_pcie *pcie, u32 reg) in visconti_ulreg_readl() argument
104 return readl_relaxed(pcie->ulreg_base + reg); in visconti_ulreg_readl()
107 /* Access registers in PCIe smu */
108 static void visconti_smu_writel(struct visconti_pcie *pcie, u32 val, u32 reg) in visconti_smu_writel() argument
110 writel_relaxed(val, pcie->smu_base + reg); in visconti_smu_writel()
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H A Dpcie-uniphier.c3 * PCIe host controller driver for UniPhier SoCs
23 #include "pcie-designware.h"
75 static void uniphier_pcie_ltssm_enable(struct uniphier_pcie *pcie, in uniphier_pcie_ltssm_enable() argument
80 val = readl(pcie->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
85 writel(val, pcie->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
88 static void uniphier_pcie_init_rc(struct uniphier_pcie *pcie) in uniphier_pcie_init_rc() argument
93 val = readl(pcie->base + PCL_MODE); in uniphier_pcie_init_rc()
96 writel(val, pcie->base + PCL_MODE); in uniphier_pcie_init_rc()
99 val = readl(pcie->base + PCL_APP_PM0); in uniphier_pcie_init_rc()
101 writel(val, pcie->base + PCL_APP_PM0); in uniphier_pcie_init_rc()
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H A Dpcie-armada8k.c3 * PCIe host controller driver for Marvell Armada-8K SoCs
5 * Armada-8K PCIe Glue Layer Source Code
25 #include "pcie-designware.h"
73 static void armada8k_pcie_disable_phys(struct armada8k_pcie *pcie) in armada8k_pcie_disable_phys() argument
78 phy_power_off(pcie->phy[i]); in armada8k_pcie_disable_phys()
79 phy_exit(pcie->phy[i]); in armada8k_pcie_disable_phys()
83 static int armada8k_pcie_enable_phys(struct armada8k_pcie *pcie) in armada8k_pcie_enable_phys() argument
89 ret = phy_init(pcie->phy[i]); in armada8k_pcie_enable_phys()
93 ret = phy_set_mode_ext(pcie->phy[i], PHY_MODE_PCIE, in armada8k_pcie_enable_phys()
94 pcie->phy_count); in armada8k_pcie_enable_phys()
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H A Dpcie-al.c3 * PCIe host controller driver for Amazon's Annapurna Labs IP (used in chips
26 struct al_pcie_acpi *pcie = cfg->priv; in al_pcie_map_bus() local
27 void __iomem *dbi_base = pcie->dbi_base; in al_pcie_map_bus()
31 * The DW PCIe core doesn't filter out transactions to other in al_pcie_map_bus()
92 #include "pcie-designware.h"
132 void __iomem *controller_base; /* base of PCIe unit (not DW core) */
142 static inline u32 al_pcie_controller_readl(struct al_pcie *pcie, u32 offset) in al_pcie_controller_readl() argument
144 return readl_relaxed(pcie->controller_base + offset); in al_pcie_controller_readl()
147 static inline void al_pcie_controller_writel(struct al_pcie *pcie, u32 offset, in al_pcie_controller_writel() argument
150 writel_relaxed(val, pcie->controller_base + offset); in al_pcie_controller_writel()
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/linux/drivers/pci/controller/mobiveil/
H A Dpcie-mobiveil-host.c3 * PCIe host controller driver for Mobiveil PCIe Host controller
26 #include "pcie-mobiveil.h"
51 struct mobiveil_pcie *pcie = bus->sysdata; in mobiveil_pcie_map_bus() local
52 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_map_bus()
60 return pcie->csr_axi_slave_base + where; in mobiveil_pcie_map_bus()
72 mobiveil_csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0)); in mobiveil_pcie_map_bus()
86 struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc); in mobiveil_pcie_isr() local
87 struct device *dev = &pcie->pdev->dev; in mobiveil_pcie_isr()
88 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_isr()
103 val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT); in mobiveil_pcie_isr()
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H A Dpcie-mobiveil.c3 * PCIe host controller driver for Mobiveil PCIe Host controller
18 #include "pcie-mobiveil.h"
28 static void mobiveil_pcie_sel_page(struct mobiveil_pcie *pcie, u8 pg_idx) in mobiveil_pcie_sel_page() argument
32 val = readl(pcie->csr_axi_slave_base + PAB_CTRL); in mobiveil_pcie_sel_page()
36 writel(val, pcie->csr_axi_slave_base + PAB_CTRL); in mobiveil_pcie_sel_page()
39 static void __iomem *mobiveil_pcie_comp_addr(struct mobiveil_pcie *pcie, in mobiveil_pcie_comp_addr() argument
44 mobiveil_pcie_sel_page(pcie, 0); in mobiveil_pcie_comp_addr()
45 return pcie->csr_axi_slave_base + off; in mobiveil_pcie_comp_addr()
48 mobiveil_pcie_sel_page(pcie, OFFSET_TO_PAGE_IDX(off)); in mobiveil_pcie_comp_addr()
49 return pcie->csr_axi_slave_base + OFFSET_TO_PAGE_ADDR(off); in mobiveil_pcie_comp_addr()
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H A Dpcie-layerscape-gen4.c3 * PCIe Gen4 host controller driver for NXP Layerscape SoCs
23 #include "pcie-mobiveil.h"
45 static inline u32 ls_g4_pcie_pf_readl(struct ls_g4_pcie *pcie, u32 off) in ls_g4_pcie_pf_readl() argument
47 return ioread32(pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); in ls_g4_pcie_pf_readl()
50 static inline void ls_g4_pcie_pf_writel(struct ls_g4_pcie *pcie, in ls_g4_pcie_pf_writel() argument
53 iowrite32(val, pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); in ls_g4_pcie_pf_writel()
58 struct ls_g4_pcie *pcie = to_ls_g4_pcie(pci); in ls_g4_pcie_link_up() local
61 state = ls_g4_pcie_pf_readl(pcie, PCIE_PF_DBG); in ls_g4_pcie_link_up()
65 static void ls_g4_pcie_disable_interrupt(struct ls_g4_pcie *pcie) in ls_g4_pcie_disable_interrupt() argument
67 struct mobiveil_pcie *mv_pci = &pcie->pci; in ls_g4_pcie_disable_interrupt()
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H A Dpcie-mobiveil.h3 * PCIe host controller driver for Mobiveil PCIe Host controller
147 int (*interrupt_init)(struct mobiveil_pcie *pcie);
162 bool (*link_up)(struct mobiveil_pcie *pcie);
169 phys_addr_t pcie_reg_base; /* Physical PCIe Controller Base */
178 int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie);
179 int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit);
180 bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie);
181 int mobiveil_bringup_link(struct mobiveil_pcie *pcie);
182 void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
184 void program_ib_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
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/linux/drivers/pci/controller/cadence/
H A Dpcie-cadence-ep.c3 // Cadence PCIe endpoint controller driver.
15 #include "pcie-cadence.h"
22 static u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn) in cdns_pcie_get_fn_from_vfn() argument
30 cap = cdns_pcie_find_ext_capability(pcie, PCI_EXT_CAP_ID_SRIOV); in cdns_pcie_get_fn_from_vfn()
31 first_vf_offset = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_OFFSET); in cdns_pcie_get_fn_from_vfn()
32 stride = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_STRIDE); in cdns_pcie_get_fn_from_vfn()
42 struct cdns_pcie *pcie = &ep->pcie; in cdns_pcie_ep_write_header() local
46 cap = cdns_pcie_find_ext_capability(pcie, PCI_EXT_CAP_ID_SRIOV); in cdns_pcie_ep_write_header()
52 cdns_pcie_ep_fn_writew(pcie, fn, reg, hdr->deviceid); in cdns_pcie_ep_write_header()
56 cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid); in cdns_pcie_ep_write_header()
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/linux/Documentation/devicetree/bindings/pci/
H A Drcar-pci-host.yaml8 title: Renesas R-Car PCIe Host
20 - const: renesas,pcie-r8a7779 # R-Car H1
23 - renesas,pcie-r8a7742 # RZ/G1H
24 - renesas,pcie-r8a7743 # RZ/G1M
25 - renesas,pcie-r8a7744 # RZ/G1N
26 - renesas,pcie-r8a7790 # R-Car H2
27 - renesas,pcie-r8a7791 # R-Car M2-W
28 - renesas,pcie-r8a7793 # R-Car M2-N
29 - const: renesas,pcie-rcar-gen2 # R-Car Gen2 and RZ/G1
32 - renesas,pcie-r8a774a1 # RZ/G2M
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H A Dfsl,layerscape-pcie.yaml4 $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml#
7 title: Freescale Layerscape PCIe Root Complex(RC) controller
13 This PCIe RC controller is based on the Synopsys DesignWare PCIe IP
19 register available in the Freescale PCIe controller register set,
20 which can allow determining the underlying DesignWare PCIe controller version
27 - fsl,ls1012a-pcie
28 - fsl,ls1021a-pcie
29 - fsl,ls1028a-pcie
30 - fsl,ls1043a-pcie
31 - fsl,ls1046a-pcie
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H A Dti,j721e-pci-ep.yaml8 title: TI J721E PCI EP (PCIe Wrapper)
16 - const: ti,j721e-pcie-ep
17 - const: ti,j784s4-pcie-ep
18 - description: PCIe EP controller in AM64
20 - const: ti,am64-pcie-ep
21 - const: ti,j721e-pcie-ep
22 - description: PCIe EP controller in J7200
24 - const: ti,j7200-pcie-ep
25 - const: ti,j721e-pcie-ep
37 ti,syscon-pcie-ctrl:
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H A Daxis,artpec6-pcie.yaml5 $id: http://devicetree.org/schemas/pci/axis,artpec6-pcie.yaml#
8 title: Axis ARTPEC-6 PCIe host controller
14 This PCIe host controller is based on the Synopsys DesignWare PCIe IP.
21 - axis,artpec6-pcie
22 - axis,artpec6-pcie-ep
23 - axis,artpec7-pcie
24 - axis,artpec7-pcie-ep
32 - axis,artpec6-pcie
33 - axis,artpec6-pcie-ep
34 - axis,artpec7-pcie
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H A Dnvidia,tegra20-pcie.txt1 NVIDIA Tegra PCIe controller
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
11 contain BPMP phandle and PCIe power partition ID. This is required only
71 - "default": active state, puts PCIe I/O out of deep power down state
72 - "idle": puts PCIe I/O into deep power down state
79 - pcie
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H A Dbrcm,stb-pcie.yaml4 $id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml#
7 title: Brcmstb PCIe Host Controller
16 - brcm,bcm2711-pcie # The Raspberry Pi 4
17 - brcm,bcm2712-pcie # Raspberry Pi 5
18 - brcm,bcm4908-pcie
19 - brcm,bcm7211-pcie # Broadcom STB version of RPi4
20 - brcm,bcm7216-pcie # Broadcom 7216 Arm
21 - brcm,bcm7278-pcie # Broadcom 7278 Arm
22 - brcm,bcm7425-pcie # Broadcom 7425 MIPs
23 - brcm,bcm7435-pcie # Broadcom 7435 MIPs
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/linux/arch/powerpc/sysdev/
H A Dfsl_pci.h19 #define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
22 #define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */
23 #define PCIE_IP_REV_3_0 0x02080300 /* PCIE IP block version Rev3.0 */
60 __be32 config_addr; /* 0x.000 - PCI/PCIE Configuration Address Register */
61 __be32 config_data; /* 0x.004 - PCI/PCIE Configuration Data Register */
63 __be32 pex_otb_cpl_tor; /* 0x.00c - PCIE Outbound completion timeout register */
64 __be32 pex_conf_tor; /* 0x.010 - PCIE configuration timeout register */
65 __be32 pex_config; /* 0x.014 - PCIE CONFIG Register */
66 __be32 pex_int_status; /* 0x.018 - PCIE interrupt status */
68 __be32 pex_pme_mes_dr; /* 0x.020 - PCIE PME and message detect register */
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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/pci/
H A Dpcie.c53 if (!pci->func->pcie.version) in nvkm_pcie_get_version()
56 return pci->func->pcie.version(pci); in nvkm_pcie_get_version()
62 if (!pci->func->pcie.version_supported) in nvkm_pcie_get_max_version()
65 return pci->func->pcie.version_supported(pci); in nvkm_pcie_get_max_version()
71 if (!pci->func->pcie.set_version) in nvkm_pcie_set_version()
75 pci->func->pcie.set_version(pci, version); in nvkm_pcie_set_version()
82 if (pci->func->pcie.max_speed) in nvkm_pcie_oneinit()
83 nvkm_debug(&pci->subdev, "pcie max speed: %s\n", in nvkm_pcie_oneinit()
84 nvkm_pcie_speeds[pci->func->pcie.max_speed(pci)]); in nvkm_pcie_oneinit()
94 /* raise pcie version first */ in nvkm_pcie_init()
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