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/linux/drivers/pci/controller/dwc/
H A D	pcie-tegra194.c	3 * PCIe host controller driver for the following SoCs 33 #include "pcie-designware.h" 292 static inline void appl_writel(struct tegra_pcie_dw pcie, const u32 value, 295 writel_relaxed(value, pcie->appl_base + reg); in appl_writel() 298 static inline u32 appl_readl(struct tegra_pcie_dw pcie, const u32 reg) 300 return readl_relaxed(pcie->appl_base + reg); in appl_readl() 303 static void tegra_pcie_icc_set(struct tegra_pcie_dw pcie) 305 struct dw_pcie pci = &pcie->pci; in tegra_pcie_icc_set() 308 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in tegra_pcie_icc_set() 315 if (icc_set_bw(pcie in tegra_pcie_icc_set() 293 appl_writel(struct tegra_pcie_dw * pcie,const u32 value,const u32 reg) appl_writel() argument 299 appl_readl(struct tegra_pcie_dw * pcie,const u32 reg) appl_readl() argument 304 tegra_pcie_icc_set(struct tegra_pcie_dw * pcie) tegra_pcie_icc_set() argument 328 struct tegra_pcie_dw pcie = to_tegra_pcie(pci); apply_bad_link_workaround() local 360 struct tegra_pcie_dw pcie = arg; tegra_pcie_rp_irq_handler() local 436 pex_ep_event_hot_rst_done(struct tegra_pcie_dw * pcie) pex_ep_event_hot_rst_done() argument 464 struct tegra_pcie_dw pcie = arg; tegra_pcie_ep_irq_thread() local 519 struct tegra_pcie_dw pcie = arg; tegra_pcie_ep_hard_irq() local 567 struct tegra_pcie_dw pcie = to_tegra_pcie(pci); tegra_pcie_dw_rd_own_conf() local 589 struct tegra_pcie_dw pcie = to_tegra_pcie(pci); tegra_pcie_dw_wr_own_conf() local 611 disable_aspm_l11(struct tegra_pcie_dw * pcie) disable_aspm_l11() argument 620 disable_aspm_l12(struct tegra_pcie_dw * pcie) disable_aspm_l12() argument 629 event_counter_prog(struct tegra_pcie_dw * pcie,u32 event) event_counter_prog() argument 649 struct tegra_pcie_dw pcie = (struct tegra_pcie_dw ) aspm_state_cnt() local 682 init_host_aspm(struct tegra_pcie_dw * pcie) init_host_aspm() argument 714 init_debugfs(struct tegra_pcie_dw * pcie) init_debugfs() argument 729 disable_aspm_l12(struct tegra_pcie_dw * pcie) disable_aspm_l12() argument 730 disable_aspm_l11(struct tegra_pcie_dw * pcie) disable_aspm_l11() argument 731 init_host_aspm(struct tegra_pcie_dw * pcie) init_host_aspm() argument 732 init_debugfs(struct tegra_pcie_dw * pcie) init_debugfs() argument 738 struct tegra_pcie_dw pcie = to_tegra_pcie(pci); tegra_pcie_enable_system_interrupts() local 777 struct tegra_pcie_dw pcie = to_tegra_pcie(pci); tegra_pcie_enable_intx_interrupts() local 798 struct tegra_pcie_dw pcie = to_tegra_pcie(pci); tegra_pcie_enable_msi_interrupts() local 811 struct tegra_pcie_dw pcie = to_tegra_pcie(pci); tegra_pcie_enable_interrupts() local 836 config_gen3_gen4_eq_presets(struct tegra_pcie_dw * pcie) config_gen3_gen4_eq_presets() argument 893 struct tegra_pcie_dw pcie = to_tegra_pcie(pci); tegra_pcie_dw_host_init() local 959 struct tegra_pcie_dw pcie = to_tegra_pcie(pci); tegra_pcie_dw_start_link() local 1041 struct tegra_pcie_dw pcie = to_tegra_pcie(pci); tegra_pcie_dw_link_up() local 1049 struct tegra_pcie_dw pcie = to_tegra_pcie(pci); tegra_pcie_dw_stop_link() local 1064 tegra_pcie_disable_phy(struct tegra_pcie_dw * pcie) tegra_pcie_disable_phy() argument 1074 tegra_pcie_enable_phy(struct tegra_pcie_dw * pcie) tegra_pcie_enable_phy() argument 1101 tegra_pcie_dw_parse_dt(struct tegra_pcie_dw * pcie) tegra_pcie_dw_parse_dt() argument 1211 tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw * pcie,bool enable) tegra_pcie_bpmp_set_ctrl_state() argument 1249 tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw * pcie,bool enable) tegra_pcie_bpmp_set_pll_state() argument 1284 tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw * pcie) tegra_pcie_downstream_dev_to_D0() argument 1322 tegra_pcie_get_slot_regulators(struct tegra_pcie_dw * pcie) tegra_pcie_get_slot_regulators() argument 1343 tegra_pcie_enable_slot_regulators(struct tegra_pcie_dw * pcie) tegra_pcie_enable_slot_regulators() argument 1381 tegra_pcie_disable_slot_regulators(struct tegra_pcie_dw * pcie) tegra_pcie_disable_slot_regulators() argument 1389 tegra_pcie_config_controller(struct tegra_pcie_dw * pcie,bool en_hw_hot_rst) tegra_pcie_config_controller() argument 1512 tegra_pcie_unconfig_controller(struct tegra_pcie_dw * pcie) tegra_pcie_unconfig_controller() argument 1546 tegra_pcie_init_controller(struct tegra_pcie_dw * pcie) tegra_pcie_init_controller() argument 1571 tegra_pcie_try_link_l2(struct tegra_pcie_dw * pcie) tegra_pcie_try_link_l2() argument 1587 tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw * pcie) tegra_pcie_dw_pme_turnoff() argument 1649 tegra_pcie_deinit_controller(struct tegra_pcie_dw * pcie) tegra_pcie_deinit_controller() argument 1657 tegra_pcie_config_rp(struct tegra_pcie_dw * pcie) tegra_pcie_config_rp() argument 1701 pex_ep_event_pex_rst_assert(struct tegra_pcie_dw * pcie) pex_ep_event_pex_rst_assert() argument 1747 pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw * pcie) pex_ep_event_pex_rst_deassert() argument 1948 struct tegra_pcie_dw pcie = arg; tegra_pcie_ep_pex_rst_irq() local 1967 tegra_pcie_ep_raise_intx_irq(struct tegra_pcie_dw pcie,u16 irq) tegra_pcie_ep_raise_intx_irq() argument 1979 tegra_pcie_ep_raise_msi_irq(struct tegra_pcie_dw * pcie,u16 irq) tegra_pcie_ep_raise_msi_irq() argument 1989 tegra_pcie_ep_raise_msix_irq(struct tegra_pcie_dw * pcie,u16 irq) tegra_pcie_ep_raise_msix_irq() argument 2002 struct tegra_pcie_dw pcie = to_tegra_pcie(pci); tegra_pcie_ep_raise_irq() local 2047 tegra_pcie_config_ep(struct tegra_pcie_dw pcie,struct platform_device * pdev) tegra_pcie_config_ep() argument 2114 struct tegra_pcie_dw pcie; tegra_pcie_dw_probe() local 2310 struct tegra_pcie_dw pcie = platform_get_drvdata(pdev); tegra_pcie_dw_remove() local 2332 struct tegra_pcie_dw pcie = dev_get_drvdata(dev); tegra_pcie_dw_suspend_late() local 2357 struct tegra_pcie_dw pcie = dev_get_drvdata(dev); tegra_pcie_dw_suspend_noirq() local 2371 struct tegra_pcie_dw pcie = dev_get_drvdata(dev); tegra_pcie_dw_resume_noirq() local 2402 struct tegra_pcie_dw pcie = dev_get_drvdata(dev); tegra_pcie_dw_resume_early() local 2429 struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev); tegra_pcie_dw_shutdown() local [all...]
H A D	Kconfig	3 menu "DesignWare-based PCIe controllers" 10 bool "DesignWare PCIe debugfs entries" 14 Say Y here to enable debugfs entries for the PCIe controller. These 30 bool "Amazon Annapurna Labs PCIe controller" 36 Say Y here to enable support of the Amazon's Annapurna Labs PCIe 37 controller IP on Amazon SoCs. The PCIe controller uses the DesignWare 40 Annapurna Labs PCIe controller don't need to enable this. 43 bool "AMD MDB Versal2 PCIe controller" 48 Say Y here if you want to enable PCIe controller support on AMD 49 Versal2 SoCs. The AMD MDB Versal2 PCIe controlle [all...]
H A D	pcie-qcom.c	`3 * Qualcomm PCIe root complex driver 30 #include <linux/phy/pcie.h> 40 #include "pcie-designware.h" 41 #include "pcie-qcom-common.h" 247 int (get_resources)(struct qcom_pcie pcie); 248 int (init)(struct qcom_pcie pcie); 249 int (post_init)(struct qcom_pcie pcie); 250 void (host_post_init)(struct qcom_pcie pcie); 251 void (deinit)(struct qcom_pcie pcie); 252 void (ltssm_enable)(struct qcom_pcie pcie); [all …]`
H A D	pcie-visconti.c	3 * DWC PCIe RC driver for Toshiba Visconti ARM SoC 24 #include "pcie-designware.h" 96 /* Access registers in PCIe ulreg / 97 static void visconti_ulreg_writel(struct visconti_pcie pcie, u32 val, u32 reg) in visconti_ulreg_writel() argument 99 writel_relaxed(val, pcie->ulreg_base + reg); in visconti_ulreg_writel() 102 static u32 visconti_ulreg_readl(struct visconti_pcie pcie, u32 reg) in visconti_ulreg_readl() argument 104 return readl_relaxed(pcie->ulreg_base + reg); in visconti_ulreg_readl() 107 / Access registers in PCIe smu / 108 static void visconti_smu_writel(struct visconti_pcie pcie, u32 val, u32 reg) in visconti_smu_writel() argument 110 writel_relaxed(val, pcie->smu_base + reg); in visconti_smu_writel() [all …]
H A D	pcie-uniphier.c	3 * PCIe host controller driver for UniPhier SoCs 23 #include "pcie-designware.h" 75 static void uniphier_pcie_ltssm_enable(struct uniphier_pcie pcie, in uniphier_pcie_ltssm_enable() argument 80 val = readl(pcie->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable() 85 writel(val, pcie->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable() 88 static void uniphier_pcie_init_rc(struct uniphier_pcie pcie) in uniphier_pcie_init_rc() argument 93 val = readl(pcie->base + PCL_MODE); in uniphier_pcie_init_rc() 96 writel(val, pcie->base + PCL_MODE); in uniphier_pcie_init_rc() 99 val = readl(pcie->base + PCL_APP_PM0); in uniphier_pcie_init_rc() 101 writel(val, pcie->base + PCL_APP_PM0); in uniphier_pcie_init_rc() [all …]
H A D	pcie-amd-mdb.c	3 * PCIe host controller driver for AMD MDB PCIe Bridge 22 #include "pcie-designware.h" 55 * struct amd_mdb_pcie - PCIe port information 56 * @pci: DesignWare PCIe controller structure 77 struct amd_mdb_pcie pcie = irq_data_get_irq_chip_data(data); in amd_mdb_intx_irq_mask() local 78 struct dw_pcie pci = &pcie->pci; in amd_mdb_intx_irq_mask() 91 writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_DISABLE_MISC); in amd_mdb_intx_irq_mask() 97 struct amd_mdb_pcie pcie = irq_data_get_irq_chip_data(data); in amd_mdb_intx_irq_unmask() local 98 struct dw_pcie pci = &pcie->pci; in amd_mdb_intx_irq_unmask() 111 writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_ENABLE_MISC); in amd_mdb_intx_irq_unmask() [all …]
H A D	pcie-keembay.c	3 * PCIe controller driver for Intel Keem Bay 22 #include "pcie-designware.h" 72 static void keembay_ep_reset_assert(struct keembay_pcie pcie) in keembay_ep_reset_assert() argument 74 gpiod_set_value_cansleep(pcie->reset, 1); in keembay_ep_reset_assert() 78 static void keembay_ep_reset_deassert(struct keembay_pcie pcie) in keembay_ep_reset_deassert() argument 88 gpiod_set_value_cansleep(pcie->reset, 0); in keembay_ep_reset_deassert() 92 static void keembay_pcie_ltssm_set(struct keembay_pcie pcie, bool enable) in keembay_pcie_ltssm_set() argument 96 val = readl(pcie->apb_base + PCIE_REGS_PCIE_APP_CNTRL); in keembay_pcie_ltssm_set() 101 writel(val, pcie->apb_base + PCIE_REGS_PCIE_APP_CNTRL); in keembay_pcie_ltssm_set() 106 struct keembay_pcie pcie = dev_get_drvdata(pci->dev); in keembay_pcie_link_up() local [all …]
/linux/drivers/pci/controller/
H A D	pcie-altera.c	6 * Description: Altera PCIe host controller driver 45 #define S10_RP_CFG_ADDR(pcie, reg) \ argument 46 (((pcie)->hip_base) + (reg) + (1 << 20)) 47 #define S10_RP_SECONDARY(pcie) \ argument 48 readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS)) 59 #define TLP_CFG_DW0(pcie, cfg) \ argument 62 #define TLP_CFG_DW1(pcie, tag, be) \ argument 63 (((PCI_DEVID(pcie->root_bus_nr, RP_DEVFN)) << 16) \| (tag << 8) \| (be)) 81 #define AGLX_RP_CFG_ADDR(pcie, reg) (((pcie)->hip_base) + (reg)) argument 82 #define AGLX_RP_SECONDARY(pcie) \ argument [all …]
H A D	pcie-xilinx-nwl.c	3 * PCIe host controller driver for NWL PCIe Bridge 4 * Based on pcie-xilinx.c, pci-tegra.c 163 phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base / 176 static inline u32 nwl_bridge_readl(struct nwl_pcie pcie, u32 off) in nwl_bridge_readl() argument 178 return readl(pcie->breg_base + off); in nwl_bridge_readl() 181 static inline void nwl_bridge_writel(struct nwl_pcie pcie, u32 val, u32 off) in nwl_bridge_writel() argument 183 writel(val, pcie->breg_base + off); in nwl_bridge_writel() 186 static bool nwl_pcie_link_up(struct nwl_pcie pcie) in nwl_pcie_link_up() argument 188 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT) in nwl_pcie_link_up() 193 static bool nwl_phy_link_up(struct nwl_pcie *pcie) in nwl_phy_link_up() argument [all …]
H A D	pci-aardvark.c	3 * Driver for the Aardvark PCIe controller, used on Marvell Armada 32 /* PCIe core registers / 125 / PCIe window configuration / 216 / PCIe core controller registers / 224 / PCIe Central Interrupts Registers / 292 static inline void advk_writel(struct advk_pcie pcie, u32 val, u64 reg) in advk_writel() argument 294 writel(val, pcie->base + reg); in advk_writel() 297 static inline u32 advk_readl(struct advk_pcie pcie, u64 reg) in advk_readl() argument 299 return readl(pcie->base + reg); in advk_readl() 302 static u8 advk_pcie_ltssm_state(struct advk_pcie pcie) in advk_pcie_ltssm_state() argument [all …]
H A D	pcie-mediatek-gen3.c	`3 * MediaTek PCIe host controller driver. 136 /* Time in ms needed to complete PCIe reset on EN7581 SoC / 153 @power_up: pcie power_up callback 156 * @flags: pcie device flags. 159 int (power_up)(struct mtk_gen3_pcie pcie); 181 * struct mtk_gen3_pcie - PCIe port information 182 * @dev: pointer to PCIe device 188 * @clks: PCIe clocks 189 * @num_clks: PCIe clocks count for this port 190 * @max_link_speed: Maximum link speed (PCIe Gen) for this port [all …]`
H A D	pci-tegra.c	3 * PCIe host controller driver for Tegra SoCs 8 * Based on NVIDIA PCIe driver 11 * Bits taken from arch/arm/mach-dove/pcie.c 259 * entries, one entry per PCIe port. These field definitions and desired 364 struct tegra_pcie pcie; member 377 static inline void afi_writel(struct tegra_pcie pcie, u32 value, in afi_writel() argument 380 writel(value, pcie->afi + offset); in afi_writel() 383 static inline u32 afi_readl(struct tegra_pcie pcie, unsigned long offset) in afi_readl() argument 385 return readl(pcie->afi + offset); in afi_readl() 388 static inline void pads_writel(struct tegra_pcie pcie, u32 value, in pads_writel() argument [all …]
H A D	pcie-brcmstb.c	46 /* Broadcom STB PCIe Register Offsets / 202 / PCIe parameters / argument 237 #define IDX_ADDR(pcie) ((pcie)->cfg->offsets[EXT_CFG_INDEX]) 238 #define DATA_ADDR(pcie) ((pcie)->cfg->offsets[EXT_CFG_DATA]) 239 #define PCIE_RGR1_SW_INIT_1(pcie) ((pcie)->cfg->offsets[RGR1_SW_INIT_1]) 240 #define HARD_DEBUG(pcie) ((pcie) 201 IDX_ADDR(pcie) global() argument 203 PCIE_RGR1_SW_INIT_1(pcie) global() argument 204 HARD_DEBUG(pcie) global() argument 205 INTR2_CPU_BASE(pcie) global() argument 308 is_bmips(const struct brcm_pcie pcie) is_bmips() argument 380 brcm_pcie_set_ssc(struct brcm_pcie * pcie) brcm_pcie_set_ssc() argument 416 brcm_pcie_set_gen(struct brcm_pcie * pcie,int gen) brcm_pcie_set_gen() argument 428 brcm_pcie_set_outbound_win(struct brcm_pcie * pcie,u8 win,u64 cpu_addr,u64 pcie_addr,u64 size) brcm_pcie_set_outbound_win() argument 614 brcm_msi_remove(struct brcm_pcie * pcie) brcm_msi_remove() argument 645 brcm_pcie_enable_msi(struct brcm_pcie * pcie) brcm_pcie_enable_msi() argument 698 brcm_pcie_rc_mode(struct brcm_pcie * pcie) brcm_pcie_rc_mode() argument 706 brcm_pcie_link_up(struct brcm_pcie * pcie) brcm_pcie_link_up() argument 718 struct brcm_pcie pcie = bus->sysdata; brcm_pcie_map_bus() local 739 struct brcm_pcie pcie = bus->sysdata; brcm7425_pcie_map_bus() local 757 brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie * pcie,u32 val) brcm_pcie_bridge_sw_init_set_generic() argument 783 brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie * pcie,u32 val) brcm_pcie_bridge_sw_init_set_7278() argument 795 brcm_pcie_perst_set_4908(struct brcm_pcie * pcie,u32 val) brcm_pcie_perst_set_4908() argument 813 brcm_pcie_perst_set_7278(struct brcm_pcie * pcie,u32 val) brcm_pcie_perst_set_7278() argument 825 brcm_pcie_perst_set_generic(struct brcm_pcie * pcie,u32 val) brcm_pcie_perst_set_generic() argument 836 brcm_pcie_post_setup_bcm2712(struct brcm_pcie * pcie) brcm_pcie_post_setup_bcm2712() argument 878 brcm_pcie_get_inbound_wins(struct brcm_pcie * pcie,struct inbound_win inbound_wins[]) brcm_pcie_get_inbound_wins() argument 1032 set_inbound_win_registers(struct brcm_pcie * pcie,const struct inbound_win * inbound_wins,u8 num_inbound_wins) set_inbound_win_registers() argument 1072 brcm_pcie_setup(struct brcm_pcie * pcie) brcm_pcie_setup() argument 1267 brcm_extend_rbus_timeout(struct brcm_pcie * pcie) brcm_extend_rbus_timeout() argument 1281 brcm_config_clkreq(struct brcm_pcie * pcie) brcm_config_clkreq() argument 1343 brcm_pcie_start_link(struct brcm_pcie * pcie) brcm_pcie_start_link() argument 1420 struct brcm_pcie pcie = bus->sysdata; brcm_pcie_add_bus() local 1459 struct brcm_pcie pcie = bus->sysdata; brcm_pcie_remove_bus() local 1473 brcm_pcie_enter_l23(struct brcm_pcie * pcie) brcm_pcie_enter_l23() argument 1498 brcm_phy_cntl(struct brcm_pcie * pcie,const int start) brcm_phy_cntl() argument 1534 brcm_phy_start(struct brcm_pcie * pcie) brcm_phy_start() argument 1539 brcm_phy_stop(struct brcm_pcie * pcie) brcm_phy_stop() argument 1544 brcm_pcie_turn_off(struct brcm_pcie * pcie) brcm_pcie_turn_off() argument 1586 struct brcm_pcie pcie = dev_get_drvdata(dev); brcm_pcie_suspend_noirq() local 1637 struct brcm_pcie pcie = dev_get_drvdata(dev); brcm_pcie_resume_noirq() local 1710 __brcm_pcie_remove(struct brcm_pcie * pcie) __brcm_pcie_remove() argument 1723 struct brcm_pcie pcie = platform_get_drvdata(pdev); brcm_pcie_remove() local 1873 struct brcm_pcie pcie; brcm_pcie_probe() local [all...]
H A D	pcie-rcar-host.c	3 * PCIe driver for Renesas R-Car SoCs 7 * arch/sh/drivers/pci/pcie-sh7786.c 36 #include "pcie-rcar.h" 47 /* Structure representing the PCIe interface / 49 struct rcar_pcie pcie; member 67 Test if the PCIe controller received PM_ENTER_L1 DLLP and in rcar_pcie_wakeup() 68 * the PCIe controller is not in L1 link state. If true, apply in rcar_pcie_wakeup() 92 static u32 rcar_read_conf(struct rcar_pcie pcie, int where) in rcar_read_conf() argument 95 u32 val = rcar_pci_read_reg(pcie, where & ~3); in rcar_read_conf() 117 static int rcar_pci_write_reg_workaround(struct rcar_pcie pcie, u32 val, in rcar_pci_write_reg_workaround() argument [all …]
H A D	pcie-xilinx.c	3 * PCIe host controller driver for Xilinx AXI PCIe Bridge 7 * Based on the Tegra PCIe driver 95 * struct xilinx_pcie - PCIe port information 114 static inline u32 pcie_read(struct xilinx_pcie pcie, u32 reg) in pcie_read() argument 116 return readl(pcie->reg_base + reg); in pcie_read() 119 static inline void pcie_write(struct xilinx_pcie pcie, u32 val, u32 reg) in pcie_write() argument 121 writel(val, pcie->reg_base + reg); in pcie_write() 124 static inline bool xilinx_pcie_link_up(struct xilinx_pcie pcie) in xilinx_pcie_link_up() argument 126 return (pcie_read(pcie, XILINX_PCIE_REG_PSCR) & in xilinx_pcie_link_up() 132 @pcie: PCIe port information [all …]
H A D	Kconfig	11 tristate "Aardvark PCIe controller" 18 Add support for Aardvark 64bit PCIe Host Controller. This 23 tristate "Altera PCIe controller" 26 Say Y here if you want to enable PCIe controller support on Altera 30 tristate "Altera PCIe MSI feature" 35 Say Y here if you want PCIe MSI support for the Altera FPGA. 44 tristate "Apple PCIe controller" 51 Say Y here if you want to enable PCIe controller support on Apple 62 tristate "Broadcom Brcmstb PCIe controller" 70 Say Y here to enable PCIe hos [all...]
/linux/drivers/pci/controller/plda/
H A D	pcie-starfive.c	3 * PCIe host controller driver for StarFive JH7110 Soc. 27 #include "pcie-plda.h" 67 * JH7110 PCIe port BAR0/1 can be configured as 64-bit prefetchable memory 68 * space. PCIe read and write requests targeting BAR0/1 are routed to so called 105 static int starfive_pcie_parse_dt(struct starfive_jh7110_pcie *pcie, in starfive_pcie_parse_dt() argument 110 pcie->num_clks = devm_clk_bulk_get_all(dev, &pcie->clks); in starfive_pcie_parse_dt() 111 if (pcie->num_clks < 0) in starfive_pcie_parse_dt() 112 return dev_err_probe(dev, pcie->num_clks, in starfive_pcie_parse_dt() 113 "failed to get pcie clocks\n"); in starfive_pcie_parse_dt() 115 pcie->resets = devm_reset_control_array_get_exclusive(dev); in starfive_pcie_parse_dt() [all …]
/linux/Documentation/devicetree/bindings/phy/
H A D	qcom,sc8280xp-qmp-pcie-phy.yaml	`4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml# 7 title: Qualcomm QMP PHY controller (PCIe, SC8280XP) 14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. 19 - qcom,qcs615-qmp-gen3x1-pcie-phy 20 - qcom,qcs8300-qmp-gen4x2-pcie-phy 21 - qcom,sa8775p-qmp-gen4x2-pcie-phy 22 - qcom,sa8775p-qmp-gen4x4-pcie-phy 23 - qcom,sar2130p-qmp-gen3x2-pcie-phy 24 - qcom,sc8180x-qmp-pcie-phy 25 - qcom,sc8280xp-qmp-gen3x1-pcie-phy [all …]`
/linux/drivers/pci/controller/mobiveil/
H A D	pcie-mobiveil-host.c	3 * PCIe host controller driver for Mobiveil PCIe Host controller 26 #include "pcie-mobiveil.h" 51 struct mobiveil_pcie pcie = bus->sysdata; in mobiveil_pcie_map_bus() local 52 struct mobiveil_root_port rp = &pcie->rp; in mobiveil_pcie_map_bus() 60 return pcie->csr_axi_slave_base + where; in mobiveil_pcie_map_bus() 72 mobiveil_csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0)); in mobiveil_pcie_map_bus() 86 struct mobiveil_pcie pcie = irq_desc_get_handler_data(desc); in mobiveil_pcie_isr() local 87 struct device dev = &pcie->pdev->dev; in mobiveil_pcie_isr() 88 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_isr() 103 val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT); in mobiveil_pcie_isr() [all …]
H A D	pcie-mobiveil.c	3 * PCIe host controller driver for Mobiveil PCIe Host controller 18 #include "pcie-mobiveil.h" 28 static void mobiveil_pcie_sel_page(struct mobiveil_pcie pcie, u8 pg_idx) in mobiveil_pcie_sel_page() argument 32 val = readl(pcie->csr_axi_slave_base + PAB_CTRL); in mobiveil_pcie_sel_page() 36 writel(val, pcie->csr_axi_slave_base + PAB_CTRL); in mobiveil_pcie_sel_page() 39 static void __iomem mobiveil_pcie_comp_addr(struct mobiveil_pcie *pcie, in mobiveil_pcie_comp_addr() argument 44 mobiveil_pcie_sel_page(pcie, 0); in mobiveil_pcie_comp_addr() 45 return pcie->csr_axi_slave_base + off; in mobiveil_pcie_comp_addr() 48 mobiveil_pcie_sel_page(pcie, OFFSET_TO_PAGE_IDX(off)); in mobiveil_pcie_comp_addr() 49 return pcie->csr_axi_slave_base + OFFSET_TO_PAGE_ADDR(off); in mobiveil_pcie_comp_addr() [all …]
H A D	pcie-layerscape-gen4.c	3 * PCIe Gen4 host controller driver for NXP Layerscape SoCs 23 #include "pcie-mobiveil.h" 45 static inline u32 ls_g4_pcie_pf_readl(struct ls_g4_pcie pcie, u32 off) in ls_g4_pcie_pf_readl() argument 47 return ioread32(pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); in ls_g4_pcie_pf_readl() 50 static inline void ls_g4_pcie_pf_writel(struct ls_g4_pcie pcie, in ls_g4_pcie_pf_writel() argument 53 iowrite32(val, pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); in ls_g4_pcie_pf_writel() 58 struct ls_g4_pcie pcie = to_ls_g4_pcie(pci); in ls_g4_pcie_link_up() local 61 state = ls_g4_pcie_pf_readl(pcie, PCIE_PF_DBG); in ls_g4_pcie_link_up() 65 static void ls_g4_pcie_disable_interrupt(struct ls_g4_pcie pcie) in ls_g4_pcie_disable_interrupt() argument 67 struct mobiveil_pcie *mv_pci = &pcie->pci; in ls_g4_pcie_disable_interrupt() [all …]
/linux/drivers/pci/controller/cadence/
H A D	pcie-cadence.c	3 // Cadence PCIe controller driver. 10 #include "pcie-cadence.h" 13 u8 cdns_pcie_find_capability(struct cdns_pcie pcie, u8 cap) in cdns_pcie_find_capability() argument 16 cap, pcie); in cdns_pcie_find_capability() 20 u16 cdns_pcie_find_ext_capability(struct cdns_pcie pcie, u8 cap) in cdns_pcie_find_ext_capability() argument 22 return PCI_FIND_NEXT_EXT_CAP(cdns_pcie_read_cfg, 0, cap, pcie); in cdns_pcie_find_ext_capability() 26 bool cdns_pcie_linkup(struct cdns_pcie pcie) in cdns_pcie_detect_quiet_min_delay_set() argument 30 pl_reg_val = cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE); in cdns_pcie_detect_quiet_min_delay_set() 37 void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie pcie) in cdns_pcie_detect_quiet_min_delay_set() 45 ltssm_control_cap = cdns_pcie_readl(pcie, CDNS_PCIE_LTSSM_CONTROL_CA in cdns_pcie_set_outbound_region() 43 cdns_pcie_set_outbound_region(struct cdns_pcie * pcie,u8 busnr,u8 fn,u32 r,bool is_io,u64 cpu_addr,u64 pci_addr,size_t size) cdns_pcie_set_outbound_region() argument 121 cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie * pcie,u8 busnr,u8 fn,u32 r,u64 cpu_addr) cdns_pcie_set_outbound_region_for_normal_msg() argument 156 cdns_pcie_reset_outbound_region(struct cdns_pcie * pcie,u32 r) cdns_pcie_reset_outbound_region() argument 169 cdns_pcie_disable_phy(struct cdns_pcie * pcie) cdns_pcie_disable_phy() argument 180 cdns_pcie_enable_phy(struct cdns_pcie * pcie) cdns_pcie_enable_phy() argument 209 cdns_pcie_init_phy(struct device * dev,struct cdns_pcie * pcie) cdns_pcie_init_phy() argument 271 struct cdns_pcie pcie = dev_get_drvdata(dev); cdns_pcie_suspend_noirq() local 280 struct cdns_pcie pcie = dev_get_drvdata(dev); cdns_pcie_resume_noirq() local [all...]
H A D	pci-j721e.c	3 * pci-j721e - PCIe controller driver for TI's J721E SoCs 26 #include "pcie-cadence.h" 28 #define cdns_pcie_to_rc(p) container_of(p, struct cdns_pcie_rc, pcie) 83 static inline u32 j721e_pcie_user_readl(struct j721e_pcie pcie, u32 offset) in j721e_pcie_user_readl() argument 85 return readl(pcie->user_cfg_base + offset); in j721e_pcie_user_readl() 88 static inline void j721e_pcie_user_writel(struct j721e_pcie pcie, u32 offset, in j721e_pcie_user_writel() argument 91 writel(value, pcie->user_cfg_base + offset); in j721e_pcie_user_writel() 94 static inline u32 j721e_pcie_intd_readl(struct j721e_pcie pcie, u32 offset) in j721e_pcie_intd_readl() argument 96 return readl(pcie->intd_cfg_base + offset); in j721e_pcie_intd_readl() 99 static inline void j721e_pcie_intd_writel(struct j721e_pcie pcie, u3 argument 107 struct j721e_pcie pcie = priv; j721e_pcie_link_irq_handler() local 121 j721e_pcie_disable_link_irq(struct j721e_pcie pcie) j721e_pcie_disable_link_irq() argument 130 j721e_pcie_config_link_irq(struct j721e_pcie * pcie) j721e_pcie_config_link_irq() argument 141 struct j721e_pcie pcie = dev_get_drvdata(cdns_pcie->dev); j721e_pcie_start_link() local 153 struct j721e_pcie pcie = dev_get_drvdata(cdns_pcie->dev); j721e_pcie_stop_link() local 163 struct j721e_pcie pcie = dev_get_drvdata(cdns_pcie->dev); j721e_pcie_link_up() local 176 j721e_pcie_set_mode(struct j721e_pcie pcie,struct regmap * syscon,unsigned int offset) j721e_pcie_set_mode() argument 195 j721e_pcie_set_link_speed(struct j721e_pcie * pcie,struct regmap * syscon,unsigned int offset) j721e_pcie_set_link_speed() argument 216 j721e_pcie_set_lane_count(struct j721e_pcie * pcie,struct regmap * syscon,unsigned int offset) j721e_pcie_set_lane_count() argument 236 j721e_enable_acspcie_refclk(struct j721e_pcie * pcie,struct regmap * syscon) j721e_enable_acspcie_refclk() argument 266 j721e_pcie_ctrl_init(struct j721e_pcie * pcie) j721e_pcie_ctrl_init() argument 477 struct j721e_pcie pcie; j721e_pcie_probe() local 666 struct j721e_pcie pcie = platform_get_drvdata(pdev); j721e_pcie_remove() local 691 struct j721e_pcie pcie = dev_get_drvdata(dev); j721e_pcie_suspend_noirq() local 705 struct j721e_pcie pcie = dev_get_drvdata(dev); j721e_pcie_resume_noirq() local [all...]
H A D	pcie-cadence-host.c	3 // Cadence PCIe host controller driver. 14 #include "pcie-cadence.h" 15 #include "pcie-cadence-host-common.h" 27 struct cdns_pcie pcie = &rc->pcie; 40 return pcie->reg_base + (where & 0xfff); in cdns_pci_map_bus() 43 if (!(cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE) & 0x1)) in cdns_pci_map_bus() 46 cdns_pcie_writel(pcie, CDNS_PCIE_AT_LINKDOWN, 0x0); in cdns_pci_map_bus() 52 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(0), addr0); in cdns_pci_map_bus() 65 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC in cdns_pci_map_bus() 34 struct cdns_pcie pcie = &rc->pcie; cdns_pci_map_bus() local 84 cdns_pcie_host_training_complete(struct cdns_pcie * pcie) cdns_pcie_host_training_complete() argument 105 cdns_pcie_host_wait_for_link(struct cdns_pcie * pcie) cdns_pcie_host_wait_for_link() argument 122 cdns_pcie_retrain(struct cdns_pcie * pcie) cdns_pcie_retrain() argument 155 cdns_pcie_host_disable_ptm_response(struct cdns_pcie * pcie) cdns_pcie_host_disable_ptm_response() argument 163 cdns_pcie_host_enable_ptm_response(struct cdns_pcie * pcie) cdns_pcie_host_enable_ptm_response() argument 173 struct cdns_pcie pcie = &rc->pcie; cdns_pcie_host_start_link() local 190 struct cdns_pcie pcie = &rc->pcie; cdns_pcie_host_deinit_root_port() local 210 struct cdns_pcie pcie = &rc->pcie; cdns_pcie_host_init_root_port() local 253 struct cdns_pcie pcie = &rc->pcie; cdns_pcie_host_bar_ib_config() local 345 struct cdns_pcie pcie = &rc->pcie; cdns_pcie_host_bar_config() local 426 struct cdns_pcie pcie = &rc->pcie; cdns_pcie_host_unmap_dma_ranges() local 452 struct cdns_pcie pcie = &rc->pcie; cdns_pcie_host_map_dma_ranges() local 489 struct cdns_pcie pcie = &rc->pcie; cdns_pcie_host_deinit_address_translation() local 512 struct cdns_pcie pcie = &rc->pcie; cdns_pcie_host_init_address_translation() local 587 struct cdns_pcie pcie = &rc->pcie; cdns_pcie_host_link_disable() local 595 struct cdns_pcie pcie = &rc->pcie; cdns_pcie_host_link_setup() local 638 struct cdns_pcie pcie; cdns_pcie_host_setup() local [all...]
H A D	pcie-cadence-ep.c	3 // Cadence PCIe endpoint controller driver. 15 #include "pcie-cadence.h" 22 static u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie pcie, u8 fn, u8 vfn) in cdns_pcie_get_fn_from_vfn() argument 30 cap = cdns_pcie_find_ext_capability(pcie, PCI_EXT_CAP_ID_SRIOV); in cdns_pcie_get_fn_from_vfn() 31 first_vf_offset = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_OFFSET); in cdns_pcie_get_fn_from_vfn() 32 stride = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_STRIDE); in cdns_pcie_get_fn_from_vfn() 42 struct cdns_pcie pcie = &ep->pcie; in cdns_pcie_ep_write_header() local 46 cap = cdns_pcie_find_ext_capability(pcie, PCI_EXT_CAP_ID_SRIOV); in cdns_pcie_ep_write_header() 52 cdns_pcie_ep_fn_writew(pcie, fn, reg, hdr->deviceid); in cdns_pcie_ep_write_header() 56 cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid); in cdns_pcie_ep_write_header() [all …]

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