| /linux/drivers/pci/controller/dwc/ |
| H A D | pcie-tegra194.c | 3 * PCIe host controller driver for the following SoCs
33 #include "pcie-designware.h"
293 static inline void appl_writel(struct tegra_pcie_dw *pcie, const u32 value, in appl_writel() argument
296 writel_relaxed(value, pcie->appl_base + reg); in appl_writel()
299 static inline u32 appl_readl(struct tegra_pcie_dw *pcie, const u32 reg) in appl_readl() argument
301 return readl_relaxed(pcie->appl_base + reg); in appl_readl()
304 static void tegra_pcie_icc_set(struct tegra_pcie_dw *pcie) in tegra_pcie_icc_set() argument
306 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_icc_set()
309 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in tegra_pcie_icc_set()
316 if (icc_set_bw(pcie->icc_path, Mbps_to_icc(val), 0)) in tegra_pcie_icc_set()
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| H A D | pcie-qcom.c | 3 * Qualcomm PCIe root complex driver
28 #include <linux/phy/pcie.h>
37 #include "pcie-designware.h"
38 #include "pcie-qcom-common.h"
244 int (*get_resources)(struct qcom_pcie *pcie);
245 int (*init)(struct qcom_pcie *pcie);
246 int (*post_init)(struct qcom_pcie *pcie);
247 void (*host_post_init)(struct qcom_pcie *pcie);
248 void (*deinit)(struct qcom_pcie *pcie);
249 void (*ltssm_enable)(struct qcom_pcie *pcie);
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| H A D | pcie-visconti.c | 3 * DWC PCIe RC driver for Toshiba Visconti ARM SoC
24 #include "pcie-designware.h"
96 /* Access registers in PCIe ulreg */
97 static void visconti_ulreg_writel(struct visconti_pcie *pcie, u32 val, u32 reg) in visconti_ulreg_writel() argument
99 writel_relaxed(val, pcie->ulreg_base + reg); in visconti_ulreg_writel()
102 static u32 visconti_ulreg_readl(struct visconti_pcie *pcie, u32 reg) in visconti_ulreg_readl() argument
104 return readl_relaxed(pcie->ulreg_base + reg); in visconti_ulreg_readl()
107 /* Access registers in PCIe smu */
108 static void visconti_smu_writel(struct visconti_pcie *pcie, u32 val, u32 reg) in visconti_smu_writel() argument
110 writel_relaxed(val, pcie->smu_base + reg); in visconti_smu_writel()
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| H A D | pcie-uniphier.c | 3 * PCIe host controller driver for UniPhier SoCs
23 #include "pcie-designware.h"
75 static void uniphier_pcie_ltssm_enable(struct uniphier_pcie *pcie, in uniphier_pcie_ltssm_enable() argument
80 val = readl(pcie->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
85 writel(val, pcie->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
88 static void uniphier_pcie_init_rc(struct uniphier_pcie *pcie) in uniphier_pcie_init_rc() argument
93 val = readl(pcie->base + PCL_MODE); in uniphier_pcie_init_rc()
96 writel(val, pcie->base + PCL_MODE); in uniphier_pcie_init_rc()
99 val = readl(pcie->base + PCL_APP_PM0); in uniphier_pcie_init_rc()
101 writel(val, pcie->base + PCL_APP_PM0); in uniphier_pcie_init_rc()
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| H A D | pcie-amd-mdb.c | 3 * PCIe host controller driver for AMD MDB PCIe Bridge
21 #include "pcie-designware.h"
54 * struct amd_mdb_pcie - PCIe port information
55 * @pci: DesignWare PCIe controller structure
74 struct amd_mdb_pcie *pcie = irq_data_get_irq_chip_data(data); in amd_mdb_intx_irq_mask() local
75 struct dw_pcie *pci = &pcie->pci; in amd_mdb_intx_irq_mask()
88 writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_DISABLE_MISC); in amd_mdb_intx_irq_mask()
94 struct amd_mdb_pcie *pcie = irq_data_get_irq_chip_data(data); in amd_mdb_intx_irq_unmask() local
95 struct dw_pcie *pci = &pcie->pci; in amd_mdb_intx_irq_unmask()
108 writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_ENABLE_MISC); in amd_mdb_intx_irq_unmask()
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| H A D | pcie-keembay.c | 3 * PCIe controller driver for Intel Keem Bay
22 #include "pcie-designware.h"
72 static void keembay_ep_reset_assert(struct keembay_pcie *pcie) in keembay_ep_reset_assert() argument
74 gpiod_set_value_cansleep(pcie->reset, 1); in keembay_ep_reset_assert()
78 static void keembay_ep_reset_deassert(struct keembay_pcie *pcie) in keembay_ep_reset_deassert() argument
88 gpiod_set_value_cansleep(pcie->reset, 0); in keembay_ep_reset_deassert()
92 static void keembay_pcie_ltssm_set(struct keembay_pcie *pcie, bool enable) in keembay_pcie_ltssm_set() argument
96 val = readl(pcie->apb_base + PCIE_REGS_PCIE_APP_CNTRL); in keembay_pcie_ltssm_set()
101 writel(val, pcie->apb_base + PCIE_REGS_PCIE_APP_CNTRL); in keembay_pcie_ltssm_set()
106 struct keembay_pcie *pcie = dev_get_drvdata(pci->dev); in keembay_pcie_link_up() local
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| H A D | pcie-armada8k.c | 3 * PCIe host controller driver for Marvell Armada-8K SoCs
5 * Armada-8K PCIe Glue Layer Source Code
25 #include "pcie-designware.h"
73 static void armada8k_pcie_disable_phys(struct armada8k_pcie *pcie) in armada8k_pcie_disable_phys() argument
78 phy_power_off(pcie->phy[i]); in armada8k_pcie_disable_phys()
79 phy_exit(pcie->phy[i]); in armada8k_pcie_disable_phys()
83 static int armada8k_pcie_enable_phys(struct armada8k_pcie *pcie) in armada8k_pcie_enable_phys() argument
89 ret = phy_init(pcie->phy[i]); in armada8k_pcie_enable_phys()
93 ret = phy_set_mode_ext(pcie->phy[i], PHY_MODE_PCIE, in armada8k_pcie_enable_phys()
94 pcie->phy_count); in armada8k_pcie_enable_phys()
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| /linux/drivers/pci/controller/ |
| H A D | pcie-altera.c | 6 * Description: Altera PCIe host controller driver
45 #define S10_RP_CFG_ADDR(pcie, reg) \ argument
46 (((pcie)->hip_base) + (reg) + (1 << 20))
47 #define S10_RP_SECONDARY(pcie) \ argument
48 readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
59 #define TLP_CFG_DW0(pcie, cfg) \ argument
62 #define TLP_CFG_DW1(pcie, tag, be) \ argument
63 (((PCI_DEVID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
81 #define AGLX_RP_CFG_ADDR(pcie, reg) (((pcie)->hip_base) + (reg)) argument
82 #define AGLX_RP_SECONDARY(pcie) \ argument
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| H A D | pcie-xilinx-nwl.c | 3 * PCIe host controller driver for NWL PCIe Bridge
4 * Based on pcie-xilinx.c, pci-tegra.c
163 phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base */
176 static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off) in nwl_bridge_readl() argument
178 return readl(pcie->breg_base + off); in nwl_bridge_readl()
181 static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off) in nwl_bridge_writel() argument
183 writel(val, pcie->breg_base + off); in nwl_bridge_writel()
186 static bool nwl_pcie_link_up(struct nwl_pcie *pcie) in nwl_pcie_link_up() argument
188 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT) in nwl_pcie_link_up()
193 static bool nwl_phy_link_up(struct nwl_pcie *pcie) in nwl_phy_link_up() argument
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| H A D | pci-aardvark.c | 3 * Driver for the Aardvark PCIe controller, used on Marvell Armada
31 /* PCIe core registers */
124 /* PCIe window configuration */
215 /* PCIe core controller registers */
223 /* PCIe Central Interrupts Registers */
292 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) in advk_writel() argument
294 writel(val, pcie->base + reg); in advk_writel()
297 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg) in advk_readl() argument
299 return readl(pcie->base + reg); in advk_readl()
302 static u8 advk_pcie_ltssm_state(struct advk_pcie *pcie) in advk_pcie_ltssm_state() argument
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| H A D | pcie-mediatek-gen3.c | 3 * MediaTek PCIe host controller driver.
132 /* Time in ms needed to complete PCIe reset on EN7581 SoC */
149 * @power_up: pcie power_up callback
151 * @flags: pcie device flags.
154 int (*power_up)(struct mtk_gen3_pcie *pcie);
175 * struct mtk_gen3_pcie - PCIe port information
176 * @dev: pointer to PCIe device
182 * @clks: PCIe clocks
183 * @num_clks: PCIe clocks count for this port
184 * @max_link_speed: Maximum link speed (PCIe Gen) for this port
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| H A D | pci-tegra.c | 3 * PCIe host controller driver for Tegra SoCs
8 * Based on NVIDIA PCIe driver
11 * Bits taken from arch/arm/mach-dove/pcie.c
258 * entries, one entry per PCIe port. These field definitions and desired
363 struct tegra_pcie *pcie; member
376 static inline void afi_writel(struct tegra_pcie *pcie, u32 value, in afi_writel() argument
379 writel(value, pcie->afi + offset); in afi_writel()
382 static inline u32 afi_readl(struct tegra_pcie *pcie, unsigned long offset) in afi_readl() argument
384 return readl(pcie->afi + offset); in afi_readl()
387 static inline void pads_writel(struct tegra_pcie *pcie, u32 value, in pads_writel() argument
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| H A D | pcie-brcmstb.c | 40 /* Broadcom STB PCIe Register Offsets */
161 /* PCIe parameters */
196 #define IDX_ADDR(pcie) ((pcie)->cfg->offsets[EXT_CFG_INDEX]) argument
197 #define DATA_ADDR(pcie) ((pcie)->cfg->offsets[EXT_CFG_DATA]) argument
198 #define PCIE_RGR1_SW_INIT_1(pcie) ((pcie)->cfg->offsets[RGR1_SW_INIT_1]) argument
199 #define HARD_DEBUG(pcie) ((pcie)->cfg->offsets[PCIE_HARD_DEBUG]) argument
200 #define INTR2_CPU_BASE(pcie) ((pcie)->cfg->offsets[PCIE_INTR2_CPU_BASE]) argument
240 * The RESCAL block is tied to PCIe controller #1, regardless of the number of
241 * controllers, and turning off PCIe controller #1 prevents access to the RESCAL
254 int (*perst_set)(struct brcm_pcie *pcie, u32 val);
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| H A D | pcie-xilinx.c | 3 * PCIe host controller driver for Xilinx AXI PCIe Bridge
7 * Based on the Tegra PCIe driver
94 * struct xilinx_pcie - PCIe port information
113 static inline u32 pcie_read(struct xilinx_pcie *pcie, u32 reg) in pcie_read() argument
115 return readl(pcie->reg_base + reg); in pcie_read()
118 static inline void pcie_write(struct xilinx_pcie *pcie, u32 val, u32 reg) in pcie_write() argument
120 writel(val, pcie->reg_base + reg); in pcie_write()
123 static inline bool xilinx_pcie_link_up(struct xilinx_pcie *pcie) in xilinx_pcie_link_up() argument
125 return (pcie_read(pcie, XILINX_PCIE_REG_PSCR) & in xilinx_pcie_link_up()
131 * @pcie: PCIe port information
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| H A D | pcie-iproc.c | 24 #include "pcie-iproc.h"
91 * struct iproc_pcie_ob_map - iProc PCIe outbound mapping controller-specific
138 * enum iproc_pcie_ib_map_type - iProc PCIe inbound mapping type
150 * struct iproc_pcie_ib_map - iProc PCIe inbound mapping controller-specific
229 * iProc PCIe host registers
306 /* iProc PCIe PAXB BCMA registers */
317 /* iProc PCIe PAXB registers */
333 /* iProc PCIe PAXB v2 registers */
364 /* iProc PCIe PAXC v1 registers */
373 /* iProc PCIe PAXC v2 registers */
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| H A D | Kconfig | 11 tristate "Aardvark PCIe controller"
17 Add support for Aardvark 64bit PCIe Host Controller. This
22 tristate "Altera PCIe controller"
25 Say Y here if you want to enable PCIe controller support on Altera
29 tristate "Altera PCIe MSI feature"
33 Say Y here if you want PCIe MSI support for the Altera FPGA.
42 tristate "Apple PCIe controller"
49 Say Y here if you want to enable PCIe controller support on Apple
60 tristate "Broadcom Brcmstb PCIe controller"
67 Say Y here to enable PCIe host controller support for
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| H A D | pcie-rcar-ep.c | 3 * PCIe endpoint driver for Renesas R-Car SoCs
17 #include "pcie-rcar.h"
21 /* Structure representing the PCIe interface */
23 struct rcar_pcie pcie; member
33 static void rcar_pcie_ep_hw_init(struct rcar_pcie *pcie) in rcar_pcie_ep_hw_init() argument
37 rcar_pci_write_reg(pcie, 0, PCIETCTLR); in rcar_pcie_ep_hw_init()
40 rcar_pci_write_reg(pcie, 0, PCIEMSR); in rcar_pcie_ep_hw_init()
43 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP); in rcar_pcie_ep_hw_init()
44 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS), in rcar_pcie_ep_hw_init()
46 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), PCI_HEADER_TYPE_MASK, in rcar_pcie_ep_hw_init()
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| /linux/drivers/pci/controller/mobiveil/ |
| H A D | pcie-mobiveil-host.c | 3 * PCIe host controller driver for Mobiveil PCIe Host controller
25 #include "pcie-mobiveil.h"
50 struct mobiveil_pcie *pcie = bus->sysdata; in mobiveil_pcie_map_bus() local
51 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_map_bus()
59 return pcie->csr_axi_slave_base + where; in mobiveil_pcie_map_bus()
71 mobiveil_csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0)); in mobiveil_pcie_map_bus()
85 struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc); in mobiveil_pcie_isr() local
86 struct device *dev = &pcie->pdev->dev; in mobiveil_pcie_isr()
87 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_isr()
102 val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT); in mobiveil_pcie_isr()
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| H A D | pcie-mobiveil.c | 3 * PCIe host controller driver for Mobiveil PCIe Host controller
18 #include "pcie-mobiveil.h"
28 static void mobiveil_pcie_sel_page(struct mobiveil_pcie *pcie, u8 pg_idx) in mobiveil_pcie_sel_page() argument
32 val = readl(pcie->csr_axi_slave_base + PAB_CTRL); in mobiveil_pcie_sel_page()
36 writel(val, pcie->csr_axi_slave_base + PAB_CTRL); in mobiveil_pcie_sel_page()
39 static void __iomem *mobiveil_pcie_comp_addr(struct mobiveil_pcie *pcie, in mobiveil_pcie_comp_addr() argument
44 mobiveil_pcie_sel_page(pcie, 0); in mobiveil_pcie_comp_addr()
45 return pcie->csr_axi_slave_base + off; in mobiveil_pcie_comp_addr()
48 mobiveil_pcie_sel_page(pcie, OFFSET_TO_PAGE_IDX(off)); in mobiveil_pcie_comp_addr()
49 return pcie->csr_axi_slave_base + OFFSET_TO_PAGE_ADDR(off); in mobiveil_pcie_comp_addr()
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| H A D | pcie-layerscape-gen4.c | 3 * PCIe Gen4 host controller driver for NXP Layerscape SoCs
23 #include "pcie-mobiveil.h"
45 static inline u32 ls_g4_pcie_pf_readl(struct ls_g4_pcie *pcie, u32 off) in ls_g4_pcie_pf_readl() argument
47 return ioread32(pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); in ls_g4_pcie_pf_readl()
50 static inline void ls_g4_pcie_pf_writel(struct ls_g4_pcie *pcie, in ls_g4_pcie_pf_writel() argument
53 iowrite32(val, pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); in ls_g4_pcie_pf_writel()
58 struct ls_g4_pcie *pcie = to_ls_g4_pcie(pci); in ls_g4_pcie_link_up() local
61 state = ls_g4_pcie_pf_readl(pcie, PCIE_PF_DBG); in ls_g4_pcie_link_up()
65 static void ls_g4_pcie_disable_interrupt(struct ls_g4_pcie *pcie) in ls_g4_pcie_disable_interrupt() argument
67 struct mobiveil_pcie *mv_pci = &pcie->pci; in ls_g4_pcie_disable_interrupt()
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| /linux/drivers/pci/controller/cadence/ |
| H A D | pci-j721e.c | 3 * pci-j721e - PCIe controller driver for TI's J721E SoCs
26 #include "pcie-cadence.h"
28 #define cdns_pcie_to_rc(p) container_of(p, struct cdns_pcie_rc, pcie)
83 static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) in j721e_pcie_user_readl() argument
85 return readl(pcie->user_cfg_base + offset); in j721e_pcie_user_readl()
88 static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset, in j721e_pcie_user_writel() argument
91 writel(value, pcie->user_cfg_base + offset); in j721e_pcie_user_writel()
94 static inline u32 j721e_pcie_intd_readl(struct j721e_pcie *pcie, u32 offset) in j721e_pcie_intd_readl() argument
96 return readl(pcie->intd_cfg_base + offset); in j721e_pcie_intd_readl()
99 static inline void j721e_pcie_intd_writel(struct j721e_pcie *pcie, u32 offset, in j721e_pcie_intd_writel() argument
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| H A D | pcie-cadence.c | 3 // Cadence PCIe controller driver.
10 #include "pcie-cadence.h"
12 void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie) in cdns_pcie_detect_quiet_min_delay_set() argument
20 ltssm_control_cap = cdns_pcie_readl(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP); in cdns_pcie_detect_quiet_min_delay_set()
25 cdns_pcie_writel(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP, ltssm_control_cap); in cdns_pcie_detect_quiet_min_delay_set()
29 void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, in cdns_pcie_set_outbound_region() argument
49 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r), addr0); in cdns_pcie_set_outbound_region()
50 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r), addr1); in cdns_pcie_set_outbound_region()
52 /* Set the PCIe header descriptor */ in cdns_pcie_set_outbound_region()
61 * PCIe descriptor, the PCI function number must be set into in cdns_pcie_set_outbound_region()
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| H A D | pcie-cadence-host.c | 3 // Cadence PCIe host controller driver.
14 #include "pcie-cadence.h"
34 struct cdns_pcie *pcie = &rc->pcie; in cdns_pci_map_bus() local
47 return pcie->reg_base + (where & 0xfff); in cdns_pci_map_bus()
50 if (!(cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE) & 0x1)) in cdns_pci_map_bus()
53 cdns_pcie_writel(pcie, CDNS_PCIE_AT_LINKDOWN, 0x0); in cdns_pci_map_bus()
59 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(0), addr0); in cdns_pci_map_bus()
72 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC0(0), desc0); in cdns_pci_map_bus()
84 static int cdns_pcie_host_training_complete(struct cdns_pcie *pcie) in cdns_pcie_host_training_complete() argument
93 lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); in cdns_pcie_host_training_complete()
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| H A D | pcie-cadence-ep.c | 3 // Cadence PCIe endpoint controller driver.
15 #include "pcie-cadence.h"
22 static u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn) in cdns_pcie_get_fn_from_vfn() argument
30 first_vf_offset = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_OFFSET); in cdns_pcie_get_fn_from_vfn()
31 stride = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_STRIDE); in cdns_pcie_get_fn_from_vfn()
42 struct cdns_pcie *pcie = &ep->pcie; in cdns_pcie_ep_write_header() local
50 cdns_pcie_ep_fn_writew(pcie, fn, reg, hdr->deviceid); in cdns_pcie_ep_write_header()
54 cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid); in cdns_pcie_ep_write_header()
55 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid); in cdns_pcie_ep_write_header()
56 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG, hdr->progif_code); in cdns_pcie_ep_write_header()
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| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | qcom,pcie.yaml | 4 $id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
14 Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
15 PCIe IP.
21 - qcom,pcie-apq8064
22 - qcom,pcie-apq8084
23 - qcom,pcie-ipq4019
24 - qcom,pcie-ipq5018
25 - qcom,pcie-ipq6018
26 - qcom,pcie-ipq8064
27 - qcom,pcie-ipq8064-v2
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