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/linux/Documentation/devicetree/bindings/pci/
H A Dqcom,pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
15 PCIe IP.
20 - enum:
21 - qcom,pcie-apq8064
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H A Dsocionext,uniphier-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier PCIe endpoint controller
10 UniPhier PCIe endpoint controller is based on the Synopsys DesignWare
11 PCI core. It shares common features with the PCIe DesignWare core and
13 Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro5-pcie-ep
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H A Dnvidia,tegra194-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra194 (and later) PCIe Endpoint controller (Synopsys DesignWare Core based)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
15 This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus
16 inherits all the common properties defined in snps,dw-pcie-ep.yaml. Some
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H A Drockchip-dw-pcie-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DesignWare based PCIe RC/EP controller on Rockchip SoCs
10 - Shawn Lin <shawn.lin@rock-chips.com>
11 - Simon Xue <xxm@rock-chips.com>
12 - Heiko Stuebner <heiko@sntech.de>
15 Generic properties for the DesignWare based PCIe RC/EP controller on Rockchip
20 minItems: 5
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H A Dhisilicon,kirin-pcie.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/hisilicon,kirin-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: HiSilicon Kirin SoCs PCIe host DT description
10 - Xiaowei Song <songxiaowei@hisilicon.com>
11 - Binghui Wang <wangbinghui@hisilicon.com>
14 Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
15 It shares common functions with the PCIe DesignWare core driver and
17 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
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H A Dnvidia,tegra194-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra194 (and later) PCIe controller (Synopsys DesignWare Core based)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
15 This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
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H A Drockchip-dw-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DesignWare based PCIe Root Complex controller on Rockchip SoCs
10 - Shawn Lin <shawn.lin@rock-chips.com>
11 - Simon Xue <xxm@rock-chips.com>
12 - Heiko Stuebner <heiko@sntech.de>
15 RK3568 SoC PCIe Root Complex controller is based on the Synopsys DesignWare
16 PCIe IP and thus inherits all the common properties defined in
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H A Dqcom,pcie-sm8550.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sm8550.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 Qualcomm SM8550 SoC (and compatible) PCIe root complex controller is based on
15 the Synopsys DesignWare PCIe IP.
20 - const: qcom,pcie-sm8550
21 - items:
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H A Dbrcm,stb-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Brcmstb PCIe Host Controller
10 - Jim Quinlan <james.quinlan@broadcom.com>
15 - enum:
16 - brcm,bcm2711-pcie # The Raspberry Pi 4
17 - brcm,bcm2712-pcie # Raspberry Pi 5
18 - brcm,bcm4908-pcie
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H A Dqcom,pcie-sa8775p.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sa8775p.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 Qualcomm SA8775p SoC PCIe root complex controller is based on the Synopsys
15 DesignWare PCIe IP.
20 - const: qcom,pcie-sa8775p
21 - items:
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H A Dqcom,pcie-sc8280xp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sc8280xp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 Qualcomm SC8280XP SoC PCIe root complex controller is based on the Synopsys
15 DesignWare PCIe IP.
20 - qcom,pcie-sa8540p
21 - qcom,pcie-sc8280xp
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H A Dqcom,pcie-sm8250.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sm8250.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 Qualcomm SM8250 SoC PCIe root complex controller is based on the Synopsys
15 DesignWare PCIe IP.
19 const: qcom,pcie-sm8250
22 minItems: 5
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H A Dqcom,pcie-sc7280.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sc7280.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 Qualcomm SC7280 SoC PCIe root complex controller is based on the Synopsys
15 DesignWare PCIe IP.
19 const: qcom,pcie-sc7280
22 minItems: 5
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H A Dqcom,pcie-sm8150.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sm8150.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 Qualcomm SM8150 SoC PCIe root complex controller is based on the Synopsys
15 DesignWare PCIe IP.
20 - const: qcom,pcie-sm8150
21 - items:
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/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,sc8280xp-qmp-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
10 - Vinod Koul <vkoul@kernel.org>
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
19 - qcom,qcs615-qmp-gen3x1-pcie-phy
20 - qcom,qcs8300-qmp-gen4x2-pcie-phy
21 - qcom,sa8775p-qmp-gen4x2-pcie-phy
[all …]
/linux/drivers/pci/controller/cadence/
H A Dpcie-cadence.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 // Cadence PCIe controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
11 #include <linux/pci-epf.h>
67 (GENMASK(7, 5) << ((b) * 8))
69 (((c) << ((b) * 8 + 5)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b))
76 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0)
117 (((aperture) - 2) << ((bar) * 8))
145 /* Region r Outbound AXI to PCIe Address Translation Register 0 */
148 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0)
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/linux/arch/arm/boot/dts/st/
H A Dspear1310.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
15 compatible = "st,spear-spics-gpio";
17 st-spics,peripcfg-reg = <0x3b0>;
18 st-spics,sw-enable-bit = <12>;
19 st-spics,cs-value-bit = <11>;
20 st-spics,cs-enable-mask = <3>;
21 st-spics,cs-enable-shift = <8>;
22 gpio-controller;
23 #gpio-cells = <2>;
27 compatible = "st,spear1310-miphy";
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/linux/drivers/pci/controller/
H A Dpcie-rcar.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Renesas R-Car SoCs
4 * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
12 #include "pcie-rcar.h"
14 void rcar_pci_write_reg(struct rcar_pcie *pcie, u32 val, unsigned int reg) in rcar_pci_write_reg() argument
16 writel(val, pcie->base + reg); in rcar_pci_write_reg()
19 u32 rcar_pci_read_reg(struct rcar_pcie *pcie, unsigned int reg) in rcar_pci_read_reg() argument
21 return readl(pcie->base + reg); in rcar_pci_read_reg()
24 void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data) in rcar_rmw32() argument
27 u32 val = rcar_pci_read_reg(pcie, where & ~3); in rcar_rmw32()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
11 tristate "Aardvark PCIe controller"
18 Add support for Aardvark 64bit PCIe Host Controller. This
23 tristate "Altera PCIe controller"
26 Say Y here if you want to enable PCIe controller support on Altera
30 tristate "Altera PCIe MSI feature"
35 Say Y here if you want PCIe MSI support for the Altera FPGA.
44 tristate "Apple PCIe controller"
51 Say Y here if you want to enable PCIe controller support on Apple
52 system-on-chips, like the Apple M1. This is required for the USB
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/linux/drivers/phy/broadcom/
H A Dphy-bcm-sr-pcie.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Broadcom
18 #define SR_PAXC_PHY_IDX (SR_NR_PCIE_PHYS - 1)
40 * struct sr_pcie_phy - Stingray PCIe PHY
42 * @core: pointer to the Stingray PCIe PHY core control
53 * struct sr_pcie_phy_core - Stingray PCIe PHY core control
56 * @base: base register of PCIe SS
60 * @phys: array of PCIe PHYs
72 * PCIe PIPEMUX lookup table
75 * The array element represents a bitmap where a set bit means the PCIe
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/linux/Documentation/admin-guide/perf/
H A Dhisi-pcie-pmu.rst2 HiSilicon PCIe Performance Monitoring Unit (PMU)
5 On Hip09, HiSilicon PCIe Performance Monitoring Unit (PMU) could monitor
6 bandwidth, latency, bus utilization and buffer occupancy data of PCIe.
8 Each PCIe Core has a PMU to monitor multi Root Ports of this PCIe Core and
12 HiSilicon PCIe PMU driver
15 The PCIe PMU driver registers a perf PMU with the name of its sicl-id and PCIe
40 ------------------------------------------
42 $# perf stat -e hisi_pcie0_core0/rx_mwr_latency,port=0xffff/
43 $# perf stat -e hisi_pcie0_core0/rx_mwr_cnt,port=0xffff/
56 …$# perf stat -e "{hisi_pcie0_core0/rx_mwr_latency,port=0xffff/,hisi_pcie0_core0/rx_mwr_cnt,port=0x…
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/linux/arch/arm/mach-mv78xx0/
H A Dmv78xx0.h1 /* SPDX-License-Identifier: GPL-2.0-only */
16 * c0000000 PCIe Memory space
17 * f0800000 PCIe #0 I/O space
18 * f0900000 PCIe #1 I/O space
19 * f0a00000 PCIe #2 I/O space
20 * f0b00000 PCIe #3 I/O space
21 * f0c00000 PCIe #4 I/O space
22 * f0d00000 PCIe #5 I/O space
23 * f0e00000 PCIe #6 I/O space
24 * f0f00000 PCIe #7 I/O space
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/linux/drivers/pci/hotplug/
H A Dpciehp.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
8 * Copyright (C) 2003-2004 Intel Corporation
26 #include "../pcie/portdrv.h"
36 pci_dbg(ctrl->pcie->port, format, ## arg)
38 pci_err(ctrl->pcie->port, format, ## arg)
40 pci_info(ctrl->pcie->port, format, ## arg)
42 pci_warn(ctrl->pcie->port, format, ## arg)
47 * struct controller - PCIe hotplug controller
48 * @pcie: pointer to the controller's PCIe port service device
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/linux/drivers/pci/controller/mobiveil/
H A Dpcie-mobiveil.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * PCIe host controller driver for Mobiveil PCIe Host controller
58 #define PAB_INTP_INTA BIT(5)
101 #define PAB_INTX_START 5
147 int (*interrupt_init)(struct mobiveil_pcie *pcie);
162 bool (*link_up)(struct mobiveil_pcie *pcie);
169 phys_addr_t pcie_reg_base; /* Physical PCIe Controller Base */
178 int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie);
179 int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit);
180 bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie);
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/linux/arch/powerpc/boot/dts/
H A Dturris1x.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2013 - 2022 CZ.NIC z.s.p.o. (http://www.nic.cz/)
8 * and available at: https://docs.turris.cz/hw/turris-1x/turris-1x/
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/leds/common.h>
14 /include/ "fsl/p2020si-pre.dtsi"
41 gpio-controller@18 {
45 #gpio-cells = <2>;
46 gpio-controller;
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