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/linux/drivers/pci/controller/dwc/
H A Dpcie-tegra194.c1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for the following SoCs
7 * Copyright (C) 2019-2022 NVIDIA Corporation.
33 #include "pcie-designware.h"
35 #include <soc/tegra/bpmp-abi.h>
38 #define TEGRA194_DWC_IP_VER 0x490A
39 #define TEGRA234_DWC_IP_VER 0x562A
41 #define APPL_PINMUX 0x0
42 #define APPL_PINMUX_PEX_RST BIT(0)
48 #define APPL_CTRL 0x4
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H A Dpcie-visconti.c1 // SPDX-License-Identifier: GPL-2.0
3 * DWC PCIe RC driver for Toshiba Visconti ARM SoC
24 #include "pcie-designware.h"
37 #define PCIE_UL_REG_S_PCIE_MODE 0x00F4
38 #define PCIE_UL_REG_S_PCIE_MODE_EP 0x00
39 #define PCIE_UL_REG_S_PCIE_MODE_RC 0x04
41 #define PCIE_UL_REG_S_PERSTN_CTRL 0x00F8
45 #define PCIE_UL_DIRECT_PERSTN BIT(0)
50 #define PCIE_UL_REG_S_PHY_INIT_02 0x0104
51 #define PCIE_UL_PHY0_SRAM_EXT_LD_DONE BIT(0)
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H A Dpcie-qcom.c1 // SPDX-License-Identifier: GPL-2.0
3 * Qualcomm PCIe root complex driver
5 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
8 * Author: Stanimir Varbanov <svarbanov@mm-sol.com>
26 #include <linux/pci-ecam.h>
30 #include <linux/phy/pcie.h>
39 #include "../pci-host-common.h"
40 #include "pcie-designware.h"
41 #include "pcie-qcom-common.h"
44 #define PARF_SYS_CTRL 0x00
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H A Dpcie-keembay.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PCIe controller driver for Intel Keem Bay
22 #include "pcie-designware.h"
25 #define PCIE_REGS_PCIE_CFG 0x0004
27 #define PCIE_RSTN BIT(0)
28 #define PCIE_REGS_PCIE_APP_CNTRL 0x0008
29 #define APP_LTSSM_ENABLE BIT(0)
30 #define PCIE_REGS_INTERRUPT_ENABLE 0x0028
32 #define EDMA_INT_EN GENMASK(7, 0)
33 #define PCIE_REGS_INTERRUPT_STATUS 0x002c
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H A Dpcie-uniphier.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for UniPhier SoCs
23 #include "pcie-designware.h"
25 #define PCL_PINCTRL0 0x002c
31 #define PCL_PERST_OUT_REGVAL BIT(0)
33 #define PCL_PIPEMON 0x0044
36 #define PCL_MODE 0x8000
38 #define PCL_MODE_REGVAL BIT(0)
40 #define PCL_APP_READY_CTRL 0x8008
41 #define PCL_APP_LTSSM_ENABLE BIT(0)
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H A Dpcie-amd-mdb.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for AMD MDB PCIe Bridge
5 * Copyright (C) 2024-2025, Advanced Micro Devices, Inc.
22 #include "pcie-designware.h"
24 #define AMD_MDB_TLP_IR_STATUS_MISC 0x4C0
25 #define AMD_MDB_TLP_IR_MASK_MISC 0x4C4
26 #define AMD_MDB_TLP_IR_ENABLE_MISC 0x4C8
27 #define AMD_MDB_TLP_IR_DISABLE_MISC 0x4CC
55 * struct amd_mdb_pcie - PCIe port information
56 * @pci: DesignWare PCIe controller structure
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/linux/drivers/pci/controller/
H A Dpcie-altera.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright Altera Corporation (C) 2013-2015. All rights reserved
6 * Description: Altera PCIe host controller driver
24 #define RP_TX_REG0 0x2000
25 #define RP_TX_REG1 0x2004
26 #define RP_TX_CNTRL 0x2008
27 #define RP_TX_EOP 0x2
28 #define RP_TX_SOP 0x1
29 #define RP_RXCPL_STATUS 0x2010
30 #define RP_RXCPL_EOP 0x2
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H A Dpci-aardvark.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the Aardvark PCIe controller, used on Marvell Armada
16 #include <linux/irqchip/irq-msi-lib.h>
21 #include <linux/pci-ecam.h>
30 #include "../pci-bridge-emul.h"
32 /* PCIe core registers */
33 #define PCIE_CORE_DEV_ID_REG 0x0
34 #define PCIE_CORE_CMD_STATUS_REG 0x4
35 #define PCIE_CORE_DEV_REV_REG 0x8
36 #define PCIE_CORE_SSDEV_ID_REG 0x2c
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H A Dpcie-xilinx-nwl.c1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for NWL PCIe Bridge
4 * Based on pcie-xilinx.c, pci-tegra.c
6 * (C) Copyright 2014 - 2015, Xilinx, Inc.
13 #include <linux/irqchip/irq-msi-lib.h>
22 #include <linux/pci-ecam.h>
30 #define BRCFG_PCIE_RX0 0x00000000
31 #define BRCFG_PCIE_RX1 0x00000004
32 #define BRCFG_INTERRUPT 0x00000010
33 #define BRCFG_PCIE_RX_MSG_FILTER 0x00000020
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H A Dpci-tegra.c1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for Tegra SoCs
8 * Based on NVIDIA PCIe driver
9 * Copyright (c) 2008-2009, NVIDIA Corporation.
11 * Bits taken from arch/arm/mach-dove/pcie.c
26 #include <linux/irqchip/irq-msi-lib.h>
54 #define AFI_AXI_BAR0_SZ 0x00
55 #define AFI_AXI_BAR1_SZ 0x04
56 #define AFI_AXI_BAR2_SZ 0x08
57 #define AFI_AXI_BAR3_SZ 0x0c
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H A Dpcie-mediatek-gen3.c1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek PCIe host controller driver.
11 #include <linux/clk-provider.h>
15 #include <linux/irqchip/irq-msi-lib.h>
34 #define PCIE_BASE_CFG_REG 0x14
37 #define PCIE_SETTING_REG 0x80
40 #define PCIE_PCI_IDS_1 0x9c
42 #define PCIE_RC_MODE BIT(0)
44 #define PCIE_EQ_PRESET_01_REG 0x100
45 #define PCIE_VAL_LN0_DOWNSTREAM GENMASK(6, 0)
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H A Dpcie-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
15 #include <linux/irqchip/irq-msi-lib.h>
27 #include <linux/pci-ecam.h>
38 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
39 #define BRCM_PCIE_CAP_REGS 0x00ac
41 /* Broadcom STB PCIe Register Offsets */
42 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
43 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
44 #define PCIE_RC_CFG_VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN 0x0
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H A Dpcie-rcar-host.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Renesas R-Car SoCs
4 * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
7 * arch/sh/drivers/pci/pcie-sh7786.c
8 * arch/sh/drivers/pci/ops-sh7786.c
9 * Copyright (C) 2009 - 2011 Paul Mundt
17 #include <linux/clk-provider.h>
21 #include <linux/irqchip/irq-msi-lib.h>
36 #include "pcie-rcar.h"
47 /* Structure representing the PCIe interface */
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H A Dpcie-iproc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
9 #include <linux/pci-ecam.h>
17 #include <linux/irqchip/arm-gic-v3.h>
24 #include "pcie-iproc.h"
30 #define RC_PCIE_RST_OUTPUT_SHIFT 0
32 #define PAXC_RESET_MASK 0x7f
34 #define GIC_V3_CFG_SHIFT 0
37 #define MSI_ENABLE_CFG_SHIFT 0
40 #define CFG_IND_ADDR_MASK 0x00001ffc
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H A Dpcie-xilinx.c1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for Xilinx AXI PCIe Bridge
5 * Copyright (c) 2012 - 2014 Xilinx, Inc.
7 * Based on the Tegra PCIe driver
15 #include <linux/irqchip/irq-msi-lib.h>
25 #include <linux/pci-ecam.h>
31 #define XILINX_PCIE_REG_BIR 0x00000130
32 #define XILINX_PCIE_REG_IDR 0x00000138
33 #define XILINX_PCIE_REG_IMR 0x0000013c
34 #define XILINX_PCIE_REG_PSCR 0x00000144
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H A Dpcie-rcar-ep.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe endpoint driver for Renesas R-Car SoCs
6 * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
13 #include <linux/pci-epc.h>
17 #include "pcie-rcar.h"
21 /* Structure representing the PCIe interface */
23 struct rcar_pcie pcie; member
33 static void rcar_pcie_ep_hw_init(struct rcar_pcie *pcie) in rcar_pcie_ep_hw_init() argument
37 rcar_pci_write_reg(pcie, 0, PCIETCTLR); in rcar_pcie_ep_hw_init()
40 rcar_pci_write_reg(pcie, 0, PCIEMSR); in rcar_pcie_ep_hw_init()
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H A Dpcie-apple.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host bridge driver for Apple system-on-chips.
6 * the driver mostly deals MSI mapping and handling of per-port
26 #include <linux/irqchip/irq-msi-lib.h>
32 #include <linux/pci-ecam.h>
34 #include "pci-host-common.h"
37 #define CORE_RC_PHYIF_CTL 0x00024
38 #define CORE_RC_PHYIF_CTL_RUN BIT(0)
39 #define CORE_RC_PHYIF_STAT 0x00028
41 #define CORE_RC_CTL 0x00050
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/linux/drivers/pci/controller/plda/
H A Dpcie-starfive.c1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for StarFive JH7110 Soc.
27 #include "pcie-plda.h"
32 #define STG_SYSCON_PCIE0_BASE 0x48
33 #define STG_SYSCON_PCIE1_BASE 0x1f8
35 #define STG_SYSCON_AR_OFFSET 0x78
38 #define STG_SYSCON_AW_OFFSET 0x7c
39 #define STG_SYSCON_AXI4_SLVL_AW_MASK GENMASK(14, 0)
43 #define STG_SYSCON_RP_NEP_OFFSET 0xe8
45 #define STG_SYSCON_LNKSTA_OFFSET 0x170
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/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,sc8280xp-qmp-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
10 - Vinod Koul <vkoul@kernel.org>
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
19 - qcom,qcs615-qmp-gen3x1-pcie-phy
20 - qcom,qcs8300-qmp-gen4x2-pcie-phy
21 - qcom,sa8775p-qmp-gen4x2-pcie-phy
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/linux/drivers/pci/controller/cadence/
H A Dpcie-cadence.c1 // SPDX-License-Identifier: GPL-2.0
3 // Cadence PCIe controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
10 #include "pcie-cadence.h"
13 u8 cdns_pcie_find_capability(struct cdns_pcie *pcie, u8 cap) in cdns_pcie_find_capability() argument
16 cap, pcie); in cdns_pcie_find_capability()
20 u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap) in cdns_pcie_find_ext_capability() argument
22 return PCI_FIND_NEXT_EXT_CAP(cdns_pcie_read_cfg, 0, cap, pcie); in cdns_pcie_find_ext_capability()
26 void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie) in cdns_pcie_detect_quiet_min_delay_set() argument
28 u32 delay = 0x3; in cdns_pcie_detect_quiet_min_delay_set()
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H A Dpci-j721e.c1 // SPDX-License-Identifier: GPL-2.0
3 * pci-j721e - PCIe controller driver for TI's J721E SoCs
5 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
10 #include <linux/clk-provider.h>
26 #include "pcie-cadence.h"
28 #define cdns_pcie_to_rc(p) container_of(p, struct cdns_pcie_rc, pcie)
30 #define ENABLE_REG_SYS_2 0x108
31 #define ENABLE_CLR_REG_SYS_2 0x308
32 #define STATUS_REG_SYS_2 0x508
33 #define STATUS_CLR_REG_SYS_2 0x708
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H A Dpcie-cadence-host.c1 // SPDX-License-Identifier: GPL-2.0
3 // Cadence PCIe host controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
14 #include "pcie-cadence.h"
25 [RP_BAR0] = 0x1F,
26 [RP_BAR1] = 0xF,
34 struct cdns_pcie *pcie = &rc->pcie; in cdns_pci_map_bus() local
35 unsigned int busn = bus->number; in cdns_pci_map_bus()
40 * Only the root port (devfn == 0) is connected to this bus. in cdns_pci_map_bus()
47 return pcie->reg_base + (where & 0xfff); in cdns_pci_map_bus()
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H A Dpcie-cadence-ep.c1 // SPDX-License-Identifier: GPL-2.0
3 // Cadence PCIe endpoint controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
11 #include <linux/pci-epc.h>
15 #include "pcie-cadence.h"
19 #define CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE 0x1
20 #define CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY 0x3
22 static u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn) in cdns_pcie_get_fn_from_vfn() argument
27 if (vfn == 0) in cdns_pcie_get_fn_from_vfn()
30 cap = cdns_pcie_find_ext_capability(pcie, PCI_EXT_CAP_ID_SRIOV); in cdns_pcie_get_fn_from_vfn()
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/linux/Documentation/devicetree/bindings/pci/
H A Dqcom,pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
15 PCIe IP.
20 - enum:
21 - qcom,pcie-apq8064
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/linux/drivers/pci/controller/mobiveil/
H A Dpcie-mobiveil-host.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Mobiveil PCIe Host controller
6 * Copyright 2019-2020 NXP
15 #include <linux/irqchip/irq-msi-lib.h>
26 #include "pcie-mobiveil.h"
31 if (pci_is_root_bus(bus) && (devfn > 0)) in mobiveil_pcie_valid_device()
38 if ((bus->primary == to_pci_host_bridge(bus->bridge)->busnr) && (PCI_SLOT(devfn) > 0)) in mobiveil_pcie_valid_device()
45 * mobiveil_pcie_map_bus - routine to get the configuration base of either
51 struct mobiveil_pcie *pcie = bus->sysdata; in mobiveil_pcie_map_bus() local
52 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_map_bus()
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