1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright Altera Corporation (C) 2013-2015. All rights reserved
6  * Description: Altera PCIe host controller driver
24 #define RP_TX_REG0			0x2000
25 #define RP_TX_REG1			0x2004
26 #define RP_TX_CNTRL			0x2008
27 #define RP_TX_EOP			0x2
28 #define RP_TX_SOP			0x1
29 #define RP_RXCPL_STATUS			0x2010
30 #define RP_RXCPL_EOP			0x2
31 #define RP_RXCPL_SOP			0x1
32 #define RP_RXCPL_REG0			0x2014
33 #define RP_RXCPL_REG1			0x2018
34 #define P2A_INT_STATUS			0x3060
35 #define P2A_INT_STS_ALL			0xf
36 #define P2A_INT_ENABLE			0x3070
37 #define P2A_INT_ENA_ALL			0xf
38 #define RP_LTSSM			0x3c64
39 #define RP_LTSSM_MASK			0x1f
40 #define LTSSM_L0			0xf
42 #define S10_RP_TX_CNTRL			0x2004
43 #define S10_RP_RXCPL_REG		0x2008
44 #define S10_RP_RXCPL_STATUS		0x200C
45 #define S10_RP_CFG_ADDR(pcie, reg)	\  argument
46 	(((pcie)->hip_base) + (reg) + (1 << 20))
47 #define S10_RP_SECONDARY(pcie)		\  argument
48 	readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
50 /* TLP configuration type 0 and 1 */
51 #define TLP_FMTTYPE_CFGRD0		0x04	/* Configuration Read Type 0 */
52 #define TLP_FMTTYPE_CFGWR0		0x44	/* Configuration Write Type 0 */
53 #define TLP_FMTTYPE_CFGRD1		0x05	/* Configuration Read Type 1 */
54 #define TLP_FMTTYPE_CFGWR1		0x45	/* Configuration Write Type 1 */
55 #define TLP_PAYLOAD_SIZE		0x01
56 #define TLP_READ_TAG			0x1d
57 #define TLP_WRITE_TAG			0x10
58 #define RP_DEVFN			0
59 #define TLP_CFG_DW0(pcie, cfg)		\  argument
62 #define TLP_CFG_DW1(pcie, tag, be)	\  argument
63 	(((PCI_DEVID(pcie->root_bus_nr,  RP_DEVFN)) << 16) | (tag << 8) | (be))
67 #define TLP_BYTE_COUNT(s)		(((s) >> 0) & 0xfff)
76 #define S10_TLP_FMTTYPE_CFGRD0		0x05
77 #define S10_TLP_FMTTYPE_CFGRD1		0x04
78 #define S10_TLP_FMTTYPE_CFGWR0		0x45
79 #define S10_TLP_FMTTYPE_CFGWR1		0x44
81 #define AGLX_RP_CFG_ADDR(pcie, reg)	(((pcie)->hip_base) + (reg))  argument
82 #define AGLX_RP_SECONDARY(pcie)		\  argument
83 	readb(AGLX_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
85 #define AGLX_BDF_REG			0x00002004
86 #define AGLX_ROOT_PORT_IRQ_STATUS	0x14c
87 #define AGLX_ROOT_PORT_IRQ_ENABLE	0x150
91 #define AGLX_CFG_TARGET_TYPE0		0
97 	ALTERA_PCIE_V1 = 0,
114 	int (*tlp_read_pkt)(struct altera_pcie *pcie, u32 *value);
115 	void (*tlp_write_pkt)(struct altera_pcie *pcie, u32 *headers,
117 	bool (*get_link_status)(struct altera_pcie *pcie);
118 	int (*rp_read_cfg)(struct altera_pcie *pcie, int where,
120 	int (*rp_write_cfg)(struct altera_pcie *pcie, u8 busno,
122 	int (*ep_read_cfg)(struct altera_pcie *pcie, u8 busno,
124 	int (*ep_write_cfg)(struct altera_pcie *pcie, u8 busno,
132 	u32 cap_offset;		/* PCIe capability structure register offset */
148 static inline void cra_writel(struct altera_pcie *pcie, const u32 value,  in cra_writel()  argument
151 	writel_relaxed(value, pcie->cra_base + reg);  in cra_writel()
154 static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg)  in cra_readl()  argument
156 	return readl_relaxed(pcie->cra_base + reg);  in cra_readl()
159 static inline void cra_writew(struct altera_pcie *pcie, const u32 value,  in cra_writew()  argument
162 	writew_relaxed(value, pcie->cra_base + reg);  in cra_writew()
165 static inline u32 cra_readw(struct altera_pcie *pcie, const u32 reg)  in cra_readw()  argument
167 	return readw_relaxed(pcie->cra_base + reg);  in cra_readw()
170 static inline void cra_writeb(struct altera_pcie *pcie, const u32 value,  in cra_writeb()  argument
173 	writeb_relaxed(value, pcie->cra_base + reg);  in cra_writeb()
176 static inline u32 cra_readb(struct altera_pcie *pcie, const u32 reg)  in cra_readb()  argument
178 	return readb_relaxed(pcie->cra_base + reg);  in cra_readb()
181 static bool altera_pcie_link_up(struct altera_pcie *pcie)  in altera_pcie_link_up()  argument
183 	return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);  in altera_pcie_link_up()
186 static bool s10_altera_pcie_link_up(struct altera_pcie *pcie)  in s10_altera_pcie_link_up()  argument
188 	void __iomem *addr = S10_RP_CFG_ADDR(pcie,  in s10_altera_pcie_link_up()
189 				   pcie->pcie_data->cap_offset +  in s10_altera_pcie_link_up()
195 static bool aglx_altera_pcie_link_up(struct altera_pcie *pcie)  in aglx_altera_pcie_link_up()  argument
197 	void __iomem *addr = AGLX_RP_CFG_ADDR(pcie,  in aglx_altera_pcie_link_up()
198 				   pcie->pcie_data->cap_offset +  in aglx_altera_pcie_link_up()
205  * Altera PCIe port uses BAR0 of RC's configuration space as the translation
206  * from PCI bus to native BUS.  Entire DDR region is mapped into PCIe space
208  * This BAR0 will also access to MSI vector when receiving MSI/MSI-X interrupt
211  * allocation by PCIe core.
216 	if (pci_is_root_bus(bus) && (devfn == 0) &&  in altera_pcie_hide_rc_bar()
223 static void tlp_write_tx(struct altera_pcie *pcie,  in tlp_write_tx()  argument
226 	cra_writel(pcie, tlp_rp_regdata->reg0, RP_TX_REG0);  in tlp_write_tx()
227 	cra_writel(pcie, tlp_rp_regdata->reg1, RP_TX_REG1);  in tlp_write_tx()
228 	cra_writel(pcie, tlp_rp_regdata->ctrl, RP_TX_CNTRL);  in tlp_write_tx()
231 static void s10_tlp_write_tx(struct altera_pcie *pcie, u32 reg0, u32 ctrl)  in s10_tlp_write_tx()  argument
233 	cra_writel(pcie, reg0, RP_TX_REG0);  in s10_tlp_write_tx()
234 	cra_writel(pcie, ctrl, S10_RP_TX_CNTRL);  in s10_tlp_write_tx()
237 static bool altera_pcie_valid_device(struct altera_pcie *pcie,  in altera_pcie_valid_device()  argument
241 	if (bus->number != pcie->root_bus_nr) {  in altera_pcie_valid_device()
242 		if (!pcie->pcie_data->ops->get_link_status(pcie))  in altera_pcie_valid_device()
247 	if (bus->number == pcie->root_bus_nr && dev > 0)  in altera_pcie_valid_device()
253 static int tlp_read_packet(struct altera_pcie *pcie, u32 *value)  in tlp_read_packet()  argument
265 	for (i = 0; i < TLP_LOOP; i++) {  in tlp_read_packet()
266 		ctrl = cra_readl(pcie, RP_RXCPL_STATUS);  in tlp_read_packet()
268 			reg0 = cra_readl(pcie, RP_RXCPL_REG0);  in tlp_read_packet()
269 			reg1 = cra_readl(pcie, RP_RXCPL_REG1);  in tlp_read_packet()
292 static int s10_tlp_read_packet(struct altera_pcie *pcie, u32 *value)  in s10_tlp_read_packet()  argument
298 	struct device *dev = &pcie->pdev->dev;  in s10_tlp_read_packet()
300 	for (count = 0; count < TLP_LOOP; count++) {  in s10_tlp_read_packet()
301 		ctrl = cra_readl(pcie, S10_RP_RXCPL_STATUS);  in s10_tlp_read_packet()
304 			dw[0] = cra_readl(pcie, S10_RP_RXCPL_REG);  in s10_tlp_read_packet()
319 		ctrl = cra_readl(pcie, S10_RP_RXCPL_STATUS);  in s10_tlp_read_packet()
320 		dw[count++] = cra_readl(pcie, S10_RP_RXCPL_REG);  in s10_tlp_read_packet()
339 static void tlp_write_packet(struct altera_pcie *pcie, u32 *headers,  in tlp_write_packet()  argument
344 	tlp_rp_regdata.reg0 = headers[0];  in tlp_write_packet()
347 	tlp_write_tx(pcie, &tlp_rp_regdata);  in tlp_write_packet()
351 		tlp_rp_regdata.reg1 = 0;  in tlp_write_packet()
352 		tlp_rp_regdata.ctrl = 0;  in tlp_write_packet()
353 		tlp_write_tx(pcie, &tlp_rp_regdata);  in tlp_write_packet()
356 		tlp_rp_regdata.reg1 = 0;  in tlp_write_packet()
363 	tlp_write_tx(pcie, &tlp_rp_regdata);  in tlp_write_packet()
366 static void s10_tlp_write_packet(struct altera_pcie *pcie, u32 *headers,  in s10_tlp_write_packet()  argument
369 	s10_tlp_write_tx(pcie, headers[0], RP_TX_SOP);  in s10_tlp_write_packet()
370 	s10_tlp_write_tx(pcie, headers[1], 0);  in s10_tlp_write_packet()
371 	s10_tlp_write_tx(pcie, headers[2], 0);  in s10_tlp_write_packet()
372 	s10_tlp_write_tx(pcie, data, RP_TX_EOP);  in s10_tlp_write_packet()
375 static void get_tlp_header(struct altera_pcie *pcie, u8 bus, u32 devfn,  in get_tlp_header()  argument
379 	u8 cfg0 = read ? pcie->pcie_data->cfgrd0 : pcie->pcie_data->cfgwr0;  in get_tlp_header()
380 	u8 cfg1 = read ? pcie->pcie_data->cfgrd1 : pcie->pcie_data->cfgwr1;  in get_tlp_header()
383 	if (pcie->pcie_data->version == ALTERA_PCIE_V1)  in get_tlp_header()
384 		cfg = (bus == pcie->root_bus_nr) ? cfg0 : cfg1;  in get_tlp_header()
386 		cfg = (bus > S10_RP_SECONDARY(pcie)) ? cfg0 : cfg1;  in get_tlp_header()
388 	headers[0] = TLP_CFG_DW0(pcie, cfg);  in get_tlp_header()
389 	headers[1] = TLP_CFG_DW1(pcie, tag, byte_en);  in get_tlp_header()
393 static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn,  in tlp_cfg_dword_read()  argument
398 	get_tlp_header(pcie, bus, devfn, where, byte_en, true,  in tlp_cfg_dword_read()
401 	pcie->pcie_data->ops->tlp_write_pkt(pcie, headers, 0, false);  in tlp_cfg_dword_read()
403 	return pcie->pcie_data->ops->tlp_read_pkt(pcie, value);  in tlp_cfg_dword_read()
406 static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn,  in tlp_cfg_dword_write()  argument
412 	get_tlp_header(pcie, bus, devfn, where, byte_en, false,  in tlp_cfg_dword_write()
416 	if ((where & 0x7) == 0)  in tlp_cfg_dword_write()
417 		pcie->pcie_data->ops->tlp_write_pkt(pcie, headers,  in tlp_cfg_dword_write()
420 		pcie->pcie_data->ops->tlp_write_pkt(pcie, headers,  in tlp_cfg_dword_write()
423 	ret = pcie->pcie_data->ops->tlp_read_pkt(pcie, NULL);  in tlp_cfg_dword_write()
431 	if ((bus == pcie->root_bus_nr) && (where == PCI_PRIMARY_BUS))  in tlp_cfg_dword_write()
432 		pcie->root_bus_nr = (u8)(value);  in tlp_cfg_dword_write()
437 static int s10_rp_read_cfg(struct altera_pcie *pcie, int where,  in s10_rp_read_cfg()  argument
440 	void __iomem *addr = S10_RP_CFG_ADDR(pcie, where);  in s10_rp_read_cfg()
457 static int s10_rp_write_cfg(struct altera_pcie *pcie, u8 busno,  in s10_rp_write_cfg()  argument
460 	void __iomem *addr = S10_RP_CFG_ADDR(pcie, where);  in s10_rp_write_cfg()
478 	if (busno == pcie->root_bus_nr && where == PCI_PRIMARY_BUS)  in s10_rp_write_cfg()
479 		pcie->root_bus_nr = value & 0xff;  in s10_rp_write_cfg()
484 static int aglx_rp_read_cfg(struct altera_pcie *pcie, int where,  in aglx_rp_read_cfg()  argument
487 	void __iomem *addr = AGLX_RP_CFG_ADDR(pcie, where);  in aglx_rp_read_cfg()
503 		*value = 0x01;  in aglx_rp_read_cfg()
504 	else if (where == PCI_INTERRUPT_LINE && !(*value & 0xff00))  in aglx_rp_read_cfg()
505 		*value |= 0x0100;  in aglx_rp_read_cfg()
510 static int aglx_rp_write_cfg(struct altera_pcie *pcie, u8 busno,  in aglx_rp_write_cfg()  argument
513 	void __iomem *addr = AGLX_RP_CFG_ADDR(pcie, where);  in aglx_rp_write_cfg()
531 	if (busno == pcie->root_bus_nr && where == PCI_PRIMARY_BUS)  in aglx_rp_write_cfg()
532 		pcie->root_bus_nr = value & 0xff;  in aglx_rp_write_cfg()
537 static int aglx_ep_write_cfg(struct altera_pcie *pcie, u8 busno,  in aglx_ep_write_cfg()  argument
540 	cra_writel(pcie, ((busno << 8) | devfn), AGLX_BDF_REG);  in aglx_ep_write_cfg()
541 	if (busno > AGLX_RP_SECONDARY(pcie))  in aglx_ep_write_cfg()
546 		cra_writeb(pcie, value, where);  in aglx_ep_write_cfg()
549 		cra_writew(pcie, value, where);  in aglx_ep_write_cfg()
552 		cra_writel(pcie, value, where);  in aglx_ep_write_cfg()
559 static int aglx_ep_read_cfg(struct altera_pcie *pcie, u8 busno,  in aglx_ep_read_cfg()  argument
562 	cra_writel(pcie, ((busno << 8) | devfn), AGLX_BDF_REG);  in aglx_ep_read_cfg()
563 	if (busno > AGLX_RP_SECONDARY(pcie))  in aglx_ep_read_cfg()
568 		*value = cra_readb(pcie, where);  in aglx_ep_read_cfg()
571 		*value = cra_readw(pcie, where);  in aglx_ep_read_cfg()
574 		*value = cra_readl(pcie, where);  in aglx_ep_read_cfg()
581 static int _altera_pcie_cfg_read(struct altera_pcie *pcie, u8 busno,  in _altera_pcie_cfg_read()  argument
589 	if (busno == pcie->root_bus_nr && pcie->pcie_data->ops->rp_read_cfg)  in _altera_pcie_cfg_read()
590 		return pcie->pcie_data->ops->rp_read_cfg(pcie, where,  in _altera_pcie_cfg_read()
593 	if (pcie->pcie_data->ops->ep_read_cfg)  in _altera_pcie_cfg_read()
594 		return pcie->pcie_data->ops->ep_read_cfg(pcie, busno, devfn,  in _altera_pcie_cfg_read()
605 		byte_en = 0xf;  in _altera_pcie_cfg_read()
609 	ret = tlp_cfg_dword_read(pcie, busno, devfn,  in _altera_pcie_cfg_read()
616 		*value = (data >> (8 * (where & 0x3))) & 0xff;  in _altera_pcie_cfg_read()
619 		*value = (data >> (8 * (where & 0x2))) & 0xffff;  in _altera_pcie_cfg_read()
629 static int _altera_pcie_cfg_write(struct altera_pcie *pcie, u8 busno,  in _altera_pcie_cfg_write()  argument
637 	if (busno == pcie->root_bus_nr && pcie->pcie_data->ops->rp_write_cfg)  in _altera_pcie_cfg_write()
638 		return pcie->pcie_data->ops->rp_write_cfg(pcie, busno,  in _altera_pcie_cfg_write()
641 	if (pcie->pcie_data->ops->ep_write_cfg)  in _altera_pcie_cfg_write()
642 		return pcie->pcie_data->ops->ep_write_cfg(pcie, busno, devfn,  in _altera_pcie_cfg_write()
647 		data32 = (value & 0xff) << shift;  in _altera_pcie_cfg_write()
651 		data32 = (value & 0xffff) << shift;  in _altera_pcie_cfg_write()
656 		byte_en = 0xf;  in _altera_pcie_cfg_write()
660 	return tlp_cfg_dword_write(pcie, busno, devfn, (where & ~DWORD_MASK),  in _altera_pcie_cfg_write()
667 	struct altera_pcie *pcie = bus->sysdata;  in altera_pcie_cfg_read()  local
672 	if (!altera_pcie_valid_device(pcie, bus, PCI_SLOT(devfn)))  in altera_pcie_cfg_read()
675 	return _altera_pcie_cfg_read(pcie, bus->number, devfn, where, size,  in altera_pcie_cfg_read()
682 	struct altera_pcie *pcie = bus->sysdata;  in altera_pcie_cfg_write()  local
687 	if (!altera_pcie_valid_device(pcie, bus, PCI_SLOT(devfn)))  in altera_pcie_cfg_write()
690 	return _altera_pcie_cfg_write(pcie, bus->number, devfn, where, size,  in altera_pcie_cfg_write()
699 static int altera_read_cap_word(struct altera_pcie *pcie, u8 busno,  in altera_read_cap_word()  argument
705 	ret = _altera_pcie_cfg_read(pcie, busno, devfn,  in altera_read_cap_word()
706 				    pcie->pcie_data->cap_offset + offset,  in altera_read_cap_word()
713 static int altera_write_cap_word(struct altera_pcie *pcie, u8 busno,  in altera_write_cap_word()  argument
716 	return _altera_pcie_cfg_write(pcie, busno, devfn,  in altera_write_cap_word()
717 				      pcie->pcie_data->cap_offset + offset,  in altera_write_cap_word()
722 static void altera_wait_link_retrain(struct altera_pcie *pcie)  in altera_wait_link_retrain()  argument
724 	struct device *dev = &pcie->pdev->dev;  in altera_wait_link_retrain()
731 		altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,  in altera_wait_link_retrain()
746 		if (pcie->pcie_data->ops->get_link_status(pcie))  in altera_wait_link_retrain()
757 static void altera_pcie_retrain(struct altera_pcie *pcie)  in altera_pcie_retrain()  argument
761 	if (!pcie->pcie_data->ops->get_link_status(pcie))  in altera_pcie_retrain()
765 	 * Set the retrain bit if the PCIe rootport support > 2.5GB/s, but  in altera_pcie_retrain()
768 	altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKCAP,  in altera_pcie_retrain()
773 	altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKSTA,  in altera_pcie_retrain()
776 		altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,  in altera_pcie_retrain()
779 		altera_write_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,  in altera_pcie_retrain()
782 		altera_wait_link_retrain(pcie);  in altera_pcie_retrain()
790 	irq_set_chip_data(irq, domain->host_data);  in altera_pcie_intx_map()
791 	return 0;  in altera_pcie_intx_map()
802 	struct altera_pcie *pcie;  in altera_pcie_isr()  local
809 	pcie = irq_desc_get_handler_data(desc);  in altera_pcie_isr()
810 	dev = &pcie->pdev->dev;  in altera_pcie_isr()
812 	while ((status = cra_readl(pcie, P2A_INT_STATUS)  in altera_pcie_isr()
813 		& P2A_INT_STS_ALL) != 0) {  in altera_pcie_isr()
816 			cra_writel(pcie, 1 << bit, P2A_INT_STATUS);  in altera_pcie_isr()
818 			ret = generic_handle_domain_irq(pcie->irq_domain, bit);  in altera_pcie_isr()
829 	struct altera_pcie *pcie;  in aglx_isr()  local
835 	pcie = irq_desc_get_handler_data(desc);  in aglx_isr()
836 	dev = &pcie->pdev->dev;  in aglx_isr()
838 	status = readl(pcie->hip_base + pcie->pcie_data->port_conf_offset +  in aglx_isr()
839 		       pcie->pcie_data->port_irq_status_offset);  in aglx_isr()
842 		writel(CFG_AER, (pcie->hip_base + pcie->pcie_data->port_conf_offset +  in aglx_isr()
843 				 pcie->pcie_data->port_irq_status_offset));  in aglx_isr()
845 		ret = generic_handle_domain_irq(pcie->irq_domain, 0);  in aglx_isr()
847 			dev_err_ratelimited(dev, "unexpected IRQ %d\n", pcie->irq);  in aglx_isr()
852 static int altera_pcie_init_irq_domain(struct altera_pcie *pcie)  in altera_pcie_init_irq_domain()  argument
854 	struct device *dev = &pcie->pdev->dev;  in altera_pcie_init_irq_domain()
857 	pcie->irq_domain = irq_domain_create_linear(dev_fwnode(dev), PCI_NUM_INTX,  in altera_pcie_init_irq_domain()
858 					&intx_domain_ops, pcie);  in altera_pcie_init_irq_domain()
859 	if (!pcie->irq_domain) {  in altera_pcie_init_irq_domain()
861 		return -ENOMEM;  in altera_pcie_init_irq_domain()
864 	return 0;  in altera_pcie_init_irq_domain()
867 static void altera_pcie_irq_teardown(struct altera_pcie *pcie)  in altera_pcie_irq_teardown()  argument
869 	irq_set_chained_handler_and_data(pcie->irq, NULL, NULL);  in altera_pcie_irq_teardown()
870 	irq_domain_remove(pcie->irq_domain);  in altera_pcie_irq_teardown()
871 	irq_dispose_mapping(pcie->irq);  in altera_pcie_irq_teardown()
874 static int altera_pcie_parse_dt(struct altera_pcie *pcie)  in altera_pcie_parse_dt()  argument
876 	struct platform_device *pdev = pcie->pdev;  in altera_pcie_parse_dt()
878 	pcie->cra_base = devm_platform_ioremap_resource_byname(pdev, "Cra");  in altera_pcie_parse_dt()
879 	if (IS_ERR(pcie->cra_base))  in altera_pcie_parse_dt()
880 		return PTR_ERR(pcie->cra_base);  in altera_pcie_parse_dt()
882 	if (pcie->pcie_data->version == ALTERA_PCIE_V2 ||  in altera_pcie_parse_dt()
883 	    pcie->pcie_data->version == ALTERA_PCIE_V3) {  in altera_pcie_parse_dt()
884 		pcie->hip_base = devm_platform_ioremap_resource_byname(pdev, "Hip");  in altera_pcie_parse_dt()
885 		if (IS_ERR(pcie->hip_base))  in altera_pcie_parse_dt()
886 			return PTR_ERR(pcie->hip_base);  in altera_pcie_parse_dt()
890 	pcie->irq = platform_get_irq(pdev, 0);  in altera_pcie_parse_dt()
891 	if (pcie->irq < 0)  in altera_pcie_parse_dt()
892 		return pcie->irq;  in altera_pcie_parse_dt()
894 	irq_set_chained_handler_and_data(pcie->irq, pcie->pcie_data->ops->rp_isr, pcie);  in altera_pcie_parse_dt()
895 	return 0;  in altera_pcie_parse_dt()
898 static void altera_pcie_host_init(struct altera_pcie *pcie)  in altera_pcie_host_init()  argument
900 	altera_pcie_retrain(pcie);  in altera_pcie_host_init()
930 	.cap_offset = 0x80,
941 	.cap_offset = 0x70,
951 	.cap_offset = 0x70,
952 	.port_conf_offset = 0x14000,
960 	.cap_offset = 0x70,
961 	.port_conf_offset = 0x104000,
969 	.cap_offset = 0x70,
970 	.port_conf_offset = 0x1300,
971 	.port_irq_status_offset = 0x0,
972 	.port_irq_enable_offset = 0x4,
976 	{.compatible = "altr,pcie-root-port-1.0",
978 	{.compatible = "altr,pcie-root-port-2.0",
980 	{.compatible = "altr,pcie-root-port-3.0-f-tile",
982 	{.compatible = "altr,pcie-root-port-3.0-p-tile",
984 	{.compatible = "altr,pcie-root-port-3.0-r-tile",
991 	struct device *dev = &pdev->dev;  in altera_pcie_probe()
992 	struct altera_pcie *pcie;  in altera_pcie_probe()  local
997 	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));  in altera_pcie_probe()
999 		return -ENOMEM;  in altera_pcie_probe()
1001 	pcie = pci_host_bridge_priv(bridge);  in altera_pcie_probe()
1002 	pcie->pdev = pdev;  in altera_pcie_probe()
1003 	platform_set_drvdata(pdev, pcie);  in altera_pcie_probe()
1005 	data = of_device_get_match_data(&pdev->dev);  in altera_pcie_probe()
1007 		return -ENODEV;  in altera_pcie_probe()
1009 	pcie->pcie_data = data;  in altera_pcie_probe()
1011 	ret = altera_pcie_parse_dt(pcie);  in altera_pcie_probe()
1017 	ret = altera_pcie_init_irq_domain(pcie);  in altera_pcie_probe()
1023 	if (pcie->pcie_data->version == ALTERA_PCIE_V1 ||  in altera_pcie_probe()
1024 	    pcie->pcie_data->version == ALTERA_PCIE_V2) {  in altera_pcie_probe()
1026 		cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS);  in altera_pcie_probe()
1028 		cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE);  in altera_pcie_probe()
1029 		altera_pcie_host_init(pcie);  in altera_pcie_probe()
1030 	} else if (pcie->pcie_data->version == ALTERA_PCIE_V3) {  in altera_pcie_probe()
1032 		       pcie->hip_base + pcie->pcie_data->port_conf_offset +  in altera_pcie_probe()
1033 		       pcie->pcie_data->port_irq_enable_offset);  in altera_pcie_probe()
1036 	bridge->sysdata = pcie;  in altera_pcie_probe()
1037 	bridge->busnr = pcie->root_bus_nr;  in altera_pcie_probe()
1038 	bridge->ops = &altera_pcie_ops;  in altera_pcie_probe()
1045 	struct altera_pcie *pcie = platform_get_drvdata(pdev);  in altera_pcie_remove()  local
1046 	struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);  in altera_pcie_remove()
1048 	pci_stop_root_bus(bridge->bus);  in altera_pcie_remove()
1049 	pci_remove_root_bus(bridge->bus);  in altera_pcie_remove()
1050 	altera_pcie_irq_teardown(pcie);  in altera_pcie_remove()
1057 		.name = "altera-pcie",
1064 MODULE_DESCRIPTION("Altera PCIe host controller driver");