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/linux/drivers/staging/media/atomisp/
H A DMakefile7 obj-$(CONFIG_VIDEO_ATOMISP) += pci/atomisp_gmin_platform.o
16 pci/atomisp_cmd.o \
17 pci/atomisp_compat_css20.o \
18 pci/atomisp_csi2.o \
19 pci/atomisp_csi2_bridge.o \
20 pci/atomisp_drvfs.o \
21 pci/atomisp_fops.o \
22 pci/atomisp_ioctl.o \
23 pci/atomisp_subdev.o \
24 pci/atomisp_v4l2.o \
[all …]
/linux/drivers/pci/controller/dwc/
H A Dpcie-designware.c25 #include "../../pci.h"
65 static int dw_pcie_get_clocks(struct dw_pcie *pci) in dw_pcie_get_clocks() argument
70 pci->app_clks[i].id = dw_pcie_app_clks[i]; in dw_pcie_get_clocks()
73 pci->core_clks[i].id = dw_pcie_core_clks[i]; in dw_pcie_get_clocks()
75 ret = devm_clk_bulk_get_optional(pci->dev, DW_PCIE_NUM_APP_CLKS, in dw_pcie_get_clocks()
76 pci->app_clks); in dw_pcie_get_clocks()
80 return devm_clk_bulk_get_optional(pci->dev, DW_PCIE_NUM_CORE_CLKS, in dw_pcie_get_clocks()
81 pci->core_clks); in dw_pcie_get_clocks()
84 static int dw_pcie_get_resets(struct dw_pcie *pci) in dw_pcie_get_resets() argument
89 pci->app_rsts[i].id = dw_pcie_app_rsts[i]; in dw_pcie_get_resets()
[all …]
H A Dpcie-designware-debugfs.c63 * @pci: Reference to the dw_pcie structure
69 struct dw_pcie *pci; member
189 struct dw_pcie *pci = file->private_data; in lane_detect_read() local
190 struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info; in lane_detect_read()
195 val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE_REG); in lane_detect_read()
208 struct dw_pcie *pci = file->private_data; in lane_detect_write() local
209 struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info; in lane_detect_write()
216 val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE_REG); in lane_detect_write()
219 dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE_REG, val); in lane_detect_write()
227 struct dw_pcie *pci = file->private_data; in rx_valid_read() local
[all …]
H A Dpcie-designware-host.c20 #include "../../pci.h"
44 .name = "PCI-MSI",
64 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); in dw_handle_msi_irq() local
69 status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS + in dw_handle_msi_irq()
106 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); in dw_pci_setup_msi_msg() local
116 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n", in dw_pci_setup_msi_msg()
123 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); in dw_pci_bottom_mask() local
134 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]); in dw_pci_bottom_mask()
142 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); in dw_pci_bottom_unmask() local
153 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]); in dw_pci_bottom_unmask()
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H A Dpci-layerscape-ep.c15 #include <linux/pci.h>
44 struct dw_pcie *pci; member
54 struct dw_pcie *pci = pcie->pci; in ls_pcie_pf_lut_readl() local
57 return ioread32be(pci->dbi_base + offset); in ls_pcie_pf_lut_readl()
59 return ioread32(pci->dbi_base + offset); in ls_pcie_pf_lut_readl()
64 struct dw_pcie *pci = pcie->pci; in ls_pcie_pf_lut_writel() local
67 iowrite32be(value, pci->dbi_base + offset); in ls_pcie_pf_lut_writel()
69 iowrite32(value, pci->dbi_base + offset); in ls_pcie_pf_lut_writel()
75 struct dw_pcie *pci = pcie->pci; in ls_pcie_ep_event_handler() local
87 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); in ls_pcie_ep_event_handler()
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H A Dpcie-designware-ep.c15 #include <linux/pci-epc.h>
16 #include <linux/pci-epf.h>
39 static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, u8 func_no, in __dw_pcie_ep_reset_bar() argument
42 struct dw_pcie_ep *ep = &pci->ep; in __dw_pcie_ep_reset_bar()
46 dw_pcie_dbi_ro_wr_en(pci); in __dw_pcie_ep_reset_bar()
53 dw_pcie_dbi_ro_wr_dis(pci); in __dw_pcie_ep_reset_bar()
58 * @pci: DWC PCI device
61 void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar) in dw_pcie_ep_reset_bar() argument
65 funcs = pci->ep.epc->max_functions; in dw_pcie_ep_reset_bar()
68 __dw_pcie_ep_reset_bar(pci, func_no, bar, 0); in dw_pcie_ep_reset_bar()
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H A Dpcie-armada8k.c19 #include <linux/pci.h>
30 struct dw_pcie *pci; member
112 struct dw_pcie *pci = pcie->pci; in armada8k_pcie_setup_phys() local
113 struct device *dev = pci->dev; in armada8k_pcie_setup_phys()
142 static bool armada8k_pcie_link_up(struct dw_pcie *pci) in armada8k_pcie_link_up() argument
147 reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_STATUS_REG); in armada8k_pcie_link_up()
152 dev_dbg(pci->dev, "No link detected (Global-Status: 0x%08x).\n", reg); in armada8k_pcie_link_up()
156 static int armada8k_pcie_start_link(struct dw_pcie *pci) in armada8k_pcie_start_link() argument
161 reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); in armada8k_pcie_start_link()
163 dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); in armada8k_pcie_start_link()
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H A Dpcie-designware.h22 #include <linux/pci.h>
25 #include <linux/pci-epc.h>
26 #include <linux/pci-epf.h>
28 #include "../../pci.h"
547 int dw_pcie_get_resources(struct dw_pcie *pci);
549 void dw_pcie_version_detect(struct dw_pcie *pci);
551 u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap);
552 u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap);
553 u16 dw_pcie_find_rasdes_capability(struct dw_pcie *pci);
554 u16 dw_pcie_find_ptm_capability(struct dw_pcie *pci);
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/linux/drivers/edac/
H A Dedac_pci.c3 * EDAC PCI component
31 struct edac_pci_ctl_info *pci; in edac_pci_alloc_ctl_info() local
35 pci = kzalloc(sizeof(struct edac_pci_ctl_info), GFP_KERNEL); in edac_pci_alloc_ctl_info()
36 if (!pci) in edac_pci_alloc_ctl_info()
40 pci->pvt_info = kzalloc(sz_pvt, GFP_KERNEL); in edac_pci_alloc_ctl_info()
41 if (!pci->pvt_info) in edac_pci_alloc_ctl_info()
45 pci->op_state = OP_ALLOC; in edac_pci_alloc_ctl_info()
47 snprintf(pci->name, strlen(edac_pci_name) + 1, "%s", edac_pci_name); in edac_pci_alloc_ctl_info()
49 return pci; in edac_pci_alloc_ctl_info()
52 kfree(pci); in edac_pci_alloc_ctl_info()
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H A Dedac_pci_sysfs.c20 static int check_pci_errors; /* default NO check PCI parity */
21 static int edac_pci_panic_on_pe; /* default NO panic on PCI Parity */
22 static int edac_pci_log_pe = 1; /* log PCI parity errors */
23 static int edac_pci_log_npe = 1; /* log PCI non-parity error errors */
58 /**************************** EDAC PCI sysfs instance *******************/
59 static ssize_t instance_pe_count_show(struct edac_pci_ctl_info *pci, char *data) in instance_pe_count_show() argument
61 return sprintf(data, "%u\n", atomic_read(&pci->counters.pe_count)); in instance_pe_count_show()
64 static ssize_t instance_npe_count_show(struct edac_pci_ctl_info *pci, in instance_npe_count_show() argument
67 return sprintf(data, "%u\n", atomic_read(&pci->counters.npe_count)); in instance_npe_count_show()
76 struct edac_pci_ctl_info *pci; in edac_pci_instance_release() local
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H A Docteon_edac-pci.c18 #include <asm/octeon/cvmx-pci-defs.h>
23 static void octeon_pci_poll(struct edac_pci_ctl_info *pci) in octeon_pci_poll() argument
29 edac_pci_handle_pe(pci, pci->ctl_name); in octeon_pci_poll()
34 edac_pci_handle_npe(pci, "Signaled System Error"); in octeon_pci_poll()
39 edac_pci_handle_npe(pci, "Received Master Abort"); in octeon_pci_poll()
44 edac_pci_handle_npe(pci, "Received Target Abort"); in octeon_pci_poll()
49 edac_pci_handle_npe(pci, "Signaled Target Abort"); in octeon_pci_poll()
54 edac_pci_handle_npe(pci, "Master Data Parity Error"); in octeon_pci_poll()
62 struct edac_pci_ctl_info *pci; in octeon_pci_probe() local
65 pci = edac_pci_alloc_ctl_info(0, "octeon_pci_err"); in octeon_pci_probe()
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/linux/drivers/pci/
H A DKconfig3 # PCI configuration
6 # select this to offer the PCI prompt
10 # select this to unconditionally force on PCI support
14 select PCI
16 # select this to provide a generic PCI iomap,
17 # without PCI itself having to be defined
21 menuconfig PCI config
22 bool "PCI support"
26 This option enables support for the PCI local bus, including
27 support for PCI-X and the foundations for PCI Express support.
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H A Dsearch.c3 * PCI searching functions
11 #include <linux/pci.h>
15 #include "pci.h"
37 * requester is on another PCI bus. in pci_for_each_dma_alias()
74 * PCIe-to-PCI/X bridges alias transactions from downstream in pci_for_each_dma_alias()
75 * devices using the subordinate bus number (PCI Express to in pci_for_each_dma_alias()
76 * PCI/PCI-X Bridge Spec, rev 1.0, sec 2.3). For all cases in pci_for_each_dma_alias()
77 * where the upstream bus is PCI/X we alias to the bridge in pci_for_each_dma_alias()
80 * when the secondary interface is PCI-X). in pci_for_each_dma_alias()
133 * pci_find_bus - locate PCI bus from a given domain and bus number
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/linux/drivers/pinctrl/
H A Dpinctrl-rk805.c316 struct rk805_pctrl_info *pci = gpiochip_get_data(chip); in rk805_gpio_get() local
319 ret = regmap_read(pci->rk808->regmap, pci->pin_cfg[offset].reg, &val); in rk805_gpio_get()
321 dev_err(pci->dev, "get gpio%d value failed\n", offset); in rk805_gpio_get()
325 return !!(val & pci->pin_cfg[offset].val_msk); in rk805_gpio_get()
331 struct rk805_pctrl_info *pci = gpiochip_get_data(chip); in rk805_gpio_set() local
333 return regmap_update_bits(pci->rk808->regmap, in rk805_gpio_set()
334 pci->pin_cfg[offset].reg, in rk805_gpio_set()
335 pci->pin_cfg[offset].val_msk, in rk805_gpio_set()
336 value ? pci->pin_cfg[offset].val_msk : 0); in rk805_gpio_set()
353 struct rk805_pctrl_info *pci = gpiochip_get_data(chip); in rk805_gpio_get_direction() local
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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/pci/
H A Dpcie.c51 nvkm_pcie_get_version(struct nvkm_pci *pci) in nvkm_pcie_get_version() argument
53 if (!pci->func->pcie.version) in nvkm_pcie_get_version()
56 return pci->func->pcie.version(pci); in nvkm_pcie_get_version()
60 nvkm_pcie_get_max_version(struct nvkm_pci *pci) in nvkm_pcie_get_max_version() argument
62 if (!pci->func->pcie.version_supported) in nvkm_pcie_get_max_version()
65 return pci->func->pcie.version_supported(pci); in nvkm_pcie_get_max_version()
69 nvkm_pcie_set_version(struct nvkm_pci *pci, int version) in nvkm_pcie_set_version() argument
71 if (!pci->func->pcie.set_version) in nvkm_pcie_set_version()
74 nvkm_trace(&pci->subdev, "set to version %i\n", version); in nvkm_pcie_set_version()
75 pci->func->pcie.set_version(pci, version); in nvkm_pcie_set_version()
[all …]
H A Dagp.c38 /* SiS 761 does not support AGP cards, use PCI mode */
44 nvkm_agp_fini(struct nvkm_pci *pci) in nvkm_agp_fini() argument
46 if (pci->agp.acquired) { in nvkm_agp_fini()
47 agp_backend_release(pci->agp.bridge); in nvkm_agp_fini()
48 pci->agp.acquired = false; in nvkm_agp_fini()
56 nvkm_agp_preinit(struct nvkm_pci *pci) in nvkm_agp_preinit() argument
58 struct nvkm_device *device = pci->subdev.device; in nvkm_agp_preinit()
59 u32 mode = nvkm_pci_rd32(pci, 0x004c); in nvkm_agp_preinit()
66 if ((mode | pci->agp.mode) & PCI_AGP_COMMAND_FW) { in nvkm_agp_preinit()
67 mode = pci->agp.mode & ~PCI_AGP_COMMAND_FW; in nvkm_agp_preinit()
[all …]
/linux/drivers/comedi/
H A DKconfig427 tristate "Intelligent Instruments PCI-20001C carrier support"
430 Enable support for Intelligent Instruments PCI-20001C carrier
431 PCI-20001, PCI-20006 and PCI-20341
567 tristate "Comedi PCI drivers"
568 depends on PCI
570 Enable support for comedi PCI drivers.
578 tristate "Generic PCI based 8255 digital i/o board support"
581 Enable support for PCI based 8255 digital i/o boards. This driver
582 provides a PCI wrapper around the generic 8255 driver.
585 ADlink - PCI-7224, PCI-7248, and PCI-7296
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/linux/sound/soc/intel/atom/sst/
H A Dsst_pci.c3 * sst_pci.c - SST (LPE) driver init file for pci enumeration.
15 #include <linux/pci.h>
27 struct pci_dev *pci = ctx->pci; in sst_platform_get_resources() local
29 ret = pcim_request_all_regions(pci, SST_DRV_NAME); in sst_platform_get_resources()
36 ctx->ddr_base = pci_resource_start(pci, 0); in sst_platform_get_resources()
48 ctx->ddr_end = pci_resource_end(pci, 0); in sst_platform_get_resources()
50 ctx->ddr = pcim_iomap(pci, 0, 0); in sst_platform_get_resources()
59 ctx->shim_phy_add = pci_resource_start(pci, 1); in sst_platform_get_resources()
60 ctx->shim = pcim_iomap(pci, 1, 0); in sst_platform_get_resources()
67 ctx->mailbox_add = pci_resource_start(pci, 2); in sst_platform_get_resources()
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/linux/drivers/scsi/qla2xxx/
H A Dqla_devtbl.h8 "QLA2340", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x100 */
9 "QLA2342", "133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x101 */
10 "QLA2344", "133MHz PCI-X to 2Gb FC, Quad Channel", /* 0x102 */
14 "QLA2310", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x106 */
15 "QLA2332", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x107 */
18 "QLA2342", "Sun 133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x10a */
20 "QLA2350", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x10c */
21 "QLA2352", "133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x10d */
22 "QLA2352", "Sun 133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x10e */
29 "QLA2360", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x115 */
[all …]
/linux/arch/mips/pci/
H A DMakefile3 # Makefile for the PCI specific kernel interface routines under Linux.
6 obj-y += pci.o
7 obj-$(CONFIG_PCI_DRIVERS_LEGACY)+= pci-legacy.o
8 obj-$(CONFIG_PCI_DRIVERS_GENERIC)+= pci-generic.o
11 # PCI bus host bridge specific code
17 obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
18 obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \
20 obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o
21 obj-$(CONFIG_PCI_AR2315) += pci-ar2315.o
22 obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o
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/linux/Documentation/scsi/
H A Daic7xxx.rst27 aic7850 10 PCI/32 10MHz 8Bit 3
28 aic7855 10 PCI/32 10MHz 8Bit 3
29 aic7856 10 PCI/32 10MHz 8Bit 3
30 aic7859 10 PCI/32 20MHz 8Bit 3
31 aic7860 10 PCI/32 20MHz 8Bit 3
32 aic7870 10 PCI/32 10MHz 16Bit 16
33 aic7880 10 PCI/32 20MHz 16Bit 16
34 aic7890 20 PCI/32 40MHz 16Bit 16 3 4 5 6 7 8
35 aic7891 20 PCI/64 40MHz 16Bit 16 3 4 5 6 7 8
36 aic7892 20 PCI/64-66 80MHz 16Bit 16 3 4 5 6 7 8
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/linux/include/linux/ssb/
H A Dssb_driver_pci.h12 /* PCI core registers. */
13 #define SSB_PCICORE_CTL 0x0000 /* PCI Control */
18 #define SSB_PCICORE_ARBCTL 0x0010 /* PCI Arbiter Control */
27 #define SSB_PCICORE_ISTAT_INTA 0x00000001 /* PCI INTA# */
28 #define SSB_PCICORE_ISTAT_INTB 0x00000002 /* PCI INTB# */
29 #define SSB_PCICORE_ISTAT_SERR 0x00000004 /* PCI SERR# (write to clear) */
30 #define SSB_PCICORE_ISTAT_PERR 0x00000008 /* PCI PERR# (write to clear) */
31 #define SSB_PCICORE_ISTAT_PME 0x00000010 /* PCI PME# */
33 #define SSB_PCICORE_IMASK_INTA 0x00000001 /* PCI INTA# */
34 #define SSB_PCICORE_IMASK_INTB 0x00000002 /* PCI INTB# */
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/linux/Documentation/networking/devlink/
H A Ddevlink-port.rst32 - This indicates an eswitch port representing a port of PCI
35 - This indicates an eswitch port representing a port of PCI
38 - This indicates an eswitch port representing a port of PCI
41 - This indicates a virtual port for the PCI virtual function.
60 PCI controllers
62 In most cases a PCI device has only one controller. A controller consists of
67 A PCI device connected to multiple CPUs or multiple PCI root complexes or a
70 An eswitch is on the PCI device which supports ports of multiple controllers.
79 | pci rc |=== | pf0 |______/________/ | pf1 |___/_______/ |
98 | pci rc |==| ------- ----/---- ---/----- ------- ---/--- ---/--- |
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,orion-pinctrl.txt24 mpp0 0 pcie(rstout), pci(req2), gpio
25 mpp1 1 gpio, pci(gnt2)
26 mpp2 2 gpio, pci(req3), pci-1(pme)
27 mpp3 3 gpio, pci(gnt3)
28 mpp4 4 gpio, pci(req4)
29 mpp5 5 gpio, pci(gnt4)
30 mpp6 6 gpio, pci(req5), pci-1(clk)
31 mpp7 7 gpio, pci(gnt5), pci-1(clk)
49 mpp0 0 pcie(rstout), pci(req2), gpio
50 mpp1 1 gpio, pci(gnt2)
[all …]
/linux/Documentation/virt/hyperv/
H A Dvpci.rst3 PCI pass-thru devices
5 In a Hyper-V guest VM, PCI pass-thru devices (also called
6 virtual PCI devices, or vPCI devices) are physical PCI devices
35 Hyper-V provides full PCI functionality for a vPCI device when
38 APIs for accessing PCI config space and for other integration
39 with Linux. But the initial detection of the PCI device and
40 its integration with the Linux PCI subsystem must use Hyper-V
46 drivers/pci/controller/pci-hyperv.c handles a newly introduced
47 vPCI device by fabricating a PCI bus topology and creating all
48 the normal PCI device data structures in Linux that would
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