17328c8f4SBjorn Helgaas# SPDX-License-Identifier: GPL-2.0 21da177e4SLinus Torvalds# 31da177e4SLinus Torvalds# PCI configuration 41da177e4SLinus Torvalds# 55f8fc432SBogicevic Sasa 6eb01d42aSChristoph Hellwig# select this to offer the PCI prompt 7eb01d42aSChristoph Hellwigconfig HAVE_PCI 8eb01d42aSChristoph Hellwig bool 9eb01d42aSChristoph Hellwig 10eb01d42aSChristoph Hellwig# select this to unconditionally force on PCI support 11eb01d42aSChristoph Hellwigconfig FORCE_PCI 12eb01d42aSChristoph Hellwig bool 13eb01d42aSChristoph Hellwig select HAVE_PCI 14eb01d42aSChristoph Hellwig select PCI 15eb01d42aSChristoph Hellwig 16ae874027SPhilipp Stanner# select this to provide a generic PCI iomap, 17ae874027SPhilipp Stanner# without PCI itself having to be defined 18ae874027SPhilipp Stannerconfig GENERIC_PCI_IOMAP 19ae874027SPhilipp Stanner bool 20ae874027SPhilipp Stanner 21eb01d42aSChristoph Hellwigmenuconfig PCI 22eb01d42aSChristoph Hellwig bool "PCI support" 23eb01d42aSChristoph Hellwig depends on HAVE_PCI 248fe743b5SArnd Bergmann depends on MMU 25eb01d42aSChristoph Hellwig help 26eb01d42aSChristoph Hellwig This option enables support for the PCI local bus, including 27eb01d42aSChristoph Hellwig support for PCI-X and the foundations for PCI Express support. 28eb01d42aSChristoph Hellwig Say 'Y' here unless you know what you are doing. 29eb01d42aSChristoph Hellwig 302e8cb2cfSRob Herringif PCI 312e8cb2cfSRob Herring 322eac9c2dSChristoph Hellwigconfig PCI_DOMAINS 332eac9c2dSChristoph Hellwig bool 342eac9c2dSChristoph Hellwig depends on PCI 352eac9c2dSChristoph Hellwig 362eac9c2dSChristoph Hellwigconfig PCI_DOMAINS_GENERIC 372eac9c2dSChristoph Hellwig bool 382eac9c2dSChristoph Hellwig select PCI_DOMAINS 392eac9c2dSChristoph Hellwig 4020f1b79dSChristoph Hellwigconfig PCI_SYSCALL 4120f1b79dSChristoph Hellwig bool 4220f1b79dSChristoph Hellwig 435f8fc432SBogicevic Sasasource "drivers/pci/pcie/Kconfig" 445f8fc432SBogicevic Sasa 451da177e4SLinus Torvaldsconfig PCI_MSI 461da177e4SLinus Torvalds bool "Message Signaled Interrupts (MSI and MSI-X)" 4738b6a1cfSJiang Liu select GENERIC_MSI_IRQ 481da177e4SLinus Torvalds help 491da177e4SLinus Torvalds This allows device drivers to enable MSI (Message Signaled 501da177e4SLinus Torvalds Interrupts). Message Signaled Interrupts enable a device to 511da177e4SLinus Torvalds generate an interrupt using an inbound Memory Write on its 521da177e4SLinus Torvalds PCI bus instead of asserting a device IRQ pin. 531da177e4SLinus Torvalds 54309e57dfSMatthew Wilcox Use of PCI MSI interrupts can be disabled at kernel boot time 55309e57dfSMatthew Wilcox by using the 'pci=nomsi' option. This disables MSI for the 56309e57dfSMatthew Wilcox entire system. 57309e57dfSMatthew Wilcox 583196180aSJesse Barnes If you don't know what to do here, say Y. 591da177e4SLinus Torvalds 60077ee78eSThomas Gleixnerconfig PCI_MSI_ARCH_FALLBACKS 61077ee78eSThomas Gleixner bool 62077ee78eSThomas Gleixner 6303ea2263SRandy Dunlapconfig PCI_QUIRKS 6403ea2263SRandy Dunlap default y 6503ea2263SRandy Dunlap bool "Enable PCI quirk workarounds" if EXPERT 6603ea2263SRandy Dunlap help 6703ea2263SRandy Dunlap This enables workarounds for various PCI chipset bugs/quirks. 6803ea2263SRandy Dunlap Disable this only if your target machine is unaffected by PCI 6903ea2263SRandy Dunlap quirks. 7003ea2263SRandy Dunlap 711da177e4SLinus Torvaldsconfig PCI_DEBUG 721da177e4SLinus Torvalds bool "PCI Debugging" 732e8cb2cfSRob Herring depends on DEBUG_KERNEL 741da177e4SLinus Torvalds help 751da177e4SLinus Torvalds Say Y here if you want the PCI core to produce a bunch of debug 761da177e4SLinus Torvalds messages to the system log. Select this if you are having a 771da177e4SLinus Torvalds problem with PCI support and want to see more of what is going on. 781da177e4SLinus Torvalds 791da177e4SLinus Torvalds When in doubt, say N. 801da177e4SLinus Torvalds 81b07f2ebcSYinghai Luconfig PCI_REALLOC_ENABLE_AUTO 82b07f2ebcSYinghai Lu bool "Enable PCI resource re-allocation detection" 83ad581f86SSascha El-Sharkawy depends on PCI_IOV 84b07f2ebcSYinghai Lu help 85b07f2ebcSYinghai Lu Say Y here if you want the PCI core to detect if PCI resource 86b07f2ebcSYinghai Lu re-allocation needs to be enabled. You can always use pci=realloc=on 87ad581f86SSascha El-Sharkawy or pci=realloc=off to override it. It will automatically 88ad581f86SSascha El-Sharkawy re-allocate PCI resources if SR-IOV BARs have not been allocated by 89ad581f86SSascha El-Sharkawy the BIOS. 90b07f2ebcSYinghai Lu 91b07f2ebcSYinghai Lu When in doubt, say N. 92b07f2ebcSYinghai Lu 93c70e0d9dSChris Wrightconfig PCI_STUB 94c70e0d9dSChris Wright tristate "PCI Stub driver" 95c70e0d9dSChris Wright help 96c70e0d9dSChris Wright Say Y or M here if you want be able to reserve a PCI device 97c70e0d9dSChris Wright when it is going to be assigned to a guest operating system. 98c70e0d9dSChris Wright 99c70e0d9dSChris Wright When in doubt, say N. 100c70e0d9dSChris Wright 101a8ccf8a6SAlexander Duyckconfig PCI_PF_STUB 102a8ccf8a6SAlexander Duyck tristate "PCI PF Stub driver" 103a8ccf8a6SAlexander Duyck depends on PCI_IOV 104a8ccf8a6SAlexander Duyck help 105a8ccf8a6SAlexander Duyck Say Y or M here if you want to enable support for devices that 1064a57f58fSRandy Dunlap require SR-IOV support, while at the same time the PF (Physical 1074a57f58fSRandy Dunlap Function) itself is not providing any actual services on the 1084a57f58fSRandy Dunlap host itself such as storage or networking. 109a8ccf8a6SAlexander Duyck 110a8ccf8a6SAlexander Duyck When in doubt, say N. 111a8ccf8a6SAlexander Duyck 112956a9202SRyan Wilsonconfig XEN_PCIDEV_FRONTEND 113956a9202SRyan Wilson tristate "Xen PCI Frontend" 114e243ae95SJan Beulich depends on XEN_PV 115956a9202SRyan Wilson select PCI_XEN 116fce263c1SKonrad Rzeszutek Wilk select XEN_XENBUS_FRONTEND 117956a9202SRyan Wilson default y 118956a9202SRyan Wilson help 119956a9202SRyan Wilson The PCI device frontend driver allows the kernel to import arbitrary 120956a9202SRyan Wilson PCI devices from a PCI backend to support PCI driver domains. 121956a9202SRyan Wilson 122db3c33c6SJoerg Roedelconfig PCI_ATS 123db3c33c6SJoerg Roedel bool 124db3c33c6SJoerg Roedel 125f16469eeSDan Williamsconfig PCI_IDE 126f16469eeSDan Williams bool 127f16469eeSDan Williams 128*3225f52cSDan Williamsconfig PCI_TSM 129*3225f52cSDan Williams bool "PCI TSM: Device security protocol support" 130*3225f52cSDan Williams select PCI_IDE 131*3225f52cSDan Williams select PCI_DOE 132*3225f52cSDan Williams select TSM 133*3225f52cSDan Williams help 134*3225f52cSDan Williams The TEE (Trusted Execution Environment) Device Interface 135*3225f52cSDan Williams Security Protocol (TDISP) defines a "TSM" as a platform agent 136*3225f52cSDan Williams that manages device authentication, link encryption, link 137*3225f52cSDan Williams integrity protection, and assignment of PCI device functions 138*3225f52cSDan Williams (virtual or physical) to confidential computing VMs that can 139*3225f52cSDan Williams access (DMA) guest private memory. 140*3225f52cSDan Williams 141*3225f52cSDan Williams Enable a platform TSM driver to use this capability. 142*3225f52cSDan Williams 1439d24322eSJonathan Cameronconfig PCI_DOE 1446fc6ded5SAlistair Francis bool "Enable PCI Data Object Exchange (DOE) support" 1456fc6ded5SAlistair Francis help 1466fc6ded5SAlistair Francis Say Y here if you want be able to communicate with PCIe DOE 1476fc6ded5SAlistair Francis mailboxes. 1489d24322eSJonathan Cameron 14935ff9477SJayachandran Cconfig PCI_ECAM 15035ff9477SJayachandran C bool 15135ff9477SJayachandran C 152714fe383SThomas Gleixnerconfig PCI_LOCKLESS_CONFIG 153714fe383SThomas Gleixner bool 154714fe383SThomas Gleixner 15523a5fba4SThomas Petazzoniconfig PCI_BRIDGE_EMUL 15623a5fba4SThomas Petazzoni bool 15723a5fba4SThomas Petazzoni 158d1b054daSYu Zhaoconfig PCI_IOV 159d1b054daSYu Zhao bool "PCI IOV support" 160db3c33c6SJoerg Roedel select PCI_ATS 161d1b054daSYu Zhao help 162d1b054daSYu Zhao I/O Virtualization is a PCI feature supported by some devices 163d1b054daSYu Zhao which allows them to create virtual devices which share their 164d1b054daSYu Zhao physical resources. 165d1b054daSYu Zhao 166d1b054daSYu Zhao If unsure, say N. 167204d49a5SBjorn Helgaas 1684e893545SMariusz Tkaczykconfig PCI_NPEM 1694e893545SMariusz Tkaczyk bool "Native PCIe Enclosure Management" 1704e893545SMariusz Tkaczyk depends on LEDS_CLASS=y 1714e893545SMariusz Tkaczyk help 1724e893545SMariusz Tkaczyk Support for Native PCIe Enclosure Management. It allows managing LED 1734e893545SMariusz Tkaczyk indications in storage enclosures. Enclosure must support following 1744e893545SMariusz Tkaczyk indications: OK, Locate, Fail, Rebuild, other indications are 1754e893545SMariusz Tkaczyk optional. 1764e893545SMariusz Tkaczyk 177c320b976SJoerg Roedelconfig PCI_PRI 178c320b976SJoerg Roedel bool "PCI PRI support" 179c320b976SJoerg Roedel select PCI_ATS 180c320b976SJoerg Roedel help 181c320b976SJoerg Roedel PRI is the PCI Page Request Interface. It allows PCI devices that are 182c320b976SJoerg Roedel behind an IOMMU to recover from page faults. 183c320b976SJoerg Roedel 184c320b976SJoerg Roedel If unsure, say N. 185c320b976SJoerg Roedel 186086ac11fSJoerg Roedelconfig PCI_PASID 187086ac11fSJoerg Roedel bool "PCI PASID support" 188086ac11fSJoerg Roedel select PCI_ATS 189086ac11fSJoerg Roedel help 190086ac11fSJoerg Roedel Process Address Space Identifiers (PASIDs) can be used by PCI devices 191086ac11fSJoerg Roedel to access more than one IO address space at the same time. To make 192086ac11fSJoerg Roedel use of this feature an IOMMU is required which also supports PASIDs. 193086ac11fSJoerg Roedel Select this option if you have such an IOMMU and want to compile the 194086ac11fSJoerg Roedel driver for it into your kernel. 195086ac11fSJoerg Roedel 196086ac11fSJoerg Roedel If unsure, say N. 197086ac11fSJoerg Roedel 198f69767a1SWei Huangconfig PCIE_TPH 199f69767a1SWei Huang bool "TLP Processing Hints" 200f69767a1SWei Huang help 201f69767a1SWei Huang This option adds support for PCIe TLP Processing Hints (TPH). 202f69767a1SWei Huang TPH allows endpoint devices to provide optimization hints, such as 203f69767a1SWei Huang desired caching behavior, for requests that target memory space. 204f69767a1SWei Huang These hints, called Steering Tags, can empower the system hardware 205f69767a1SWei Huang to optimize the utilization of platform resources. 206f69767a1SWei Huang 20752916982SLogan Gunthorpeconfig PCI_P2PDMA 20852916982SLogan Gunthorpe bool "PCI peer-to-peer transfer support" 2092e8cb2cfSRob Herring depends on ZONE_DEVICE 21042399301SLogan Gunthorpe # 21142399301SLogan Gunthorpe # The need for the scatterlist DMA bus address flag means PCI P2PDMA 21242399301SLogan Gunthorpe # requires 64bit 21342399301SLogan Gunthorpe # 21442399301SLogan Gunthorpe depends on 64BIT 21552916982SLogan Gunthorpe select GENERIC_ALLOCATOR 216af2880ecSRobin Murphy select NEED_SG_DMA_FLAGS 21752916982SLogan Gunthorpe help 21843b0294aSLiu Song Enables drivers to do PCI peer-to-peer transactions to and from 21952916982SLogan Gunthorpe BARs that are exposed in other devices that are the part of 22052916982SLogan Gunthorpe the hierarchy where peer-to-peer DMA is guaranteed by the PCI 22152916982SLogan Gunthorpe specification to work (ie. anything below a single PCI bridge). 22252916982SLogan Gunthorpe 22352916982SLogan Gunthorpe Many PCIe root complexes do not support P2P transactions and 22452916982SLogan Gunthorpe it's hard to tell which support it at all, so at this time, 225d1bbf38aSBjorn Helgaas P2P DMA transactions must be between devices behind the same root 22652916982SLogan Gunthorpe port. 22752916982SLogan Gunthorpe 22852916982SLogan Gunthorpe If unsure, say N. 22952916982SLogan Gunthorpe 2308a226e00SRandy Dunlapconfig PCI_LABEL 2318a226e00SRandy Dunlap def_bool y if (DMI || ACPI) 2328a226e00SRandy Dunlap select NLS 23345361a4fSThomas Petazzoni 2344daace0dSJake Oshinsconfig PCI_HYPERV 2354daace0dSJake Oshins tristate "Hyper-V PCI Frontend" 23694b04355SMukesh Rathor depends on ((X86 && X86_64) || ARM64) && HYPERV_VMBUS && PCI_MSI && SYSFS 237348dd93eSHaiyang Zhang select PCI_HYPERV_INTERFACE 2385f83d633SNam Cao select IRQ_MSI_LIB 2394daace0dSJake Oshins help 2404daace0dSJake Oshins The PCI device frontend driver allows the kernel to import arbitrary 2414daace0dSJake Oshins PCI devices from a PCI backend to support PCI driver domains. 2424daace0dSJake Oshins 243407d1a51SLizhi Houconfig PCI_DYNAMIC_OF_NODES 244407d1a51SLizhi Hou bool "Create Device tree nodes for PCI devices" 24526641b3fSLizhi Hou depends on OF_IRQ 246407d1a51SLizhi Hou select OF_DYNAMIC 247407d1a51SLizhi Hou help 248407d1a51SLizhi Hou This option enables support for generating device tree nodes for some 249407d1a51SLizhi Hou PCI devices. Thus, the driver of this kind can load and overlay 250407d1a51SLizhi Hou flattened device tree for its downstream devices. 251407d1a51SLizhi Hou 252407d1a51SLizhi Hou Once this option is selected, the device tree nodes will be generated 253407d1a51SLizhi Hou for all PCI bridges. 254407d1a51SLizhi Hou 255b0e85c3cSJim Quinlanchoice 256b0e85c3cSJim Quinlan prompt "PCI Express hierarchy optimization setting" 257b0e85c3cSJim Quinlan default PCIE_BUS_DEFAULT 258b0e85c3cSJim Quinlan depends on PCI && EXPERT 259b0e85c3cSJim Quinlan help 260b0e85c3cSJim Quinlan MPS (Max Payload Size) and MRRS (Max Read Request Size) are PCIe 261b0e85c3cSJim Quinlan device parameters that affect performance and the ability to 262b0e85c3cSJim Quinlan support hotplug and peer-to-peer DMA. 263b0e85c3cSJim Quinlan 264b0e85c3cSJim Quinlan The following choices set the MPS and MRRS optimization strategy 265b0e85c3cSJim Quinlan at compile-time. The choices are the same as those offered for 266b0e85c3cSJim Quinlan the kernel command-line parameter 'pci', i.e., 267b0e85c3cSJim Quinlan 'pci=pcie_bus_tune_off', 'pci=pcie_bus_safe', 268b0e85c3cSJim Quinlan 'pci=pcie_bus_perf', and 'pci=pcie_bus_peer2peer'. 269b0e85c3cSJim Quinlan 270b0e85c3cSJim Quinlan This is a compile-time setting and can be overridden by the above 271b0e85c3cSJim Quinlan command-line parameters. If unsure, choose PCIE_BUS_DEFAULT. 272b0e85c3cSJim Quinlan 273b0e85c3cSJim Quinlanconfig PCIE_BUS_TUNE_OFF 274b0e85c3cSJim Quinlan bool "Tune Off" 275b0e85c3cSJim Quinlan depends on PCI 276b0e85c3cSJim Quinlan help 277b0e85c3cSJim Quinlan Use the BIOS defaults; don't touch MPS at all. This is the same 278b0e85c3cSJim Quinlan as booting with 'pci=pcie_bus_tune_off'. 279b0e85c3cSJim Quinlan 280b0e85c3cSJim Quinlanconfig PCIE_BUS_DEFAULT 281b0e85c3cSJim Quinlan bool "Default" 282b0e85c3cSJim Quinlan depends on PCI 283b0e85c3cSJim Quinlan help 284b0e85c3cSJim Quinlan Default choice; ensure that the MPS matches upstream bridge. 285b0e85c3cSJim Quinlan 286b0e85c3cSJim Quinlanconfig PCIE_BUS_SAFE 287b0e85c3cSJim Quinlan bool "Safe" 288b0e85c3cSJim Quinlan depends on PCI 289b0e85c3cSJim Quinlan help 290b0e85c3cSJim Quinlan Use largest MPS that boot-time devices support. If you have a 291b0e85c3cSJim Quinlan closed system with no possibility of adding new devices, this 292b0e85c3cSJim Quinlan will use the largest MPS that's supported by all devices. This 293b0e85c3cSJim Quinlan is the same as booting with 'pci=pcie_bus_safe'. 294b0e85c3cSJim Quinlan 295b0e85c3cSJim Quinlanconfig PCIE_BUS_PERFORMANCE 296b0e85c3cSJim Quinlan bool "Performance" 297b0e85c3cSJim Quinlan depends on PCI 298b0e85c3cSJim Quinlan help 299b0e85c3cSJim Quinlan Use MPS and MRRS for best performance. Ensure that a given 300b0e85c3cSJim Quinlan device's MPS is no larger than its parent MPS, which allows us to 301b0e85c3cSJim Quinlan keep all switches/bridges to the max MPS supported by their 302b0e85c3cSJim Quinlan parent. This is the same as booting with 'pci=pcie_bus_perf'. 303b0e85c3cSJim Quinlan 304b0e85c3cSJim Quinlanconfig PCIE_BUS_PEER2PEER 305b0e85c3cSJim Quinlan bool "Peer2peer" 306b0e85c3cSJim Quinlan depends on PCI 307b0e85c3cSJim Quinlan help 308b0e85c3cSJim Quinlan Set MPS = 128 for all devices. MPS configuration effected by the 309b0e85c3cSJim Quinlan other options could cause the MPS on one root port to be 310b0e85c3cSJim Quinlan different than that of the MPS on another, which may cause 311b0e85c3cSJim Quinlan hot-added devices or peer-to-peer DMA to fail. Set MPS to the 312b0e85c3cSJim Quinlan smallest possible value (128B) system-wide to avoid these issues. 313b0e85c3cSJim Quinlan This is the same as booting with 'pci=pcie_bus_peer2peer'. 314b0e85c3cSJim Quinlan 315b0e85c3cSJim Quinlanendchoice 316b0e85c3cSJim Quinlan 3171d38fe6eSBjorn Helgaasconfig VGA_ARB 3181d38fe6eSBjorn Helgaas bool "VGA Arbitration" if EXPERT 3191d38fe6eSBjorn Helgaas default y 3201d38fe6eSBjorn Helgaas depends on (PCI && !S390) 321a78835b8SMario Limonciello (AMD) select SCREEN_INFO if X86 3221d38fe6eSBjorn Helgaas help 3231d38fe6eSBjorn Helgaas Some "legacy" VGA devices implemented on PCI typically have the same 3241d38fe6eSBjorn Helgaas hard-decoded addresses as they did on ISA. When multiple PCI devices 3251d38fe6eSBjorn Helgaas are accessed at same time they need some kind of coordination. Please 3261d38fe6eSBjorn Helgaas see Documentation/gpu/vgaarbiter.rst for more details. Select this to 3271d38fe6eSBjorn Helgaas enable VGA arbiter. 3281d38fe6eSBjorn Helgaas 3291d38fe6eSBjorn Helgaasconfig VGA_ARB_MAX_GPUS 3301d38fe6eSBjorn Helgaas int "Maximum number of GPUs" 3311d38fe6eSBjorn Helgaas default 16 3321d38fe6eSBjorn Helgaas depends on VGA_ARB 3331d38fe6eSBjorn Helgaas help 3341d38fe6eSBjorn Helgaas Reserves space in the kernel to maintain resource locking for 3351d38fe6eSBjorn Helgaas multiple GPUS. The overhead for each GPU is very small. 3361d38fe6eSBjorn Helgaas 33730b5b880STero Roponensource "drivers/pci/hotplug/Kconfig" 3386e0832faSShawn Linsource "drivers/pci/controller/Kconfig" 3395e8cb403SKishon Vijay Abraham Isource "drivers/pci/endpoint/Kconfig" 340080b47deSLogan Gunthorpesource "drivers/pci/switch/Kconfig" 341b88cbaaaSBjorn Helgaassource "drivers/pci/pwrctrl/Kconfig" 3422e8cb2cfSRob Herring 3432e8cb2cfSRob Herringendif 344