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/linux/drivers/pci/controller/dwc/
H A Dpcie-kirin.c1 // SPDX-License-Identifier: GPL-2.0
20 #include <linux/phy/phy.h>
21 #include <linux/pci.h>
27 #include "pcie-designware.h"
29 #define to_kirin_pcie(x) dev_get_drvdata((x)->dev)
54 * Max number of connected PCI slots at an external PCI bridge
58 * in-board Ethernet adapter and the other two connected to M.2 and mini
59 * PCI slots.
73 struct dw_pcie *pci; member
75 struct phy *phy; member
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H A Dpcie-armada8k.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Marvell Armada-8K SoCs
5 * Armada-8K PCIe Glue Layer Source Code
19 #include <linux/pci.h>
20 #include <linux/phy/phy.h>
25 #include "pcie-designware.h"
30 struct dw_pcie *pci; member
33 struct phy *phy[ARMADA8K_PCIE_MAX_LANES]; member
61 * AR/AW Cache defaults: Normal memory, Write-Back, Read / Write
71 #define to_armada8k_pcie(x) dev_get_drvdata((x)->dev)
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H A Dpci-exynos.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2020 Samsung Electronics Co., Ltd.
17 #include <linux/pci.h>
19 #include <linux/phy/phy.h>
24 #include "pcie-designware.h"
26 #define to_exynos_pcie(x) dev_get_drvdata((x)->dev)
55 struct dw_pcie pci; member
57 struct phy *phy; member
73 struct dw_pcie *pci = &ep->pci; in exynos_pcie_sideband_dbi_w_mode() local
76 val = exynos_pcie_readl(pci->elbi_base, PCIE_ELBI_SLV_AWMISC); in exynos_pcie_sideband_dbi_w_mode()
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H A Dpci-dra7xx.c1 // SPDX-License-Identifier: GPL-2.0
3 * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
5 * Copyright (C) 2013-2014 Texas Instruments Incorporated - https://www.ti.com
22 #include <linux/pci.h>
23 #include <linux/phy/phy.h>
32 #include "../../pci.h"
33 #include "pcie-designware.h"
89 struct dw_pcie *pci; member
91 int phy_count; /* DT phy-names count */
92 struct phy **phy; member
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H A Dpcie-stm32-ep.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/phy/phy.h>
18 #include "pcie-designware.h"
19 #include "pcie-stm32.h"
22 struct dw_pcie pci; member
25 struct phy *ph member
33 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); stm32_pcie_ep_init() local
40 stm32_pcie_enable_link(struct dw_pcie * pci) stm32_pcie_enable_link() argument
51 stm32_pcie_disable_link(struct dw_pcie * pci) stm32_pcie_disable_link() argument
58 stm32_pcie_start_link(struct dw_pcie * pci) stm32_pcie_start_link() argument
76 stm32_pcie_stop_link(struct dw_pcie * pci) stm32_pcie_stop_link() argument
90 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); stm32_pcie_raise_irq() local
147 stm32_pcie_perst_assert(struct dw_pcie * pci) stm32_pcie_perst_assert() argument
162 stm32_pcie_perst_deassert(struct dw_pcie * pci) stm32_pcie_perst_deassert() argument
207 struct dw_pcie *pci = &stm32_pcie->pci; stm32_pcie_ep_perst_irq_thread() local
332 struct dw_pcie *pci = &stm32_pcie->pci; stm32_pcie_remove() local
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H A Dpci-meson.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/pci.h>
17 #include <linux/phy/phy.h>
21 #include "pcie-designware.h"
23 #define to_meson_pcie(x) dev_get_drvdata((x)->dev)
67 struct dw_pcie pci; member
72 struct phy *ph member
110 struct dw_pcie *pci = &mp->pci; meson_pcie_get_mems() local
266 struct dw_pcie *pci = &mp->pci; meson_set_max_payload() local
282 struct dw_pcie *pci = &mp->pci; meson_set_max_rd_req_size() local
296 meson_pcie_start_link(struct dw_pcie * pci) meson_pcie_start_link() argument
338 meson_pcie_link_up(struct dw_pcie * pci) meson_pcie_link_up() argument
379 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); meson_pcie_host_init() local
402 struct dw_pcie *pci; meson_pcie_probe() local
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H A Dpcie-spear13xx.c1 // SPDX-License-Identifier: GPL-2.0
7 * Copyright (C) 2010-2014 ST Microelectronics
17 #include <linux/pci.h>
18 #include <linux/phy/phy.h>
22 #include "pcie-designware.h"
25 struct dw_pcie *pci; member
27 struct phy *phy; member
67 #define to_spear13xx_pcie(x) dev_get_drvdata((x)->dev)
69 static int spear13xx_pcie_start_link(struct dw_pcie *pci) in spear13xx_pcie_start_link() argument
71 struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pci); in spear13xx_pcie_start_link()
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H A Dpcie-histb.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2017 HiSilicon Co., Ltd. http://www.hisilicon.com
18 #include <linux/pci.h>
19 #include <linux/phy/phy.h>
24 #include "pcie-designware.h"
26 #define to_histb_pcie(x) dev_get_drvdata((x)->dev)
53 struct dw_pcie *pci; member
58 struct phy *phy; member
69 return readl(histb_pcie->ctrl + reg); in histb_pcie_readl()
74 writel(val, histb_pcie->ctrl + reg); in histb_pcie_writel()
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H A Dpcie-stm32.c1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <linux/phy/phy.h>
30 #include "../../pci.h"
32 #include "pcie-designware.h"
33 #include "pcie-stm32.h" in stm32_pcie_deassert_perst()
36 struct dw_pcie pci; in stm32_pcie_deassert_perst()
24 struct dw_pcie pci; global() member
27 struct phy *phy; global() member
48 stm32_pcie_start_link(struct dw_pcie * pci) stm32_pcie_start_link() argument
57 stm32_pcie_stop_link(struct dw_pcie * pci) stm32_pcie_stop_link() argument
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H A Dpci-keystone.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2014 Texas Instruments., Ltd.
8 * Author: Murali Karicheri <m-karicheri2@ti.com>
9 * Implementation based on pci-exynos.c and pcie-designware.c
25 #include <linux/phy/phy
122 struct dw_pcie *pci; global() member
130 struct phy **phy; global() member
158 struct dw_pcie *pci; ks_pcie_msi_irq_ack() local
177 struct dw_pcie *pci; ks_pcie_compose_msi_msg() local
197 struct dw_pcie *pci; ks_pcie_msi_mask() local
221 struct dw_pcie *pci; ks_pcie_msi_unmask() local
292 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); ks_pcie_msi_host_init() local
317 struct dw_pcie *pci = ks_pcie->pci; ks_pcie_handle_intx_irq() local
407 struct dw_pcie *pci = ks_pcie->pci; ks_pcie_setup_rc_app_regs() local
454 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); ks_pcie_other_map_bus() local
495 ks_pcie_link_up(struct dw_pcie * pci) ks_pcie_link_up() argument
503 ks_pcie_stop_link(struct dw_pcie * pci) ks_pcie_stop_link() argument
514 ks_pcie_start_link(struct dw_pcie * pci) ks_pcie_start_link() argument
609 struct dw_pcie *pci = ks_pcie->pci; ks_pcie_msi_irq_handler() local
652 struct dw_pcie *pci = ks_pcie->pci; ks_pcie_intx_irq_handler() local
807 struct dw_pcie *pci = ks_pcie->pci; ks_pcie_init_id() local
836 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); ks_pcie_host_init() local
892 ks_pcie_am654_write_dbi2(struct dw_pcie * pci,void __iomem * base,u32 reg,size_t size,u32 val) ks_pcie_am654_write_dbi2() argument
911 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); ks_pcie_am654_ep_init() local
922 struct dw_pcie *pci = ks_pcie->pci; ks_pcie_am654_raise_intx_irq() local
941 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); ks_pcie_am654_raise_irq() local
1146 struct dw_pcie *pci; ks_pcie_probe() local
1153 struct phy **phy; ks_pcie_probe() local
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H A Dpci-imx6.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
18 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
22 #include <linux/pci.h>
31 #include <linux/phy/pcie.h>
32 #include <linux/phy/phy.h>
36 #include "../../pci.h"
37 #include "pcie-designware.h"
82 #define to_imx_pcie(x) dev_get_drvdata((x)->dev)
118 #define imx_check_flag(pci, val) (pci->drvdata->flags & val) argument
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H A Dpcie-uniphier.c1 // SPDX-License-Identifier: GPL-2.0
18 #include <linux/pci.h>
19 #include <linux/phy/phy.h>
23 #include "pcie-designware.h"
65 struct dw_pcie pci; member
69 struct phy *phy; member
73 #define to_uniphier_pcie(x) dev_get_drvdata((x)->dev)
80 val = readl(pcie->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
85 writel(val, pcie->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
93 val = readl(pcie->base + PCL_MODE); in uniphier_pcie_init_rc()
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H A Dpcie-dw-rockchip.c1 // SPDX-License-Identifier: GPL-2.0
6 * http://www.rock-chips.com
8 * Author: Simon Xue <xxm@rock-chips.com>
21 #include <linux/phy/phy.h>
26 #include "../../pci.h"
27 #include "pcie-designware.h"
34 #define to_rockchip_pcie(x) dev_get_drvdata((x)->de
78 struct dw_pcie pci; global() member
80 struct phy *phy; global() member
195 rockchip_pcie_link_up(struct dw_pcie * pci) rockchip_pcie_link_up() argument
203 rockchip_pcie_enable_l0s(struct dw_pcie * pci) rockchip_pcie_enable_l0s() argument
218 rockchip_pcie_start_link(struct dw_pcie * pci) rockchip_pcie_start_link() argument
242 rockchip_pcie_stop_link(struct dw_pcie * pci) rockchip_pcie_stop_link() argument
251 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); rockchip_pcie_host_init() local
287 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); rockchip_pcie_ep_hide_broken_ats_cap_rk3588() local
301 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); rockchip_pcie_ep_init() local
314 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); rockchip_pcie_raise_irq() local
366 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); rockchip_pcie_get_features() local
454 struct dw_pcie *pci = &rockchip->pci; rockchip_pcie_rc_sys_irq_thread() local
482 struct dw_pcie *pci = &rockchip->pci; rockchip_pcie_ep_sys_irq_thread() local
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H A Dpcie-qcom-ep.c1 // SPDX-License-Identifier: GPL-2.0
18 #include <linux/phy/pcie.h>
19 #include <linux/phy/phy.h>
26 #include "../../pci.h"
27 #include "pcie-designware.h"
28 #include "pcie-qcom-common.h"
157 #define to_pcie_ep(x) dev_get_drvdata((x)->dev)
167 * struct qcom_pcie_ep_cfg - Per SoC config struct
179 * struct qcom_pcie_ep - Qualcomm PCIe Endpoint Controller
180 * @pci: Designware PCIe controller struct
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H A Dpcie-uniphier-ep.c1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/pci.h>
16 #include <linux/phy/phy.h>
20 #include "pcie-designware.h"
74 struct dw_pcie pci; member
77 struct phy *phy; member
88 #define to_uniphier_pcie(x) dev_get_drvdata((x)->dev)
95 val = readl(priv->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
100 writel(val, priv->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
108 val = readl(priv->base + PCL_RSTCTRL2); in uniphier_pcie_phy_reset()
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H A Dpcie-qcom.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
8 * Author: Stanimir Varbanov <svarbanov@mm-sol.com>
25 #include <linux/pci.h>
26 #include <linux/pci-ecam.h>
30 #include <linux/phy/pcie.h>
31 #include <linux/phy/phy.h>
38 #include "../../pci.h"
39 #include "../pci-host-common.h"
40 #include "pcie-designware.h"
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/linux/drivers/usb/dwc2/
H A Dpci.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * pci.c - DesignWare HS OTG Controller PCI driver
5 * Copyright (C) 2004-2013 Synopsys, Inc.
9 * Provides the initialization and cleanup entry points for the DWC_otg PCI
19 #include <linux/pci.h>
29 static const char dwc2_driver_name[] = "dwc2-pci";
33 struct platform_device *phy; member
37 * dwc2_pci_remove() - Provides the cleanup entry points for the DWC_otg PCI
40 * @pci: The programming view of DWC_otg PCI
42 static void dwc2_pci_remove(struct pci_dev *pci) in dwc2_pci_remove() argument
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/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8572ds.dtsi2 * MPC8572DS Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
46 label = "ramdisk-nor";
51 label = "diagnostic-nor";
52 read-only;
57 label = "dink-nor";
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H A Dppa8548.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PPA8548 Device Tree Source (36-bit address map)
7 * MPC8548 CDS Device Tree Source (36-bit address map)
11 /include/ "mpc8548si-pre.dtsi"
16 #address-cells = <2>;
17 #size-cells = <2>;
18 interrupt-parent = <&mpic>;
34 pci0: pci@fe0008000 {
35 /* ppa8548 board doesn't support PCI */
39 pci1: pci@fe0009000 {
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H A Dp2020ds.dtsi2 * P2020DS Device Tree Source stub (no addresses or top-level ranges)
4 * Copyright 2011-2012 Freescale Semiconductor Inc.
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
46 read-only;
51 read-only;
56 read-only;
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/linux/drivers/usb/chipidea/
H A Dci_hdrc_pci.c1 // SPDX-License-Identifier: GPL-2.0
3 * ci_hdrc_pci.c - MIPS USB IP core family device controller
5 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
12 #include <linux/pci.h>
23 struct platform_device *phy; member
27 * PCI block
46 * ci_hdrc_pci_probe: PCI probe
48 * @id: PCI hotplug ID connecting controller to UDC framework
51 * Allocates basic PCI resources for this USB device controller, and then
57 struct ci_hdrc_platform_data *platdata = (void *)id->driver_data; in ci_hdrc_pci_probe()
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/linux/Documentation/devicetree/bindings/pci/
H A Drenesas,pci-rcar-gen2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/renesas,pci-rcar-gen2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas AHB to PCI bridge
10 - Marek Vasut <marek.vasut+renesas@gmail.com>
11 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
21 - items:
22 - enum:
23 - renesas,pci-r8a7742 # RZ/G1H
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H A Dmediatek,mt7621-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/mediatek,mt7621-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
14 with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link
18 .-------.
22 '-------'
27 .------------------.
28 .-----------| HOST/PCI Bridge |------------.
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/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,mt7621-pci-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/mediatek,mt7621-pci-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek Mt7621 PCIe PHY
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
14 const: mediatek,mt7621-pci-phy
22 "#phy-cells":
24 description: selects if the phy is dual-ported
27 - compatible
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/linux/drivers/net/wireless/broadcom/b43/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
27 b43-fwcutter.
61 # Auto-select SSB PCI-HOST support, if possible
69 # Auto-select SSB PCICORE driver, if possible
81 Broadcom 43xx device support for Soft-MAC SDIO devices.
83 With this config option you can drive Soft-MAC b43 cards with a
87 Note that this does not support Broadcom 43xx Full-MAC devices.
108 bool "Support for G-PHY (802.11g) devices"
112 This PHY type can be found in the following chipsets:
113 PCI: BCM4306, BCM4311, BCM4318
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