page\-level (full) in projects: freebsd

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/freebsd/lib/libpmc/pmu-events/arch/arm64/ampere/emag/
H A D	cache.json	78 …"PublicDescription": "Level 2 access to data TLB that caused a page table walk. This event counts … 84 …"PublicDescription": "Level 2 access to instruciton TLB that caused a page table walk. This event … 108 "PublicDescription": "Level 1 data cache late miss", 114 "PublicDescription": "Level 1 data cache prefetch request", 120 "PublicDescription": "Level 2 data cache prefetch request", 126 "PublicDescription": "Level 1 stage 2 TLB refill", 132 "PublicDescription": "Page walk cache level-0 stage-1 hit", 135 "BriefDescription": "Page walk, L0 stage-1 hit" 138 "PublicDescription": "Page walk cache level-1 stage-1 hit", 141 "BriefDescription": "Page walk, L1 stage-1 hit" [all …]
/freebsd/lib/libpmc/pmu-events/arch/powerpc/power9/
H A D	marked.json	10 …"BriefDescription": "A Page Directory Entry was reloaded to a level 1 page walk cache from beyond … 20 … Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same … 45 …efDescription": "A Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 d… 50 …efDescription": "A Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 d… 60 …iption": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marke… 70 …Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the sa… 95 …Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the … 100 …Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the sa… 140 …"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the loc… 170 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without d… [all …]
/freebsd/lib/libc/db/btree/
H A D	bt_delete.c	`1 /- 2 SPDX-License-Identifier: BSD-3-Clause 45 static int __bt_curdel(BTREE , const DBT , PAGE , u_int); 46 static int __bt_pdelete(BTREE , PAGE ); 47 static int __bt_relink(BTREE , PAGE ); 48 static int __bt_stkacq(BTREE , PAGE *, CURSOR ); 61 PAGE h; in __bt_delete() 64 t = dbp->internal; in __bt_delete() 66 / Toss any page pinned across calls. */ in __bt_delete() 67 if (t->bt_pinned != NULL) { in __bt_delete() [all …]`
/freebsd/lib/libpmc/pmu-events/arch/x86/tremontx/
H A D	virtual-memory.json	3 …"BriefDescription": "Counts the number of page walks due to loads that miss the PDE (Page Director… 14 …ription": "Counts the number of first level TLB misses but second level hits due to loads that did… 25 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page… 31 …page walks completed due to loads (including SW prefetches) whose address translations missed in a… 36 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 1G pag… 43 …page walks completed due to loads (including SW prefetches) whose address translations missed in a… 48 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or … 55 …page walks completed due to loads (including SW prefetches) whose address translations missed in a… 60 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K pag… 67 …page walks completed due to loads (including SW prefetches) whose address translations missed in a… [all …]
/freebsd/sys/arm64/iommu/
H A D	iommu_pmap.c	`1 /- 2 SPDX-License-Identifier: BSD-2-Clause 4 * Copyright (c) 2020-2021 Ruslan Bukin <br@bsdpad.com> 5 * Copyright (c) 2014-2021 Andrew Turner 6 * Copyright (c) 2014-2016 The FreeBSD Foundation 63 #define SMMU_PMAP_LOCK(pmap) mtx_lock(&(pmap)->sp_mtx) 64 #define SMMU_PMAP_UNLOCK(pmap) mtx_unlock(&(pmap)->sp_mtx) 66 mtx_assert(&(pmap)->sp_mtx, (type)) 107 return (&pmap->sp_l0[smmu_l0_index(va)]); in smmu_pmap_l0() 184 * The next level may or may not point to a valid page or block. [all …]`
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z196/
H A D	extended.json	6 …iption": "A directory write to the Level-1 D-Cache directory where the returned cache line was sou… 12 …iption": "A directory write to the Level-1 I-Cache directory where the returned cache line was sou… 18 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB… 24 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle… 30 "PublicDescription": "Incremented by one for every store sent to Level-2 cache" 35 "BriefDescription": "L1D Off-Book L3 Sourced Writes", 36 …on": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced… 41 "BriefDescription": "L1D On-Book L4 Sourced Writes", 42 …on": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced… 47 "BriefDescription": "L1I On-Book L4 Sourced Writes", [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/ivybridge/
H A D	virtual-memory.json	3 "BriefDescription": "Page walk for a large page completed for Demand load.", 12 … load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size.", 17 …"PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand… 22 …cription": "Load operations that miss the first DTLB level but hit the second and do not cause pag… 27 … "PublicDescription": "Counts load operations that missed 1st level DTLB but hit the 2nd level.", 32 …in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page siz… 37 …"PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by dema… 42 "BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.", 52 "BriefDescription": "Store misses in all DTLB levels that cause page walks", 57 … "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).", [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/ivytown/
H A D	virtual-memory.json	3 …in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page siz… 12 "BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.", 21 "BriefDescription": "Page walk for a large page completed for Demand load.", 30 … load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size.", 35 …"PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand… 40 …cription": "Load operations that miss the first DTLB level but hit the second and do not cause pag… 45 … "PublicDescription": "Counts load operations that missed 1st level DTLB but hit the 2nd level.", 50 …in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page siz… 55 …"PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by dema… 60 "BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.", [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/elkhartlake/
H A D	virtual-memory.json	3 …"BriefDescription": "Counts the number of page walks due to loads that miss the PDE (Page Director… 14 …ription": "Counts the number of first level TLB misses but second level hits due to loads that did… 25 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page… 31 …page walks completed due to loads (including SW prefetches) whose address translations missed in a… 36 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or … 43 …page walks completed due to loads (including SW prefetches) whose address translations missed in a… 48 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K pag… 55 …page walks completed due to loads (including SW prefetches) whose address translations missed in a… 60 …"BriefDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) fo… 67 …page walks outstanding in the page miss handler (PMH) for loads every cycle. A page walk is outst… [all …]
/freebsd/sys/powerpc/include/
H A D	pte.h	`1 /- 2 SPDX-License-Identifier: BSD-4-Clause 42 * Page Table Entries 46 /* 32-bit PTE / 56 / 64-bit (long) PTE / 82 / 32-bit PTE definitions / 100 #define PTE_SW 0x00000001 / Super. Write-Only (U: RO, S: RW) / 106 #define PTE_EXEC 0x00000200 / pseudo bit in attrs; page is exec / 108 / 64-bit PTE definitions / 118 #define LPTE_BIG 0x0000000000000004ULL / 4kb/16Mb page */ [all …]`
/freebsd/sys/amd64/include/
H A D	param.h	`1 /- 2 SPDX-License-Identifier: BSD-4-Clause 86 * CACHE_LINE_SIZE is the compile-time maximum cache line size for an 92 /* Size of the level 1 page table units / 96 #define PAGE_SIZE (1<<PAGE_SHIFT) / bytes/page / 97 #define PAGE_MASK (PAGE_SIZE-1) 98 / Size of the level 2 page directory units / 102 #define NBPDR (1<<PDRSHIFT) / bytes/page dir / 103 #define PDRMASK (NBPDR-1) 104 / Size of the level 3 page directory pointer table units */ [all …]`
H A D	pmap.h	1 /- 2 SPDX-License-Identifier: BSD-3-Clause 37 * Jolitz uses a recursive map [a pde points to the page directory] to 38 * map the page tables using the pagetables themselves. This is done to 81 * Promotion to a 2MB (PDE) page mapping requires that the corresponding 4KB 82 * (PTE) page mappings have identical settings for the following fields: 114 ((unsigned long)-1 << 47) \| \ 120 ((unsigned long)-1 << 56) \| \ 150 * one-to-one with the kernel map. 156 * We use the same numbering of the page table pages for 5-level and [all …]
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z13/
H A D	extended.json	5 "BriefDescription": "L1D Read-only Exclusive Writes", 6 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in… 12 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi… 18 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB… 23 "BriefDescription": "DTLB1 One-Megabyte Page Writes", 24 …A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-me… 29 "BriefDescription": "DTLB1 Two-Gigabyte Page Writes", 30 …A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a two-gi… 36 …tion": "A directory write to the Level-1 Data cache directory where the returned cache line was so… 42 …"PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation … [all …]
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_zec12/
H A D	extended.json	6 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB… 12 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle… 18 …tion": "A directory write to the Level-1 Data cache directory where the returned cache line was so… 24 …n": "A directory write to the Level-1 Instruction cache directory where the returned cache line wa… 30 …tion": "A directory write to the Level-1 Data cache directory where the returned cache line was so… 36 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi… 42 …"PublicDescription": "A directory write to the Level-1 Data cache where the installed cache line w… 48 …"PublicDescription": "A directory write to the Level-1 Instruction cache where the installed cache… 53 "BriefDescription": "L1D Read-only Exclusive Writes", 54 …"PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a … [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/haswell/
H A D	virtual-memory.json	3 "BriefDescription": "Load misses in all DTLB levels that cause page walks", 8 "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.", 13 …"BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translati… 18 …"PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translat… 23 …cription": "Load operations that miss the first DTLB level but hit the second and do not cause pag… 28 "PublicDescription": "Number of cache load STLB hits. No page walk.", 38 …vent counts load operations from a 2M page that miss the first DTLB level but hit the second and d… 48 …vent counts load operations from a 4K page that miss the first DTLB level but hit the second and d… 53 …in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page siz… 58 …"PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.", [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/haswellx/
H A D	virtual-memory.json	3 "BriefDescription": "Load misses in all DTLB levels that cause page walks", 8 "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.", 13 …"BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translati… 18 …"PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translat… 23 …cription": "Load operations that miss the first DTLB level but hit the second and do not cause pag… 28 "PublicDescription": "Number of cache load STLB hits. No page walk.", 38 …vent counts load operations from a 2M page that miss the first DTLB level but hit the second and d… 48 …vent counts load operations from a 4K page that miss the first DTLB level but hit the second and d… 53 …in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page siz… 58 …"PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.", [all …]
/freebsd/contrib/mandoc/
H A D	man.cgi.3	`28 .Bl -enum -compact 30 .Sx Top level 32 .Sx Page generators 38 .Ss Top level 39 The top level of 44 .Bl -tag -width 1n 47 .Bl -dash -compact 69 .Sx Page generators . 75 .Va req->p 77 .Va req->psz . [all …]`
H A D	man.cgi.8	`35 At the top of each generated HTML page, 38 .Bl -enum 41 either a name of a manual page or an 56 The string in the input box is interpreted as the name of a manual page. 92 .Bl -tag -width Ds 93 .It The index page. 102 .It A list page. 103 Lists are returned when searches match more than one manual page. 106 The second column shows the one-line descriptions of the manuals. 109 style searches, the content of the first manual page follows the list. [all …]`
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z14/
H A D	extended.json	5 "BriefDescription": "L1D Read-only Exclusive Writes", 6 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in… 18 …e data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on thi… 23 "BriefDescription": "DTLB2 One-Megabyte Page Writes", 24 …o the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page or … 29 "BriefDescription": "DTLB2 Two-Gigabyte Page Writes", 30 …"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB" 36 …tion": "A directory write to the Level-1 Data cache directory where the returned cache line was so… 48 …uction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cache… 54 …n": "A directory write to the Level-1 Instruction cache directory where the returned cache line wa… [all …]
/freebsd/share/doc/usd/21.troff/
H A D	m2	1 .\" Copyright (C) Caldera International Inc. 2001-2002. All rights reserved. 46 page offset space. 47 The line-length minus the indent is the basis for centering with \fBce\fR. 54 The length of \fIthree-part titles\fR produced by \fBtl\fR 58 \fB&ll\fI\|\(+-N\fR 6.5\\|in previous E,\fBm\fR Line length is set to \(+-\fIN\fR. 59 In \*(TR the maximum (line-length)+(page-offset) is about 7.54 inches. 61 \fB&in\fI\|\(+-N\fR \fIN\(eq\^\fR0 previous B,E,\fBm\fR Indent is set to \fI\(+-N\fR. 64 \fB&ti\fI\|\(+-N\fR - ignored B,E,\fBm\fR Temporary indent. 65 The \fInext\fR output text line will be indented a distance \fI\(+-N\fR 107 \(bu \fB\et\fR and \fB\ea\fR are interpreted as \s-1ASCII\s+1 horizontal tab and \s-1SOH\s+1 respec… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/jaketown/
H A D	virtual-memory.json	3 "BriefDescription": "Load misses in all DTLB levels that cause page walks.", 12 …cription": "Load operations that miss the first DTLB level but hit the second and do not cause pag… 17 …nt counts load operations that miss the first DTLB level but hit the second and do not cause any p… 22 "BriefDescription": "Load misses at all DTLB levels that cause completed page walks.", 31 "BriefDescription": "Cycles when PMH is busy with page walks.", 36 …PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page … 41 "BriefDescription": "Store misses in all DTLB levels that cause page walks.", 50 …cription": "Store operations that miss the first TLB level but hit the second and do not cause pag… 59 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.", 68 "BriefDescription": "Cycles when PMH is busy with page walks.", [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/sandybridge/
H A D	virtual-memory.json	3 "BriefDescription": "Load misses in all DTLB levels that cause page walks.", 12 …cription": "Load operations that miss the first DTLB level but hit the second and do not cause pag… 17 …nt counts load operations that miss the first DTLB level but hit the second and do not cause any p… 22 "BriefDescription": "Load misses at all DTLB levels that cause completed page walks.", 31 "BriefDescription": "Cycles when PMH is busy with page walks.", 36 …PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page … 41 "BriefDescription": "Store misses in all DTLB levels that cause page walks.", 50 …cription": "Store operations that miss the first TLB level but hit the second and do not cause pag… 59 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.", 68 "BriefDescription": "Cycles when PMH is busy with page walks.", [all …]
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z10/
H A D	extended.json	6 …iption": "A directory write to the Level-1 I-Cache directory where the returned cache line was sou… 12 …ption": "A directory write to the Level-1 D-Cache directory where the installed cache line was sou… 18 …ption": "A directory write to the Level-1 I-Cache directory where the installed cache line was sou… 24 …ption": "A directory write to the Level-1 D-Cache directory where the installtion cache line was s… 30 …iption": "A directory write to the Level-1 I-Cache directory where the installed cache line was so… 36 …iption": "A directory write to the Level-1 D-Cache directory where the installed cache line was so… 42 …"PublicDescription": "A directory write to the Level-1 D-Cache directory where the installed cache… 48 …"PublicDescription": "A directory write to the Level-1 I-Cache where the installed cache line was … 53 "BriefDescription": "L1D Read-only Exclusive Writes", 54 …"PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a … [all …]
/freebsd/sys/contrib/device-tree/Bindings/perf/
H A D	marvell-cn10k-tad.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/perf/marvell-cn10k-tad.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Marvell CN10K LLC-TAD performance monitor 10 - Bhaskara Budiredla <bbudiredla@marvell.com> 13 The Tag-and-Data units (TADs) maintain coherence and contain CN10K 14 shared on-chip last level cache (LLC). The tad pmu measures the 15 performance of last-level cache. Each tad pmu supports up to eight 23 const: marvell,cn10k-tad-pmu [all …]
/freebsd/sys/arm64/include/
H A D	pte.h	`1 /- 3 Copyright (c) 2014-2015 The FreeBSD Foundation 39 typedef uint64_t pd_entry_t; /* page directory entry / 40 typedef uint64_t pt_entry_t; / page table entry / 52 / Block and Page attributes / 88 #define ATTR_SH_NS 0 / Non-shareable / 89 #define ATTR_SH_OS 2 / Outer-shareable / 90 #define ATTR_SH_IS 3 / Inner-shareable / 138 #error Unsupported page size 141 / Level 0 table, 512GiB/128TiB per entry */ [all …]`

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