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/linux/Documentation/devicetree/bindings/timer/
H A Dmarvell,orion-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/marvell,orion-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell Orion SoC timer
10 - Andrew Lunn <andrew@lunn.ch>
11 - Gregory Clement <gregory.clement@bootlin.com>
15 const: marvell,orion-timer
25 - description: Timer0 interrupt
26 - description: Timer1 interrupt
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Dorion5x.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2012 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 #address-cells = <1>;
8 #size-cells = <1>;
11 interrupt-parent = <&intc>;
18 #address-cells = <2>;
19 #size-cells = <1>;
22 devbus_bootcs: devbus-bootcs {
23 compatible = "marvell,orion-devbus";
26 #address-cells = <1>;
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H A Dkirkwood.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
3 #include <dt-bindings/gpio/gpio.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
11 interrupt-parent = <&intc>;
14 #address-cells = <1>;
15 #size-cells = <0>;
22 clock-names = "cpu_clk", "ddrclk", "powersave";
33 compatible = "marvell,kirkwood-mbus", "simple-bus";
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H A Darmada-375.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/phy/phy.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
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H A Ddove.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/gpio/gpio.h>
3 #include <dt-bindings/interrupt-controller/irq.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
12 interrupt-parent = <&intc>;
21 #address-cells = <1>;
22 #size-cells = <0>;
25 compatible = "marvell,pj4a", "marvell,sheeva-v7";
27 next-level-cache = <&l2>;
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H A Darmada-38x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
32 compatible = "arm,cortex-a9-pmu";
33 interrupts-extended = <&mpic 3>;
37 compatible = "marvell,armada380-mbus", "simple-bus";
[all …]
H A Darmada-xp-98dx3236.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 #include "armada-370-xp.dtsi"
14 #address-cells = <2>;
15 #size-cells = <2>;
18 compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,98dx3236-smp";
33 compatible = "marvell,sheeva-v7";
36 clock-latency = <1000000>;
[all …]
H A Darmada-xp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
16 #include "armada-370-xp.dtsi"
19 #address-cells = <2>;
20 #size-cells = <2>;
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
31 compatible = "marvell,armadaxp-mbus", "simple-bus";
38 internal-regs {
40 compatible = "marvell,armada-xp-sdram-controller";
[all …]
H A Darmada-39x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
31 #address-cells = <1>;
32 #size-cells = <0>;
33 enable-method = "marvell,armada-390-smp";
37 compatible = "arm,cortex-a9";
[all …]
H A Darmada-370-xp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
20 compatible = "marvell,armada-370-xp";
28 #address-cells = <1>;
29 #size-cells = <0>;
31 compatible = "marvell,sheeva-v7";
38 compatible = "arm,cortex-a9-pmu";
39 interrupts-extended = <&mpic 3>;
43 #address-cells = <2>;
[all …]
/linux/Documentation/devicetree/bindings/watchdog/
H A Dmarvell,orion-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/marvell,orion-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell Orion Watchdog Timer
10 - Andrew Lunn <andrew@lunn.ch>
11 - Gregory Clement <gregory.clement@bootlin.com>
16 - marvell,orion-wdt
17 - marvell,armada-370-wdt
18 - marvell,armada-xp-wdt
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/linux/arch/arm/plat-orion/
H A Dtime.c2 * arch/arm/plat-orion/time.c
4 * Marvell Orion SoC timer handling.
10 * Timer 0 is used as free-running clocksource, while timer 1 is
15 #include <linux/timer.h>
33 * Timer block registers.
47 * SoC-specific data.
55 * Number of timer ticks per jiffy.
61 * Orion's sched_clock implementation. It has a resolution of
80 return -ETIME; in orion_clkevt_next_event()
85 * Clear and enable clockevent timer interrupt. in orion_clkevt_next_event()
[all …]
/linux/drivers/clocksource/
H A Dtimer-orion.c1 // SPDX-License-Identifier: GPL-2.0
3 * Marvell Orion SoC timer handling.
7 * Timer 0 is used as free-running clocksource, while timer 1 is
53 * Free-running clocksource handling.
68 /* setup and enable one-shot timer */ in orion_clkevt_next_event()
78 /* disable timer */ in orion_clkevt_shutdown()
86 /* setup and enable periodic timer at 1/HZ intervals */ in orion_clkevt_set_periodic()
87 writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD); in orion_clkevt_set_periodic()
88 writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL); in orion_clkevt_set_periodic()
120 /* timer registers are shared with watchdog timer */ in orion_timer_init()
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/linux/drivers/net/fddi/skfp/h/
H A Dsupern_2.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
48 #define FS_SSRCRTG (1<<12) /* if SA has set MSB (source-routing)*/
54 #define FS_SFRMTY2 (1<<6) /* frame-class bit */
55 #define FS_SFRMTY1 (1<<5) /* frame-type bit (impementor) */
56 #define FS_SFRMTY0 (1<<4) /* frame-type bit (LLC) */
58 #define FS_ERFBB0 (1<<0) /* - " - */
95 unsigned int rx_sadrrg :1 ; /* DA == MA or broad-/multicast */
97 unsigned int rx_seac0 :1 ; /* frame-copied C-indicator */
98 unsigned int rx_seac1 :1 ; /* address-match A-indicator */
99 unsigned int rx_seac2 :1 ; /* frame-error E-indicator */
[all …]
/linux/drivers/net/fddi/skfp/
H A Dpcmplc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
67 #define GO_STATE(x) (mib->fddiPORTPCMState = (x)|AFLAG)
68 #define ACTIONS_DONE() (mib->fddiPORTPCMState &= ~AFLAG)
109 * PCL-S control register
110 * this register in the PLC-S controls the scrambling parameters
121 * PCL-S control register
122 * this register in the PLC-S controls the scrambling parameters
152 #define PLC_MS(m) ((int)((0x10000L-(m*100000L/2048))))
157 int timer ; /* relative plc timer address */ member
202 * SMT timer interface
[all …]
/linux/
H A DMAINTAINERS5 ----------
[all...]
H A DCREDITS1 This is at least a partial credits-file of people that have
4 scripts. The fields are: name (N), email (E), web-address
6 snail-mail address (S).
10 ----------
55 D: in-kernel DRM Maintainer
75 E: tim_alpaerts@toyota-motor-europe.com
79 S: B-2610 Wilrijk-Antwerpen
105 D: Maintainer of ide-cd and Uniform CD-ROM driver,
106 D: ATAPI CD-Changer support, Major 2.1.x CD-ROM update.
114 D: Linux/PA-RISC hacker
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/linux/drivers/ata/
H A Dsata_mv.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * sata_mv.c - Marvell SATA support
5 * Copyright 2008-2009: Marvell Corporation, all rights reserved.
12 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
18 * --> Develop a low-power-consumption strategy, and implement it.
20 * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
22 * --> [Experiment, Marvell value added] Is it possible to use target
23 * mode to cross-connect two Linux boxes with Marvell cards? If so,
31 * 80x1-B2 errata PCI#11:
34 * should be careful to insert those cards only onto PCI-X bus #0,
[all …]