/freebsd/sys/contrib/device-tree/src/arm/samsung/ |
H A D | exynos5800.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 20 compatible = "samsung,exynos5800-clock", "syscon"; 24 opp-2000000000 { 25 opp-hz = /bits/ 64 <2000000000>; 26 opp-microvolt = <1312500 1312500 1500000>; 27 clock-latency-ns = <140000>; 29 opp-1900000000 { 30 opp-hz = /bits/ 64 <1900000000>; 31 opp-microvolt = <1262500 1262500 1500000>; 32 clock-latency-ns = <140000>; [all …]
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H A D | exynos4212.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 23 #address-cells = <1>; 24 #size-cells = <0>; 26 cpu-map { 39 compatible = "arm,cortex-a9"; 42 clock-names = "cpu"; 43 operating-points-v2 = <&cpu0_opp_table>; 44 #cooling-cells = <2>; /* min followed by max */ 49 compatible = "arm,cortex-a9"; 52 clock-names = "cpu"; [all …]
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H A D | exynos4412.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 23 #address-cells = <1>; 24 #size-cells = <0>; 26 cpu-map { 45 compatible = "arm,cortex-a9"; 48 clock-names = "cpu"; 49 operating-points-v2 = <&cpu0_opp_table>; 50 #cooling-cells = <2>; /* min followed by max */ 55 compatible = "arm,cortex-a9"; 58 clock-names = "cpu"; [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/amlogic/ |
H A D | meson-gx-mali450.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 gpu_opp_table: opp-table { 9 compatible = "operating-points-v2"; 11 opp-125000000 { 12 opp-hz = /bits/ 64 <125000000>; 13 opp-microvolt = <950000>; 15 opp-250000000 { 16 opp-hz = /bits/ 64 <250000000>; 17 opp-microvolt = <950000>; 19 opp-285714285 { [all …]
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H A D | meson-gxm.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 #include "meson-gxl.dtsi" 10 compatible = "amlogic,meson-gxm"; 13 cpu-map { 46 capacity-dmips-mhz = <1024>; 50 capacity-dmips-mhz = <1024>; 54 capacity-dmips-mhz = <1024>; 58 capacity-dmips-mhz = <1024>; 63 compatible = "arm,cortex-a53"; 65 enable-method = "psci"; [all …]
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/freebsd/sys/contrib/device-tree/Bindings/opp/ |
H A D | operating-points-v2-ti-cpu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/opp/operating-points-v2-ti-cpu.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: TI CPU OPP (Operating Performance Points) 12 OPP vary based on the silicon variant used. The data sheet sections 18 This document extends the operating-points-v2 binding by providing 22 - Dhruva Gole <d-gole@ti.com> 25 - $ref: opp-v2-base.yaml# 29 const: operating-points-v2-ti-cpu [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/rockchip/ |
H A D | rk3588j.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 #include "rk3588-extra.dtsi" 10 cluster0_opp_table: opp-table-cluster0 { 11 compatible = "operating-points-v2"; 12 opp-shared; 14 opp-1416000000 { 15 opp-hz = /bits/ 64 <1416000000>; 16 opp-microvolt = <750000 750000 950000>; 17 clock-latency-ns = <40000>; 18 opp-suspend; [all …]
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H A D | rk3588-opp.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 4 cluster0_opp_table: opp-table-cluster0 { 5 compatible = "operating-points-v2"; 6 opp-shared; 8 opp-1008000000 { 9 opp-hz = /bits/ 64 <1008000000>; 10 opp-microvolt = <675000 675000 950000>; 11 clock-latency-ns = <40000>; 13 opp-1200000000 { 14 opp-hz = /bits/ 64 <1200000000>; [all …]
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H A D | rk3399.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd 6 #include "rk3399-base.dtsi" 9 cluster0_opp: opp-table-0 { 10 compatible = "operating-points-v2"; 11 opp-shared; 14 opp-hz = /bits/ 64 <408000000>; 15 opp-microvolt = <825000 825000 1250000>; 16 clock-latency-ns = <40000>; 19 opp-hz = /bits/ 64 <600000000>; [all …]
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H A D | rk3399-opp.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd 7 cluster0_opp: opp-table-0 { 8 compatible = "operating-points-v2"; 9 opp-shared; 12 opp-hz = /bits/ 64 <408000000>; 13 opp-microvolt = <825000 825000 1250000>; 14 clock-latency-ns = <40000>; 17 opp-hz = /bits/ 64 <600000000>; 18 opp-microvolt = <825000 825000 1250000>; [all …]
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H A D | rk3399-op1-opp.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd 7 cluster0_opp: opp-table-0 { 8 compatible = "operating-points-v2"; 9 opp-shared; 12 opp-hz = /bits/ 64 <408000000>; 13 opp-microvolt = <800000>; 14 clock-latency-ns = <40000>; 17 opp-hz = /bits/ 64 <600000000>; 18 opp-microvolt = <825000>; [all …]
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H A D | rk3399-op1.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd 9 cluster0_opp: opp-table-0 { 10 compatible = "operating-points-v2"; 11 opp-shared; 14 opp-hz = /bits/ 64 <408000000>; 15 opp-microvolt = <800000>; 16 clock-latency-ns = <40000>; 19 opp-hz = /bits/ 64 <600000000>; 20 opp-microvolt = <825000>; [all …]
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/freebsd/sys/contrib/device-tree/Bindings/cpufreq/ |
H A D | ti-cpufreq.txt | 1 TI CPUFreq and OPP bindings 6 The ti-cpufreq driver can use revision and an efuse value from the SoC to 7 provide the OPP framework with supported hardware information. This is 8 used to determine which OPPs from the operating-points-v2 table get enabled 9 when it is parsed by the OPP framework. 12 -------------------- 14 - operating-points-v2: Phandle to the operating-points-v2 table to use. 16 In 'operating-points-v2' table: 17 - compatible: Should be 18 - 'operating-points-v2-ti-cpu' for am335x, am43xx, and dra7xx/am57xx, [all …]
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/freebsd/sys/contrib/device-tree/Bindings/display/msm/ |
H A D | qcom,sm8450-dpu.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8450-dp [all...] |
H A D | qcom,sm8450-mdss.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8450-mds [all...] |
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/ |
H A D | omap34xx.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ 8 #include <dt-bindings/bus/ti-sysc.h> 9 #include <dt-bindings/media/omap3-isp.h> 16 /* OMAP343x/OMAP35xx variants OPP1-6 */ 17 operating-points-v2 = <&cpu0_opp_table>; 19 clock-latency = <300000>; /* From legacy driver */ 20 #cooling-cells = <2>; 24 cpu0_opp_table: opp-table { 25 compatible = "operating-points-v2-ti-cpu"; [all …]
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H A D | am33xx.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ 8 #include <dt-bindings/bus/ti-sysc.h> 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/pinctrl/am33xx.h> 11 #include <dt-bindings/clock/am3.h> 15 interrupt-parent = <&intc>; 16 #address-cells = <1>; 17 #size-cells = <1>; 30 d-can0 = &dcan0; [all …]
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/freebsd/sys/contrib/device-tree/src/arm/nvidia/ |
H A D | tegra30-asus-tf201.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include "tegra30-asus-transformer-common.dtsi" 5 #include "tegra30-asus-lvds-display.dtsi" 19 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 27 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 35 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 43 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 51 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 57 /* Azurewave AW-NH615 BCM4329B1 */ [all …]
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H A D | tegra30-peripherals-opp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 4 core_opp_table: opp-table-core { 5 compatible = "operating-points-v2"; 6 opp-shared; 8 core_opp_950: opp-950000 { 9 opp-microvolt = <950000 950000 1350000>; 10 opp-level = <950000>; 13 core_opp_1000: opp-1000000 { 14 opp-microvolt = <1000000 1000000 1350000>; 15 opp-level = <1000000>; [all …]
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/freebsd/sys/contrib/device-tree/src/arm/st/ |
H A D | stih418-b2264.dts | 1 // SPDX-License-Identifier: GPL-2.0-only 6 /dts-v1/; 8 #include <dt-bindings/gpio/gpio.h> 11 compatible = "st,stih418-b2264", "st,stih418"; 14 stdout-path = &sbc_serial0; 24 operating-points-v [all...] |
/freebsd/sys/contrib/device-tree/src/arm64/socionext/ |
H A D | uniphier-ld20.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 5 // Copyright (C) 2015-2016 Socionext Inc. 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/uniphier-gpio.h> 10 #include <dt-bindings/interrupt-controller/arm-gi [all...] |
H A D | uniphier-ld11.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/uniphier-gpio.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 13 compatible = "socionext,uniphier-ld1 [all...] |
/freebsd/sys/contrib/device-tree/src/arm64/exynos/ |
H A D | exynos5433.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 16 #include <dt-bindings/clock/exynos5433.h> 17 #include <dt-bindings/interrupt-controller/arm-gic.h> 21 #address-cells = <2>; 22 #size-cells = <2>; 24 interrupt-parent = <&gic>; 26 arm-a53-pmu { 27 compatible = "arm,cortex-a53-pmu"; 32 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 35 arm-a57-pmu { [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/zte/ |
H A D | zx296718.dtsi | 5 * This file is dual-licensed: you can use it either under the terms 44 #include <dt-bindings/input/input.h> 45 #include <dt-bindings/interrupt-controller/arm-gic.h> 46 #include <dt-bindings/gpio/gpio.h> 47 #include <dt-bindings/clock/zx296718-clock.h> 51 #address-cells = <1>; 52 #size-cells = <1>; 53 interrupt-parent = <&gic>; 67 #address-cells = <2>; 68 #size-cells = <0>; [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/renesas/ |
H A D | r8a779f0.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 3 * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC 8 #include <dt-bindings/clock/r8a779f0-cpg-mssr.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 #include <dt-bindings/power/r8a779f0-sysc.h> 14 #address-cells = <2>; 15 #size-cells = <2>; 17 cluster01_opp: opp-table-0 { 18 compatible = "operating-points-v2"; 19 opp-shared; [all …]
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