| /linux/Documentation/devicetree/bindings/timer/ |
| H A D | xlnx,xps-timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/timer/xlnx,xps-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx LogiCORE IP AXI Timer
10 - Sean Anderson <sean.anderson@seco.com>
15 const: xlnx,xps-timer-1.00.a
20 clock-names:
29 '#pwm-cells': true
31 xlnx,count-width:
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| H A D | nvidia,tegra-timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/timer/nvidia,tegra-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra timer
10 - Stephen Warren <swarren@nvidia.com>
13 - if:
17 const: nvidia,tegra210-timer
25 A list of 14 interrupts; one per each timer channels 0 through 13
27 - if:
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| H A D | arm,sp804.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/arm,sp804.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Haojian Zhuang <haojian.zhuang@linaro.org>
14 16 or 32 bit operation and capable of running in one-shot, periodic, or
15 free-running mode. The input clock is shared, but can be gated and prescaled
16 independently for each timer.
18 There is a viriant of Arm SP804: Hisilicon 64-bit SP804 timer. Some Hisilicon
27 - arm,sp804
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| H A D | samsung,exynos4210-mct.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/samsung,exynos4210-mct.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC Multi Core Timer (MCT)
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
14 global timer and CPU local timers. The global timer is a 64-bit free running
15 up-counter and can generate 4 interrupts when the counter reaches one of the
16 four preset counter values. The CPU local timers are 32-bit free running
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| H A D | nvidia,tegra186-timer.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 timer
10 - Thierry Reding <treding@nvidia.com>
13 The Tegra timer provides 29-bit timer counters and a 32-bit timestamp
14 counter. Each NV timer selects its timing reference signal from the 1 MHz
16 programmed to generate one-shot, periodic, or watchdog interrupts.
22 - const: nvidia,tegra186-timer
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| H A D | cnxt,cx92755-timer.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cnxt,cx92755-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Conexant Digicolor SoCs Timer Controller
10 - Baruch Siach <baruch@tkos.co.il>
14 const: cnxt,cx92755-timer
20 description: Contains 8 interrupts, one for each timer
22 - description: interrupt for timer 0
23 - description: interrupt for timer 1
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| H A D | riscv,timer.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/riscv,timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V timer
10 - Anup Patel <anup@brainfault.org>
13 RISC-V platforms always have a RISC-V timer device for the supervisor-mode
14 based on the time CSR defined by the RISC-V privileged specification. The
15 timer interrupts of this device are configured using the RISC-V SBI Time
16 extension or the RISC-V Sstc extension.
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| H A D | faraday,fttmr010.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/faraday,fttmr010.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Faraday FTTMR010 timer
10 - Joel Stanley <joel@jms.id.au>
11 - Linus Walleij <linus.walleij@linaro.org>
14 This timer is a generic IP block from Faraday Technology, embedded in the
20 - items:
21 - const: moxa,moxart-timer
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| H A D | ingenic,sysost.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/ingenic,sysost.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
13 The SYSOST in an Ingenic SoC provides one 64bit timer for clocksource
14 and one or more 32bit timers for clockevent.
17 "#clock-cells":
22 - ingenic,x1000-ost
23 - ingenic,x2000-ost
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| /linux/Documentation/virt/kvm/x86/ |
| H A D | timekeeping.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Timekeeping Virtualization for X86-Based Architectures
20 One of the most complicated parts of the X86 platform, and specifically,
32 information relevant to KVM and hardware-based virtualization.
41 2.1. i8254 - PIT
42 ----------------
44 One of the first timer devices available is the programmable interrupt timer,
46 channels which can be programmed to deliver periodic or one-shot interrupts.
53 The PIT uses I/O ports 0x40 - 0x43. Access to the 16-bit counters is done
55 available, but not all modes are available to all timers, as only timer 2
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| /linux/Documentation/sound/ |
| H A D | utimers.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Userspace-driven timers
12 This document describes the userspace-driven timers: virtual ALSA timers
15 stream with timer sources which we don't have ALSA timers exported for
17 two virtual sound devices using ``snd-aloop`` (for instance, when
18 we have a network application sending frames to one snd-aloop device,
19 and another sound application listening on the other end of snd-aloop).
21 Enabling userspace-driven timers
24 The userspace-driven timers could be enabled in the kernel using the
28 Userspace-driven timers API
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| /linux/arch/arm/mach-at91/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
18 bool "SAM Cortex-M7 family" if ARM_SINGLE_ARMV7M
38 Select this if ou are using one of Microchip's SAMA5D2 family SoC.
49 Select this if you are using one of Microchip's SAMA5D3 family SoC.
63 Select this if you are using one of Microchip's SAMA5D4 family SoC.
74 Select this if you are using one of Microchip's SAMA7D65 family SoC.
85 Select this if you are using one of Microchip's SAMA7G5 family SoC.
125 Select this if you are using one of those Microchip SoC:
178 bool "Periodic Interval Timer (PIT) support"
184 Timer. It has a relatively low resolution and the TC Block clocksource
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| /linux/Documentation/devicetree/bindings/watchdog/ |
| H A D | marvell,cn10624-wdt.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/marvell,cn10624-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell Global Timer (GTI) system watchdog
10 - Bharat Bhushan <bbhushan2@marvell.com>
13 - $ref: watchdog.yaml#
18 - enum:
19 - marvell,cn9670-wdt
20 - marvell,cn10624-wdt
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| H A D | cnxt,cx92755-wdt.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/watchdog/cnxt,cx92755-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Conexant Digicolor SoCs Watchdog timer
12 timer counters. The first timer (called "Timer A") is the only one that can be
16 - Baruch Siach <baruch@tkos.co.il>
19 - $ref: watchdog.yaml#
23 const: cnxt,cx92755-wdt
32 - compatible
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| /linux/include/soc/at91/ |
| H A D | atmel_tcb.h | 2 * Timer/Counter Unit (TC) registers.
17 * Many 32-bit Atmel SOCs include one or more TC blocks, each of which holds
18 * three general-purpose 16-bit timers. These timers share one register bank.
19 * Depending on the SOC, each timer may have its own clock and IRQ, or those
23 * clocks or clock gates, and per-timer TIOA and TIOB signals used for PWM
37 * struct atmel_tcb_config - SoC data for a Timer/Counter Block
38 * @counter_width: size in bits of a timer counter register
39 * @has_gclk: boolean indicating if a timer counter has a generic clock
40 * @has_qdec: boolean indicating if a timer counter has a quadrature
50 * struct atmel_tc - information about a Timer/Counter Block
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| /linux/Documentation/arch/mips/ |
| H A D | ingenic-tcu.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Ingenic JZ47xx SoCs Timer/Counter Unit hardware
7 The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function
11 - JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all
14 - JZ4725B introduced a separate channel, called Operating System Timer
15 (OST). It is a 32-bit programmable timer. On JZ4760B and above, it is
16 64-bit.
18 - Each one of the TCU channels has its own clock, which can be reparented to three
21 - The watchdog and OST hardware blocks also feature a TCSR register with the same
23 - The TCU registers used to gate/ungate can also gate/ungate the watchdog and
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| /linux/drivers/char/ipmi/ |
| H A D | ipmi_watchdog.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * A watchdog timer based upon the IPMI interface.
43 * This is ugly, but I've determined that x86 is the only architecture
57 * The IPMI command/response information for the watchdog timer.
98 * pre-timeout in seconds.
109 * Setting/getting the watchdog timer value. This is for bytes 5 and
135 /* The pre-timeout is disabled by default. */
160 static int ifnum_to_use = -1;
184 return -EINVAL; in set_param_timeout()
187 return -EINVAL; in set_param_timeout()
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| /linux/drivers/clocksource/ |
| H A D | timer-cs5535.c | 1 // SPDX-License-Identifier: GPL-2.0-only
19 #define DRV_NAME "cs5535-clockevt"
26 * We are using the 32.768kHz input clock - it's the only one that has the
53 * as clock event sources - not as good as a HPET or APIC, but certainly
55 * a simplified one designed specifically to act as a clock event source.
59 static void disable_timer(struct cs5535_mfgpt_timer *timer) in disable_timer() argument
62 cs5535_mfgpt_write(timer, MFGPT_REG_SETUP, in disable_timer()
67 static void start_timer(struct cs5535_mfgpt_timer *timer, uint16_t delta) in start_timer() argument
69 cs5535_mfgpt_write(timer, MFGPT_REG_CMP2, delta); in start_timer()
70 cs5535_mfgpt_write(timer, MFGPT_REG_COUNTER, 0); in start_timer()
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| /linux/arch/m68k/include/asm/ |
| H A D | mac_via.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 * via them as are assorted bits and bobs - eg rtc, adb. The picture
59 * state-control line SEL" on all but IIfx
83 /* Macintosh Family Hardware sez: bits 0-2 of VIA1A are volume control
85 * On IIci,IIfx, bits 1-2 are the rest of the CPU ID:
89 * CHRP sez: VIA1A bits 0-2 and 5 are 'unused': if programmed as
112 #define VIA1B_vRTCClk 0x02 /* Real time clock serial-clock line. */
113 #define VIA1B_vRTCData 0x01 /* Real time clock serial-data line. */
117 * correspond to a VIA work-alike named 'EVR'. */
132 * defines the 'Video IRQ' as 0x40 for the 'EVR' VIA work-alike.
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| /linux/Documentation/kernel-hacking/ |
| H A D | locking.rst | 37 +------------------------------------+------------------------------------+
41 +------------------------------------+------------------------------------+
43 +------------------------------------+------------------------------------+
45 +------------------------------------+------------------------------------+
47 +------------------------------------+------------------------------------+
49 +------------------------------------+------------------------------------+
51 +------------------------------------+------------------------------------+
57 +------------------------------------+------------------------------------+
61 +------------------------------------+------------------------------------+
63 +------------------------------------+------------------------------------+
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| /linux/drivers/pwm/ |
| H A D | pwm-stm32-lp.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * STM32 Low-Power Timer PWM driver
9 * Inspired by Gerald Baeza's pwm-stm32 driver
13 #include <linux/mfd/stm32-lptimer.h>
31 /* STM32 Low-Power Timer is preceded by a configurable power-of-2 prescaler */
40 /* Only one PWM on this LPTIMER: enable, prescaler and reload value can be changed */ in stm32_pwm_lp_update_allowed()
41 if (!priv->num_cc_chans) in stm32_pwm_lp_update_allowed()
44 ret = regmap_read(priv->regmap, STM32_LPTIM_CCMR1, &ccmr1); in stm32_pwm_lp_update_allowed()
49 /* More than one channel enabled: enable, prescaler or ARR value can't be changed */ in stm32_pwm_lp_update_allowed()
54 * Only one channel is enabled (or none): check status on the other channel, to in stm32_pwm_lp_update_allowed()
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| H A D | pwm-xilinx.c | 1 // SPDX-License-Identifier: GPL-2.0+
6 * - When changing both duty cycle and period, we may end up with one cycle
8 * may only be reloaded by first stopping them, or by letting them be
13 * - Cannot produce 100% duty cycle by configuring the TLRs. This might be
16 * - Only produces "normal" output.
17 * - Always produces low output if disabled.
20 #include <clocksource/timer-xilinx.h>
22 #include <linux/clk-provider.h>
37 WARN_ON(cycles < 2 || cycles - 2 > priv->max); in xilinx_timer_tlr_cycles()
40 return cycles - 2; in xilinx_timer_tlr_cycles()
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| /linux/Documentation/devicetree/bindings/powerpc/fsl/ |
| H A D | mpic-timer.txt | 4 - compatible: "fsl,mpic-global-timer"
6 - reg : Contains two regions. The first is the main timer register bank
7 (GTCCRxx, GTBCRxx, GTVPRxx, GTDRxx). The second is the timer control
10 - fsl,available-ranges: use <start count> style section to define which
11 timer interrupts can be used. This property is optional; without this,
14 - interrupts: one interrupt per timer in the group, in order, starting
15 with timer zero. If timer-available-ranges is present, only the
19 /* Note that this requires #interrupt-cells to be 4 */
20 timer0: timer@41100 {
21 compatible = "fsl,mpic-global-timer";
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| /linux/kernel/time/ |
| H A D | timer_migration.c | 1 // SPDX-License-Identifier: GPL-2.0-only
15 #include "tick-internal.h"
21 * The timer migration mechanism is built on a hierarchy of groups. The
26 * per node and only the levels above cross the node topology.
34 * GRP0:0 - GRP0:2 GRP0:3 - GRP0:5
37 * CPUS 0-7 8-15 16-23 24-31 32-39 40-47
39 * The groups hold a timer queue of events sorted by expiry time. These
48 * When a CPU is awake, it checks in it's own timer tick the group
53 * If it finds expired timers in one of the group queues it pulls them over
54 * from the idle CPU and runs the timer function. After that it updates the
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| /linux/net/ipv4/ |
| H A D | inet_timewait_sock.c | 1 // SPDX-License-Identifier: GPL-2.0-only
22 * inet_twsk_bind_unhash - unhash a timewait socket from bind hash
33 struct inet_bind2_bucket *tb2 = tw->tw_tb2; in inet_twsk_bind_unhash()
34 struct inet_bind_bucket *tb = tw->tw_tb; in inet_twsk_bind_unhash()
40 tw->tw_tb = NULL; in inet_twsk_bind_unhash()
41 tw->tw_tb in inet_twsk_bind_unhash()
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