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/linux/Documentation/devicetree/bindings/mailbox/
H A Dti,omap-mailbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/ti,omap-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
19 Each mailbox IP block/cluster has a certain number of h/w fifo queues and
26 interrupt configuration registers, and have a rx and tx interrupt source per
28 appropriate programming of the rx and tx interrupt sources on the appropriate
31 The number of h/w fifo queues and interrupt lines dictate the usable
34 h/w fifo queues and interrupt lines between different instances. The interrupt
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/linux/Documentation/devicetree/bindings/net/
H A Dbrcm,systemport.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Florian Fainelli <f.fainelli@gmail.com>
15 - brcm,systemport-v1.00
16 - brcm,systemportlite-v1.00
17 - brcm,systemport
25 - description: interrupt line for RX queues
26 - description: interrupt line for TX queues
27 - description: interrupt line for Wake-on-LAN
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/linux/drivers/net/ethernet/intel/idpf/
H A Didpf_controlq_setup.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * idpf_ctlq_alloc_desc_ring - Allocate Control Queue (CQ) rings
14 size_t size = cq->ring_size * sizeof(struct idpf_ctlq_desc); in idpf_ctlq_alloc_desc_ring()
16 cq->desc_ring.va = idpf_alloc_dma_mem(hw, &cq->desc_ring, size); in idpf_ctlq_alloc_desc_ring()
17 if (!cq->desc_ring.va) in idpf_ctlq_alloc_desc_ring()
18 return -ENOMEM; in idpf_ctlq_alloc_desc_ring()
24 * idpf_ctlq_alloc_bufs - Allocate Control Queue (CQ) buffers
28 * Allocate the buffer head for all control queues, and if it's a receive
36 /* Do not allocate DMA buffers for transmit queues */ in idpf_ctlq_alloc_bufs()
37 if (cq->cq_type == IDPF_CTLQ_TYPE_MAILBOX_TX) in idpf_ctlq_alloc_bufs()
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H A Didpf_txrx.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #define idpf_tx_buf_next(buf) (*(u32 *)&(buf)->priv)
14 * idpf_chk_linearize - Check if skb exceeds max descriptors per packet
37 * idpf_tx_timeout - Respond to a Tx Hang
45 adapter->tx_timeout_count++; in idpf_tx_timeout()
48 adapter->tx_timeout_count, txqueue); in idpf_tx_timeout()
50 set_bit(IDPF_HR_FUNC_RESET, adapter->flag in idpf_tx_timeout()
1115 u32 num; idpf_vector_to_queue_set() local
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H A Didpf_virtchnl.c1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <net/libeth/rx.h>
12 * struct idpf_vc_xn_manager - Manager for tracking transactions
26 * idpf_vid_to_vport - Translate vport id to vport pointer
39 if (adapter->vport_ids[i] == v_id) in idpf_vid_to_vport()
40 return adapter->vports[i]; in idpf_vid_to_vport()
46 * idpf_handle_event_link - Handl
733 idpf_alloc_queue_set(struct idpf_vport * vport,u32 num) idpf_alloc_queue_set() argument
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/linux/drivers/net/ethernet/intel/i40e/
H A Di40e_virtchnl_pf.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
56 * These variables are used to store indices, id's and number of queues
58 * termed as channel and each channel can in-turn have 4 queues which
59 * means max 16 queues overall per VF.
69 u64 count; /* total count of Rx|Tx events */
93 /* VSI indices - actual VSI pointers are maintained in the PF structure
94 * When assigned, these will be non-zero, because VSI 0 is always
100 u8 num_queue_pairs; /* num of qps assigned to VF vsis */
101 u8 num_req_queues; /* num of requested qps */
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H A Di40e.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2013 - 2021 Intel Corporation. */
29 #define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024)
38 (test_bit(I40E_HW_CAP_RSS_AQ, (pf)->hw.caps) ? 4 : 1)
42 (test_bit(I40E_HW_CAP_128_QP_RSS, (pf)->hw.caps) ? 128 : 64)
69 (&(((union i40e_rx_desc *)((R)->desc))[i]))
71 (&(((struct i40e_tx_desc *)((R)->desc))[i]))
73 (&(((struct i40e_tx_context_desc *)((R)->des
951 struct i40e_ring_container rx; global() member
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/linux/drivers/crypto/caam/
H A Ddpseci.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
3 * Copyright 2013-2016 Freescale Semiconductor Inc.
4 * Copyright 2017-2018 NXP
21 * Maximum number of Tx/Rx queues per DPSECI object
26 * All queues considered; see dpseci_set_rx_queue()
28 #define DPSECI_ALL_QUEUES (u8)(-1)
41 * struct dpseci_cfg - Structure representing DPSECI configuration
44 * @num_tx_queues: num of queues towards the SEC
45 * @num_rx_queues: num of queues back from the SEC
49 * valid priorities are configured with values 1-8;
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/linux/arch/arm/boot/dts/axis/
H A Dartpec6.dtsi2 * Device Tree Source for the Axis ARTPEC-6 SoC
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/dma/nbpfaxi.h>
45 #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
51 interrupt-parent = <&intc>;
54 #address-cells = <1>;
55 #size-cells = <0>;
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/linux/arch/arm64/boot/dts/freescale/
H A Ds32g2.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 * Copyright 2017-2021, 2024-2025 NXP
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
18 #address-cells = <2>;
19 #size-cells = <2>;
23 compatible = "arm,scmi-shmem";
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H A Dimx8-ss-conn.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
10 conn_axi_clk: clock-conn-axi {
11 compatible = "fixed-clock";
12 #clock-cells = <0>;
13 clock-frequency = <333333333>;
14 clock-output-names = "conn_axi_clk";
17 conn_ahb_clk: clock-conn-ahb {
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H A Ds32g3.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright 2021-2025 NXP
7 * Andra-Teodora Ilie <andra.ilie@nxp.com>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <0x02>;
16 #size-cells = <0x02>;
19 #address-cells = <1>;
20 #size-cells = <0>;
22 cpu-map {
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/linux/drivers/net/ethernet/broadcom/genet/
H A Dbcmgenet.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2014-2025 Broadcom
23 #include <linux/dma-mapping.h>
48 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_param
1027 STAT_GENET_Q(num) global() argument
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/linux/drivers/net/ethernet/amazon/ena/
H A Dena_netdev.h1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
3 * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved.
61 #define ENA_DEFAULT_RX_COPYBREAK (256 - NET_IP_ALIGN)
78 /* Refill Rx queue when number of required descriptors is above
84 /* Number of queues to check for missing queues per timer service */
89 #define ENA_TX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
91 #define ENA_RX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
93 (((idx) + (n)) & ((ring_size) - 1))
98 #define ENA_IO_RXQ_IDX_TO_COMBINED_IDX(q) (((q) - 1) / 2)
139 * the xdp queues
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H A Dena_xdp.c1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
3 * Copyright 2015-2021 Amazon.com, Inc. or its affiliates. All rights reserved.
12 tx_info = &tx_ring->tx_buffer_info[req_id]; in validate_xdp_req_id()
13 if (likely(tx_info->xdpf)) in validate_xdp_req_id()
24 struct ena_adapter *adapter = tx_ring->adapter; in ena_xdp_tx_map_frame()
31 tx_info->xdpf = xdpf; in ena_xdp_tx_map_frame()
32 data = tx_info->xdpf->data; in ena_xdp_tx_map_frame()
33 size = tx_info->xdpf->len; in ena_xdp_tx_map_frame()
35 if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { in ena_xdp_tx_map_frame()
37 push_len = min_t(u32, size, tx_ring->tx_max_header_size); in ena_xdp_tx_map_frame()
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H A Dena_netdev.c1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
3 * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved.
57 if (txqueue >= adapter->num_io_queues) { in ena_tx_timeout()
62 threshold = jiffies_to_usecs(dev->watchdog_timeo); in ena_tx_timeout()
63 tx_ring = &adapter->tx_ring[txqueue]; in ena_tx_timeout()
65 time_since_last_napi = jiffies_to_usecs(jiffies - tx_ring->tx_stats.last_napi_jiffies); in ena_tx_timeout()
66 napi_scheduled = !!(tx_ring->napi->state & NAPIF_STATE_SCHED); in ena_tx_timeout()
84 if (test_and_set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags)) in ena_tx_timeout()
88 ena_increase_stat(&adapter->dev_stats.tx_timeout, 1, &adapter->syncp); in ena_tx_timeout()
95 for (i = 0; i < adapter->num_io_queues; i++) in update_rx_ring_mtu()
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/linux/arch/arm64/boot/dts/rockchip/
H A Drk3568.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "rk356x-base.dtsi"
11 cpu0_opp_table: opp-table-0 {
12 compatible = "operating-points-v2";
13 opp-shared;
15 opp-408000000 {
16 opp-hz = /bits/ 64 <408000000>;
17 opp-microvolt = <850000 850000 1150000>;
18 clock-latency-ns = <40000>;
21 opp-600000000 {
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/linux/drivers/net/ethernet/cavium/liquidio/
H A Docteon_config.h7 * Copyright (c) 2003-2016 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
25 /*--------------------------CONFIG VALUES------------------------*/
121 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq)
122 #define CFG_GET_IQ_MAX_Q(cfg) ((cfg)->iq.max_iqs)
123 #define CFG_GET_IQ_PENDING_LIST_SIZE(cfg) ((cfg)->iq.pending_list_size)
124 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type)
125 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min)
126 #define CFG_GET_IQ_DB_TIMEOUT(cfg) ((cfg)->iq.db_timeout)
128 #define CFG_GET_IQ_INTR_PKT(cfg) ((cfg)->iq.iq_intr_pkt)
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H A Docteon_device.c7 * Copyright (c) 2003-2016 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
80 /* Num of desc for rx rings */
83 /* Num of desc for tx rings */
109 /* Num of desc for rx rings */
112 /* Num of desc for tx rings */
188 /* Num of desc for rx rings */
191 /* Num of desc for tx rings */
217 /* Num of desc for rx rings */
220 /* Num of desc for tx rings */
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/linux/drivers/net/ethernet/google/gve/
H A Dgve.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Copyright (C) 2015-2024 Google LLC
10 #include <linux/dma-mapping.h>
35 /* 1 for management, 1 for rx, 1 for tx */
38 /* Numbers of gve tx/rx stats in stats report. */
45 /* Numbers of NIC tx/rx stats in stats report. */
51 #define GVE_DATA_SLOT_ADDR_PAGE_MASK (~(PAGE_SIZE - 1))
71 (GVE_ADMINQ_BUFFER_SIZE / sizeof(((struct gve_adminq_queried_flow_rule *)0)->location))
89 /* 2K buffers for DQO-QPL */
95 * allocs and uses a non-qpl page on the receive path of DQO QPL to free
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/linux/include/xen/interface/io/
H A Dnetif.h1 /* SPDX-License-Identifier: MIT */
5 * Unified network-device I/O interface for Xen guest OSes.
7 * Copyright (c) 2003-2004, Keir Fraser
37 * If the client sends notification for rx requests then it should specify
38 * feature 'feature-rx-notify' via xenbus. Otherwise the backend will assume
43 * "feature-split-event-channels" is introduced to separate guest TX
44 * and RX notification. Backend either doesn't support this feature or
48 * channels for TX and RX, advertise them to backend as
49 * "event-channel-tx" and "event-channel-rx" respectively. If frontend
50 * doesn't want to use this feature, it just writes "event-channel"
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/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex5.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/clock/intel,agilex5-clkmgr.h>
14 compatible = "intel,socfpga-agilex5";
15 #address-cells = <2>;
16 #size-cells = <2>;
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/linux/tools/testing/selftests/drivers/net/hw/
H A Dncdevmem.c1 // SPDX-License-Identifier: GPL-2.0
9 * ncdevmem -s <server IP> [-c <client IP>] -f eth1 -l -p 5201
12 * echo -n "hello\nworld" | \
13 * ncdevmem -
252 int num = -1; rxq_num() local
357 configure_channels(unsigned int rx,unsigned int tx) configure_channels() argument
399 bind_rx_queue(unsigned int ifindex,unsigned int dmabuf_fd,struct netdev_queue_id * queues,unsigned int n_queue_index,struct ynl_sock ** ys) bind_rx_queue() argument
526 struct netdev_queue_id *queues; create_queues() local
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/linux/drivers/net/ethernet/intel/ice/
H A Dice.h1 /* SPDX-License-Identifier: GPL-2.0 */
19 #include <linux/dma-mapping.h>
89 #define ICE_MAX_NUM_DESC_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? \
115 #define ICE_MAX_RXQS_PER_TC 256 /* Used when setting VSI context per TC Rx queues */
125 #define ICE_MAX_MTU (ICE_AQ_SET_MAC_FRAME_SIZE_MAX - ICE_ETH_PKT_HDR_PAD)
133 #define ICE_TX_DESC(R, i) (&(((struct ice_tx_desc *)((R)->desc))[i]))
134 #define ICE_RX_DESC(R, i) (&(((union ice_32b_rx_flex_desc *)((R)->des
480 struct ice_ring_container rx; global() member
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/linux/drivers/net/
H A Dxen-netfront.c4 * Copyright (c) 2002-2005, K A Fraser
67 "Maximum number of queues per virtual interface");
81 #define NETFRONT_SKB_CB(skb) ((struct netfront_cb *)((skb)->cb))
88 /* Minimum number of Rx slots (includes slot for GSO metadata). */
91 /* Queue name is interface name with "-qNNN" appended */
94 /* IRQ name is queue name with "-tx" or "-rx" appended */
108 unsigned int id; /* Queue ID, 0-based */
109 char name[QUEUE_NAME_SIZE]; /* DEVNAME-q
144 struct xen_netif_rx_front_ring rx; global() member
167 struct netfront_queue *queues; global() member
187 struct xen_netif_rx_response rx; global() member
968 xennet_run_xdp(struct netfront_queue * queue,struct page * pdata,struct xen_netif_rx_response * rx,struct bpf_prog * prog,struct xdp_buff * xdp,bool * need_xdp_flush) xennet_run_xdp() argument
1026 struct xen_netif_rx_response *rx = &rinfo->rx, rx_local; xennet_get_responses() local
1172 struct xen_netif_rx_response rx; xennet_fill_frags() local
1269 struct xen_netif_rx_response *rx = &rinfo.rx; xennet_poll() local
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