1f21fb3edSRaghu Vatsavayi /**********************************************************************
2f21fb3edSRaghu Vatsavayi * Author: Cavium, Inc.
3f21fb3edSRaghu Vatsavayi *
4f21fb3edSRaghu Vatsavayi * Contact: support@cavium.com
5f21fb3edSRaghu Vatsavayi * Please include "LiquidIO" in the subject.
6f21fb3edSRaghu Vatsavayi *
750579d3dSRaghu Vatsavayi * Copyright (c) 2003-2016 Cavium, Inc.
8f21fb3edSRaghu Vatsavayi *
9f21fb3edSRaghu Vatsavayi * This file is free software; you can redistribute it and/or modify
10f21fb3edSRaghu Vatsavayi * it under the terms of the GNU General Public License, Version 2, as
11f21fb3edSRaghu Vatsavayi * published by the Free Software Foundation.
12f21fb3edSRaghu Vatsavayi *
13f21fb3edSRaghu Vatsavayi * This file is distributed in the hope that it will be useful, but
14f21fb3edSRaghu Vatsavayi * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15f21fb3edSRaghu Vatsavayi * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
1650579d3dSRaghu Vatsavayi * NONINFRINGEMENT. See the GNU General Public License for more details.
1750579d3dSRaghu Vatsavayi ***********************************************************************/
18f21fb3edSRaghu Vatsavayi #include <linux/pci.h>
19f21fb3edSRaghu Vatsavayi #include <linux/netdevice.h>
205b173cf9SRaghu Vatsavayi #include <linux/vmalloc.h>
21f21fb3edSRaghu Vatsavayi #include "liquidio_common.h"
22f21fb3edSRaghu Vatsavayi #include "octeon_droq.h"
23f21fb3edSRaghu Vatsavayi #include "octeon_iq.h"
24f21fb3edSRaghu Vatsavayi #include "response_manager.h"
25f21fb3edSRaghu Vatsavayi #include "octeon_device.h"
26f21fb3edSRaghu Vatsavayi #include "octeon_main.h"
27f21fb3edSRaghu Vatsavayi #include "octeon_network.h"
28f21fb3edSRaghu Vatsavayi #include "cn66xx_regs.h"
29f21fb3edSRaghu Vatsavayi #include "cn66xx_device.h"
30e86b1ab6SRaghu Vatsavayi #include "cn23xx_pf_device.h"
31111fc64aSRaghu Vatsavayi #include "cn23xx_vf_device.h"
32f21fb3edSRaghu Vatsavayi
33f21fb3edSRaghu Vatsavayi /** Default configuration
34f21fb3edSRaghu Vatsavayi * for CN66XX OCTEON Models.
35f21fb3edSRaghu Vatsavayi */
36f21fb3edSRaghu Vatsavayi static struct octeon_config default_cn66xx_conf = {
37f21fb3edSRaghu Vatsavayi .card_type = LIO_210SV,
38f21fb3edSRaghu Vatsavayi .card_name = LIO_210SV_NAME,
39f21fb3edSRaghu Vatsavayi
40f21fb3edSRaghu Vatsavayi /** IQ attributes */
41f21fb3edSRaghu Vatsavayi .iq = {
42f21fb3edSRaghu Vatsavayi .max_iqs = CN6XXX_CFG_IO_QUEUES,
43f21fb3edSRaghu Vatsavayi .pending_list_size =
44f21fb3edSRaghu Vatsavayi (CN6XXX_MAX_IQ_DESCRIPTORS * CN6XXX_CFG_IO_QUEUES),
45f21fb3edSRaghu Vatsavayi .instr_type = OCTEON_64BYTE_INSTR,
46f21fb3edSRaghu Vatsavayi .db_min = CN6XXX_DB_MIN,
47f21fb3edSRaghu Vatsavayi .db_timeout = CN6XXX_DB_TIMEOUT,
48f21fb3edSRaghu Vatsavayi }
49f21fb3edSRaghu Vatsavayi ,
50f21fb3edSRaghu Vatsavayi
51f21fb3edSRaghu Vatsavayi /** OQ attributes */
52f21fb3edSRaghu Vatsavayi .oq = {
53f21fb3edSRaghu Vatsavayi .max_oqs = CN6XXX_CFG_IO_QUEUES,
54f21fb3edSRaghu Vatsavayi .refill_threshold = CN6XXX_OQ_REFIL_THRESHOLD,
55f21fb3edSRaghu Vatsavayi .oq_intr_pkt = CN6XXX_OQ_INTR_PKT,
56f21fb3edSRaghu Vatsavayi .oq_intr_time = CN6XXX_OQ_INTR_TIME,
57f21fb3edSRaghu Vatsavayi .pkts_per_intr = CN6XXX_OQ_PKTSPER_INTR,
58f21fb3edSRaghu Vatsavayi }
59f21fb3edSRaghu Vatsavayi ,
60f21fb3edSRaghu Vatsavayi
61f21fb3edSRaghu Vatsavayi .num_nic_ports = DEFAULT_NUM_NIC_PORTS_66XX,
62f21fb3edSRaghu Vatsavayi .num_def_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS,
63f21fb3edSRaghu Vatsavayi .num_def_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS,
64f21fb3edSRaghu Vatsavayi .def_rx_buf_size = CN6XXX_OQ_BUF_SIZE,
65f21fb3edSRaghu Vatsavayi
66f21fb3edSRaghu Vatsavayi /* For ethernet interface 0: Port cfg Attributes */
67f21fb3edSRaghu Vatsavayi .nic_if_cfg[0] = {
68f21fb3edSRaghu Vatsavayi /* Max Txqs: Half for each of the two ports :max_iq/2 */
69f21fb3edSRaghu Vatsavayi .max_txqs = MAX_TXQS_PER_INTF,
70f21fb3edSRaghu Vatsavayi
71f21fb3edSRaghu Vatsavayi /* Actual configured value. Range could be: 1...max_txqs */
72f21fb3edSRaghu Vatsavayi .num_txqs = DEF_TXQS_PER_INTF,
73f21fb3edSRaghu Vatsavayi
74f21fb3edSRaghu Vatsavayi /* Max Rxqs: Half for each of the two ports :max_oq/2 */
75f21fb3edSRaghu Vatsavayi .max_rxqs = MAX_RXQS_PER_INTF,
76f21fb3edSRaghu Vatsavayi
77f21fb3edSRaghu Vatsavayi /* Actual configured value. Range could be: 1...max_rxqs */
78f21fb3edSRaghu Vatsavayi .num_rxqs = DEF_RXQS_PER_INTF,
79f21fb3edSRaghu Vatsavayi
80f21fb3edSRaghu Vatsavayi /* Num of desc for rx rings */
81f21fb3edSRaghu Vatsavayi .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS,
82f21fb3edSRaghu Vatsavayi
83f21fb3edSRaghu Vatsavayi /* Num of desc for tx rings */
84f21fb3edSRaghu Vatsavayi .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS,
85f21fb3edSRaghu Vatsavayi
86f21fb3edSRaghu Vatsavayi /* SKB size, We need not change buf size even for Jumbo frames.
87f21fb3edSRaghu Vatsavayi * Octeon can send jumbo frames in 4 consecutive descriptors,
88f21fb3edSRaghu Vatsavayi */
89f21fb3edSRaghu Vatsavayi .rx_buf_size = CN6XXX_OQ_BUF_SIZE,
90f21fb3edSRaghu Vatsavayi
91f21fb3edSRaghu Vatsavayi .base_queue = BASE_QUEUE_NOT_REQUESTED,
92f21fb3edSRaghu Vatsavayi
93f21fb3edSRaghu Vatsavayi .gmx_port_id = 0,
94f21fb3edSRaghu Vatsavayi },
95f21fb3edSRaghu Vatsavayi
96f21fb3edSRaghu Vatsavayi .nic_if_cfg[1] = {
97f21fb3edSRaghu Vatsavayi /* Max Txqs: Half for each of the two ports :max_iq/2 */
98f21fb3edSRaghu Vatsavayi .max_txqs = MAX_TXQS_PER_INTF,
99f21fb3edSRaghu Vatsavayi
100f21fb3edSRaghu Vatsavayi /* Actual configured value. Range could be: 1...max_txqs */
101f21fb3edSRaghu Vatsavayi .num_txqs = DEF_TXQS_PER_INTF,
102f21fb3edSRaghu Vatsavayi
103f21fb3edSRaghu Vatsavayi /* Max Rxqs: Half for each of the two ports :max_oq/2 */
104f21fb3edSRaghu Vatsavayi .max_rxqs = MAX_RXQS_PER_INTF,
105f21fb3edSRaghu Vatsavayi
106f21fb3edSRaghu Vatsavayi /* Actual configured value. Range could be: 1...max_rxqs */
107f21fb3edSRaghu Vatsavayi .num_rxqs = DEF_RXQS_PER_INTF,
108f21fb3edSRaghu Vatsavayi
109f21fb3edSRaghu Vatsavayi /* Num of desc for rx rings */
110f21fb3edSRaghu Vatsavayi .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS,
111f21fb3edSRaghu Vatsavayi
112f21fb3edSRaghu Vatsavayi /* Num of desc for tx rings */
113f21fb3edSRaghu Vatsavayi .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS,
114f21fb3edSRaghu Vatsavayi
115f21fb3edSRaghu Vatsavayi /* SKB size, We need not change buf size even for Jumbo frames.
116f21fb3edSRaghu Vatsavayi * Octeon can send jumbo frames in 4 consecutive descriptors,
117f21fb3edSRaghu Vatsavayi */
118f21fb3edSRaghu Vatsavayi .rx_buf_size = CN6XXX_OQ_BUF_SIZE,
119f21fb3edSRaghu Vatsavayi
120f21fb3edSRaghu Vatsavayi .base_queue = BASE_QUEUE_NOT_REQUESTED,
121f21fb3edSRaghu Vatsavayi
122f21fb3edSRaghu Vatsavayi .gmx_port_id = 1,
123f21fb3edSRaghu Vatsavayi },
124f21fb3edSRaghu Vatsavayi
125f21fb3edSRaghu Vatsavayi /** Miscellaneous attributes */
126f21fb3edSRaghu Vatsavayi .misc = {
127f21fb3edSRaghu Vatsavayi /* Host driver link query interval */
128f21fb3edSRaghu Vatsavayi .oct_link_query_interval = 100,
129f21fb3edSRaghu Vatsavayi
130f21fb3edSRaghu Vatsavayi /* Octeon link query interval */
131f21fb3edSRaghu Vatsavayi .host_link_query_interval = 500,
132f21fb3edSRaghu Vatsavayi
133f21fb3edSRaghu Vatsavayi .enable_sli_oq_bp = 0,
134f21fb3edSRaghu Vatsavayi
135f21fb3edSRaghu Vatsavayi /* Control queue group */
136f21fb3edSRaghu Vatsavayi .ctrlq_grp = 1,
137f21fb3edSRaghu Vatsavayi }
138f21fb3edSRaghu Vatsavayi ,
139f21fb3edSRaghu Vatsavayi };
140f21fb3edSRaghu Vatsavayi
141f21fb3edSRaghu Vatsavayi /** Default configuration
142f21fb3edSRaghu Vatsavayi * for CN68XX OCTEON Model.
143f21fb3edSRaghu Vatsavayi */
144f21fb3edSRaghu Vatsavayi
145f21fb3edSRaghu Vatsavayi static struct octeon_config default_cn68xx_conf = {
146f21fb3edSRaghu Vatsavayi .card_type = LIO_410NV,
147f21fb3edSRaghu Vatsavayi .card_name = LIO_410NV_NAME,
148f21fb3edSRaghu Vatsavayi
149f21fb3edSRaghu Vatsavayi /** IQ attributes */
150f21fb3edSRaghu Vatsavayi .iq = {
151f21fb3edSRaghu Vatsavayi .max_iqs = CN6XXX_CFG_IO_QUEUES,
152f21fb3edSRaghu Vatsavayi .pending_list_size =
153f21fb3edSRaghu Vatsavayi (CN6XXX_MAX_IQ_DESCRIPTORS * CN6XXX_CFG_IO_QUEUES),
154f21fb3edSRaghu Vatsavayi .instr_type = OCTEON_64BYTE_INSTR,
155f21fb3edSRaghu Vatsavayi .db_min = CN6XXX_DB_MIN,
156f21fb3edSRaghu Vatsavayi .db_timeout = CN6XXX_DB_TIMEOUT,
157f21fb3edSRaghu Vatsavayi }
158f21fb3edSRaghu Vatsavayi ,
159f21fb3edSRaghu Vatsavayi
160f21fb3edSRaghu Vatsavayi /** OQ attributes */
161f21fb3edSRaghu Vatsavayi .oq = {
162f21fb3edSRaghu Vatsavayi .max_oqs = CN6XXX_CFG_IO_QUEUES,
163f21fb3edSRaghu Vatsavayi .refill_threshold = CN6XXX_OQ_REFIL_THRESHOLD,
164f21fb3edSRaghu Vatsavayi .oq_intr_pkt = CN6XXX_OQ_INTR_PKT,
165f21fb3edSRaghu Vatsavayi .oq_intr_time = CN6XXX_OQ_INTR_TIME,
166f21fb3edSRaghu Vatsavayi .pkts_per_intr = CN6XXX_OQ_PKTSPER_INTR,
167f21fb3edSRaghu Vatsavayi }
168f21fb3edSRaghu Vatsavayi ,
169f21fb3edSRaghu Vatsavayi
170f21fb3edSRaghu Vatsavayi .num_nic_ports = DEFAULT_NUM_NIC_PORTS_68XX,
171f21fb3edSRaghu Vatsavayi .num_def_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS,
172f21fb3edSRaghu Vatsavayi .num_def_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS,
173f21fb3edSRaghu Vatsavayi .def_rx_buf_size = CN6XXX_OQ_BUF_SIZE,
174f21fb3edSRaghu Vatsavayi
175f21fb3edSRaghu Vatsavayi .nic_if_cfg[0] = {
176f21fb3edSRaghu Vatsavayi /* Max Txqs: Half for each of the two ports :max_iq/2 */
177f21fb3edSRaghu Vatsavayi .max_txqs = MAX_TXQS_PER_INTF,
178f21fb3edSRaghu Vatsavayi
179f21fb3edSRaghu Vatsavayi /* Actual configured value. Range could be: 1...max_txqs */
180f21fb3edSRaghu Vatsavayi .num_txqs = DEF_TXQS_PER_INTF,
181f21fb3edSRaghu Vatsavayi
182f21fb3edSRaghu Vatsavayi /* Max Rxqs: Half for each of the two ports :max_oq/2 */
183f21fb3edSRaghu Vatsavayi .max_rxqs = MAX_RXQS_PER_INTF,
184f21fb3edSRaghu Vatsavayi
185f21fb3edSRaghu Vatsavayi /* Actual configured value. Range could be: 1...max_rxqs */
186f21fb3edSRaghu Vatsavayi .num_rxqs = DEF_RXQS_PER_INTF,
187f21fb3edSRaghu Vatsavayi
188f21fb3edSRaghu Vatsavayi /* Num of desc for rx rings */
189f21fb3edSRaghu Vatsavayi .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS,
190f21fb3edSRaghu Vatsavayi
191f21fb3edSRaghu Vatsavayi /* Num of desc for tx rings */
192f21fb3edSRaghu Vatsavayi .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS,
193f21fb3edSRaghu Vatsavayi
194f21fb3edSRaghu Vatsavayi /* SKB size, We need not change buf size even for Jumbo frames.
195f21fb3edSRaghu Vatsavayi * Octeon can send jumbo frames in 4 consecutive descriptors,
196f21fb3edSRaghu Vatsavayi */
197f21fb3edSRaghu Vatsavayi .rx_buf_size = CN6XXX_OQ_BUF_SIZE,
198f21fb3edSRaghu Vatsavayi
199f21fb3edSRaghu Vatsavayi .base_queue = BASE_QUEUE_NOT_REQUESTED,
200f21fb3edSRaghu Vatsavayi
201f21fb3edSRaghu Vatsavayi .gmx_port_id = 0,
202f21fb3edSRaghu Vatsavayi },
203f21fb3edSRaghu Vatsavayi
204f21fb3edSRaghu Vatsavayi .nic_if_cfg[1] = {
205f21fb3edSRaghu Vatsavayi /* Max Txqs: Half for each of the two ports :max_iq/2 */
206f21fb3edSRaghu Vatsavayi .max_txqs = MAX_TXQS_PER_INTF,
207f21fb3edSRaghu Vatsavayi
208f21fb3edSRaghu Vatsavayi /* Actual configured value. Range could be: 1...max_txqs */
209f21fb3edSRaghu Vatsavayi .num_txqs = DEF_TXQS_PER_INTF,
210f21fb3edSRaghu Vatsavayi
211f21fb3edSRaghu Vatsavayi /* Max Rxqs: Half for each of the two ports :max_oq/2 */
212f21fb3edSRaghu Vatsavayi .max_rxqs = MAX_RXQS_PER_INTF,
213f21fb3edSRaghu Vatsavayi
214f21fb3edSRaghu Vatsavayi /* Actual configured value. Range could be: 1...max_rxqs */
215f21fb3edSRaghu Vatsavayi .num_rxqs = DEF_RXQS_PER_INTF,
216f21fb3edSRaghu Vatsavayi
217f21fb3edSRaghu Vatsavayi /* Num of desc for rx rings */
218f21fb3edSRaghu Vatsavayi .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS,
219f21fb3edSRaghu Vatsavayi
220f21fb3edSRaghu Vatsavayi /* Num of desc for tx rings */
221f21fb3edSRaghu Vatsavayi .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS,
222f21fb3edSRaghu Vatsavayi
223f21fb3edSRaghu Vatsavayi /* SKB size, We need not change buf size even for Jumbo frames.
224f21fb3edSRaghu Vatsavayi * Octeon can send jumbo frames in 4 consecutive descriptors,
225f21fb3edSRaghu Vatsavayi */
226f21fb3edSRaghu Vatsavayi .rx_buf_size = CN6XXX_OQ_BUF_SIZE,
227f21fb3edSRaghu Vatsavayi
228f21fb3edSRaghu Vatsavayi .base_queue = BASE_QUEUE_NOT_REQUESTED,
229f21fb3edSRaghu Vatsavayi
230f21fb3edSRaghu Vatsavayi .gmx_port_id = 1,
231f21fb3edSRaghu Vatsavayi },
232f21fb3edSRaghu Vatsavayi
233f21fb3edSRaghu Vatsavayi .nic_if_cfg[2] = {
234f21fb3edSRaghu Vatsavayi /* Max Txqs: Half for each of the two ports :max_iq/2 */
235f21fb3edSRaghu Vatsavayi .max_txqs = MAX_TXQS_PER_INTF,
236f21fb3edSRaghu Vatsavayi
237f21fb3edSRaghu Vatsavayi /* Actual configured value. Range could be: 1...max_txqs */
238f21fb3edSRaghu Vatsavayi .num_txqs = DEF_TXQS_PER_INTF,
239f21fb3edSRaghu Vatsavayi
240f21fb3edSRaghu Vatsavayi /* Max Rxqs: Half for each of the two ports :max_oq/2 */
241f21fb3edSRaghu Vatsavayi .max_rxqs = MAX_RXQS_PER_INTF,
242f21fb3edSRaghu Vatsavayi
243f21fb3edSRaghu Vatsavayi /* Actual configured value. Range could be: 1...max_rxqs */
244f21fb3edSRaghu Vatsavayi .num_rxqs = DEF_RXQS_PER_INTF,
245f21fb3edSRaghu Vatsavayi
246f21fb3edSRaghu Vatsavayi /* Num of desc for rx rings */
247f21fb3edSRaghu Vatsavayi .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS,
248f21fb3edSRaghu Vatsavayi
249f21fb3edSRaghu Vatsavayi /* Num of desc for tx rings */
250f21fb3edSRaghu Vatsavayi .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS,
251f21fb3edSRaghu Vatsavayi
252f21fb3edSRaghu Vatsavayi /* SKB size, We need not change buf size even for Jumbo frames.
253f21fb3edSRaghu Vatsavayi * Octeon can send jumbo frames in 4 consecutive descriptors,
254f21fb3edSRaghu Vatsavayi */
255f21fb3edSRaghu Vatsavayi .rx_buf_size = CN6XXX_OQ_BUF_SIZE,
256f21fb3edSRaghu Vatsavayi
257f21fb3edSRaghu Vatsavayi .base_queue = BASE_QUEUE_NOT_REQUESTED,
258f21fb3edSRaghu Vatsavayi
259f21fb3edSRaghu Vatsavayi .gmx_port_id = 2,
260f21fb3edSRaghu Vatsavayi },
261f21fb3edSRaghu Vatsavayi
262f21fb3edSRaghu Vatsavayi .nic_if_cfg[3] = {
263f21fb3edSRaghu Vatsavayi /* Max Txqs: Half for each of the two ports :max_iq/2 */
264f21fb3edSRaghu Vatsavayi .max_txqs = MAX_TXQS_PER_INTF,
265f21fb3edSRaghu Vatsavayi
266f21fb3edSRaghu Vatsavayi /* Actual configured value. Range could be: 1...max_txqs */
267f21fb3edSRaghu Vatsavayi .num_txqs = DEF_TXQS_PER_INTF,
268f21fb3edSRaghu Vatsavayi
269f21fb3edSRaghu Vatsavayi /* Max Rxqs: Half for each of the two ports :max_oq/2 */
270f21fb3edSRaghu Vatsavayi .max_rxqs = MAX_RXQS_PER_INTF,
271f21fb3edSRaghu Vatsavayi
272f21fb3edSRaghu Vatsavayi /* Actual configured value. Range could be: 1...max_rxqs */
273f21fb3edSRaghu Vatsavayi .num_rxqs = DEF_RXQS_PER_INTF,
274f21fb3edSRaghu Vatsavayi
275f21fb3edSRaghu Vatsavayi /* Num of desc for rx rings */
276f21fb3edSRaghu Vatsavayi .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS,
277f21fb3edSRaghu Vatsavayi
278f21fb3edSRaghu Vatsavayi /* Num of desc for tx rings */
279f21fb3edSRaghu Vatsavayi .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS,
280f21fb3edSRaghu Vatsavayi
281f21fb3edSRaghu Vatsavayi /* SKB size, We need not change buf size even for Jumbo frames.
282f21fb3edSRaghu Vatsavayi * Octeon can send jumbo frames in 4 consecutive descriptors,
283f21fb3edSRaghu Vatsavayi */
284f21fb3edSRaghu Vatsavayi .rx_buf_size = CN6XXX_OQ_BUF_SIZE,
285f21fb3edSRaghu Vatsavayi
286f21fb3edSRaghu Vatsavayi .base_queue = BASE_QUEUE_NOT_REQUESTED,
287f21fb3edSRaghu Vatsavayi
288f21fb3edSRaghu Vatsavayi .gmx_port_id = 3,
289f21fb3edSRaghu Vatsavayi },
290f21fb3edSRaghu Vatsavayi
291f21fb3edSRaghu Vatsavayi /** Miscellaneous attributes */
292f21fb3edSRaghu Vatsavayi .misc = {
293f21fb3edSRaghu Vatsavayi /* Host driver link query interval */
294f21fb3edSRaghu Vatsavayi .oct_link_query_interval = 100,
295f21fb3edSRaghu Vatsavayi
296f21fb3edSRaghu Vatsavayi /* Octeon link query interval */
297f21fb3edSRaghu Vatsavayi .host_link_query_interval = 500,
298f21fb3edSRaghu Vatsavayi
299f21fb3edSRaghu Vatsavayi .enable_sli_oq_bp = 0,
300f21fb3edSRaghu Vatsavayi
301f21fb3edSRaghu Vatsavayi /* Control queue group */
302f21fb3edSRaghu Vatsavayi .ctrlq_grp = 1,
303f21fb3edSRaghu Vatsavayi }
304f21fb3edSRaghu Vatsavayi ,
305f21fb3edSRaghu Vatsavayi };
306f21fb3edSRaghu Vatsavayi
307f21fb3edSRaghu Vatsavayi /** Default configuration
308f21fb3edSRaghu Vatsavayi * for CN68XX OCTEON Model.
309f21fb3edSRaghu Vatsavayi */
310f21fb3edSRaghu Vatsavayi static struct octeon_config default_cn68xx_210nv_conf = {
311f21fb3edSRaghu Vatsavayi .card_type = LIO_210NV,
312f21fb3edSRaghu Vatsavayi .card_name = LIO_210NV_NAME,
313f21fb3edSRaghu Vatsavayi
314f21fb3edSRaghu Vatsavayi /** IQ attributes */
315f21fb3edSRaghu Vatsavayi
316f21fb3edSRaghu Vatsavayi .iq = {
317f21fb3edSRaghu Vatsavayi .max_iqs = CN6XXX_CFG_IO_QUEUES,
318f21fb3edSRaghu Vatsavayi .pending_list_size =
319f21fb3edSRaghu Vatsavayi (CN6XXX_MAX_IQ_DESCRIPTORS * CN6XXX_CFG_IO_QUEUES),
320f21fb3edSRaghu Vatsavayi .instr_type = OCTEON_64BYTE_INSTR,
321f21fb3edSRaghu Vatsavayi .db_min = CN6XXX_DB_MIN,
322f21fb3edSRaghu Vatsavayi .db_timeout = CN6XXX_DB_TIMEOUT,
323f21fb3edSRaghu Vatsavayi }
324f21fb3edSRaghu Vatsavayi ,
325f21fb3edSRaghu Vatsavayi
326f21fb3edSRaghu Vatsavayi /** OQ attributes */
327f21fb3edSRaghu Vatsavayi .oq = {
328f21fb3edSRaghu Vatsavayi .max_oqs = CN6XXX_CFG_IO_QUEUES,
329f21fb3edSRaghu Vatsavayi .refill_threshold = CN6XXX_OQ_REFIL_THRESHOLD,
330f21fb3edSRaghu Vatsavayi .oq_intr_pkt = CN6XXX_OQ_INTR_PKT,
331f21fb3edSRaghu Vatsavayi .oq_intr_time = CN6XXX_OQ_INTR_TIME,
332f21fb3edSRaghu Vatsavayi .pkts_per_intr = CN6XXX_OQ_PKTSPER_INTR,
333f21fb3edSRaghu Vatsavayi }
334f21fb3edSRaghu Vatsavayi ,
335f21fb3edSRaghu Vatsavayi
336f21fb3edSRaghu Vatsavayi .num_nic_ports = DEFAULT_NUM_NIC_PORTS_68XX_210NV,
337f21fb3edSRaghu Vatsavayi .num_def_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS,
338f21fb3edSRaghu Vatsavayi .num_def_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS,
339f21fb3edSRaghu Vatsavayi .def_rx_buf_size = CN6XXX_OQ_BUF_SIZE,
340f21fb3edSRaghu Vatsavayi
341f21fb3edSRaghu Vatsavayi .nic_if_cfg[0] = {
342f21fb3edSRaghu Vatsavayi /* Max Txqs: Half for each of the two ports :max_iq/2 */
343f21fb3edSRaghu Vatsavayi .max_txqs = MAX_TXQS_PER_INTF,
344f21fb3edSRaghu Vatsavayi
345f21fb3edSRaghu Vatsavayi /* Actual configured value. Range could be: 1...max_txqs */
346f21fb3edSRaghu Vatsavayi .num_txqs = DEF_TXQS_PER_INTF,
347f21fb3edSRaghu Vatsavayi
348f21fb3edSRaghu Vatsavayi /* Max Rxqs: Half for each of the two ports :max_oq/2 */
349f21fb3edSRaghu Vatsavayi .max_rxqs = MAX_RXQS_PER_INTF,
350f21fb3edSRaghu Vatsavayi
351f21fb3edSRaghu Vatsavayi /* Actual configured value. Range could be: 1...max_rxqs */
352f21fb3edSRaghu Vatsavayi .num_rxqs = DEF_RXQS_PER_INTF,
353f21fb3edSRaghu Vatsavayi
354f21fb3edSRaghu Vatsavayi /* Num of desc for rx rings */
355f21fb3edSRaghu Vatsavayi .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS,
356f21fb3edSRaghu Vatsavayi
357f21fb3edSRaghu Vatsavayi /* Num of desc for tx rings */
358f21fb3edSRaghu Vatsavayi .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS,
359f21fb3edSRaghu Vatsavayi
360f21fb3edSRaghu Vatsavayi /* SKB size, We need not change buf size even for Jumbo frames.
361f21fb3edSRaghu Vatsavayi * Octeon can send jumbo frames in 4 consecutive descriptors,
362f21fb3edSRaghu Vatsavayi */
363f21fb3edSRaghu Vatsavayi .rx_buf_size = CN6XXX_OQ_BUF_SIZE,
364f21fb3edSRaghu Vatsavayi
365f21fb3edSRaghu Vatsavayi .base_queue = BASE_QUEUE_NOT_REQUESTED,
366f21fb3edSRaghu Vatsavayi
367f21fb3edSRaghu Vatsavayi .gmx_port_id = 0,
368f21fb3edSRaghu Vatsavayi },
369f21fb3edSRaghu Vatsavayi
370f21fb3edSRaghu Vatsavayi .nic_if_cfg[1] = {
371f21fb3edSRaghu Vatsavayi /* Max Txqs: Half for each of the two ports :max_iq/2 */
372f21fb3edSRaghu Vatsavayi .max_txqs = MAX_TXQS_PER_INTF,
373f21fb3edSRaghu Vatsavayi
374f21fb3edSRaghu Vatsavayi /* Actual configured value. Range could be: 1...max_txqs */
375f21fb3edSRaghu Vatsavayi .num_txqs = DEF_TXQS_PER_INTF,
376f21fb3edSRaghu Vatsavayi
377f21fb3edSRaghu Vatsavayi /* Max Rxqs: Half for each of the two ports :max_oq/2 */
378f21fb3edSRaghu Vatsavayi .max_rxqs = MAX_RXQS_PER_INTF,
379f21fb3edSRaghu Vatsavayi
380f21fb3edSRaghu Vatsavayi /* Actual configured value. Range could be: 1...max_rxqs */
381f21fb3edSRaghu Vatsavayi .num_rxqs = DEF_RXQS_PER_INTF,
382f21fb3edSRaghu Vatsavayi
383f21fb3edSRaghu Vatsavayi /* Num of desc for rx rings */
384f21fb3edSRaghu Vatsavayi .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS,
385f21fb3edSRaghu Vatsavayi
386f21fb3edSRaghu Vatsavayi /* Num of desc for tx rings */
387f21fb3edSRaghu Vatsavayi .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS,
388f21fb3edSRaghu Vatsavayi
389f21fb3edSRaghu Vatsavayi /* SKB size, We need not change buf size even for Jumbo frames.
390f21fb3edSRaghu Vatsavayi * Octeon can send jumbo frames in 4 consecutive descriptors,
391f21fb3edSRaghu Vatsavayi */
392f21fb3edSRaghu Vatsavayi .rx_buf_size = CN6XXX_OQ_BUF_SIZE,
393f21fb3edSRaghu Vatsavayi
394f21fb3edSRaghu Vatsavayi .base_queue = BASE_QUEUE_NOT_REQUESTED,
395f21fb3edSRaghu Vatsavayi
396f21fb3edSRaghu Vatsavayi .gmx_port_id = 1,
397f21fb3edSRaghu Vatsavayi },
398f21fb3edSRaghu Vatsavayi
399f21fb3edSRaghu Vatsavayi /** Miscellaneous attributes */
400f21fb3edSRaghu Vatsavayi .misc = {
401f21fb3edSRaghu Vatsavayi /* Host driver link query interval */
402f21fb3edSRaghu Vatsavayi .oct_link_query_interval = 100,
403f21fb3edSRaghu Vatsavayi
404f21fb3edSRaghu Vatsavayi /* Octeon link query interval */
405f21fb3edSRaghu Vatsavayi .host_link_query_interval = 500,
406f21fb3edSRaghu Vatsavayi
407f21fb3edSRaghu Vatsavayi .enable_sli_oq_bp = 0,
408f21fb3edSRaghu Vatsavayi
409f21fb3edSRaghu Vatsavayi /* Control queue group */
410f21fb3edSRaghu Vatsavayi .ctrlq_grp = 1,
411f21fb3edSRaghu Vatsavayi }
412f21fb3edSRaghu Vatsavayi ,
413f21fb3edSRaghu Vatsavayi };
414f21fb3edSRaghu Vatsavayi
415e86b1ab6SRaghu Vatsavayi static struct octeon_config default_cn23xx_conf = {
416e86b1ab6SRaghu Vatsavayi .card_type = LIO_23XX,
417e86b1ab6SRaghu Vatsavayi .card_name = LIO_23XX_NAME,
418e86b1ab6SRaghu Vatsavayi /** IQ attributes */
419e86b1ab6SRaghu Vatsavayi .iq = {
420e86b1ab6SRaghu Vatsavayi .max_iqs = CN23XX_CFG_IO_QUEUES,
421d18ca7dfSIntiyaz Basha .pending_list_size = (CN23XX_DEFAULT_IQ_DESCRIPTORS *
422e86b1ab6SRaghu Vatsavayi CN23XX_CFG_IO_QUEUES),
423e86b1ab6SRaghu Vatsavayi .instr_type = OCTEON_64BYTE_INSTR,
424e86b1ab6SRaghu Vatsavayi .db_min = CN23XX_DB_MIN,
425e86b1ab6SRaghu Vatsavayi .db_timeout = CN23XX_DB_TIMEOUT,
426e86b1ab6SRaghu Vatsavayi .iq_intr_pkt = CN23XX_DEF_IQ_INTR_THRESHOLD,
427e86b1ab6SRaghu Vatsavayi },
428e86b1ab6SRaghu Vatsavayi
429e86b1ab6SRaghu Vatsavayi /** OQ attributes */
430e86b1ab6SRaghu Vatsavayi .oq = {
431e86b1ab6SRaghu Vatsavayi .max_oqs = CN23XX_CFG_IO_QUEUES,
432e86b1ab6SRaghu Vatsavayi .pkts_per_intr = CN23XX_OQ_PKTSPER_INTR,
433e86b1ab6SRaghu Vatsavayi .refill_threshold = CN23XX_OQ_REFIL_THRESHOLD,
434e86b1ab6SRaghu Vatsavayi .oq_intr_pkt = CN23XX_OQ_INTR_PKT,
435e86b1ab6SRaghu Vatsavayi .oq_intr_time = CN23XX_OQ_INTR_TIME,
436e86b1ab6SRaghu Vatsavayi },
437e86b1ab6SRaghu Vatsavayi
438e86b1ab6SRaghu Vatsavayi .num_nic_ports = DEFAULT_NUM_NIC_PORTS_23XX,
439d18ca7dfSIntiyaz Basha .num_def_rx_descs = CN23XX_DEFAULT_OQ_DESCRIPTORS,
440d18ca7dfSIntiyaz Basha .num_def_tx_descs = CN23XX_DEFAULT_IQ_DESCRIPTORS,
441e86b1ab6SRaghu Vatsavayi .def_rx_buf_size = CN23XX_OQ_BUF_SIZE,
442e86b1ab6SRaghu Vatsavayi
443e86b1ab6SRaghu Vatsavayi /* For ethernet interface 0: Port cfg Attributes */
444e86b1ab6SRaghu Vatsavayi .nic_if_cfg[0] = {
445e86b1ab6SRaghu Vatsavayi /* Max Txqs: Half for each of the two ports :max_iq/2 */
446e86b1ab6SRaghu Vatsavayi .max_txqs = MAX_TXQS_PER_INTF,
447e86b1ab6SRaghu Vatsavayi
448e86b1ab6SRaghu Vatsavayi /* Actual configured value. Range could be: 1...max_txqs */
449e86b1ab6SRaghu Vatsavayi .num_txqs = DEF_TXQS_PER_INTF,
450e86b1ab6SRaghu Vatsavayi
451e86b1ab6SRaghu Vatsavayi /* Max Rxqs: Half for each of the two ports :max_oq/2 */
452e86b1ab6SRaghu Vatsavayi .max_rxqs = MAX_RXQS_PER_INTF,
453e86b1ab6SRaghu Vatsavayi
454e86b1ab6SRaghu Vatsavayi /* Actual configured value. Range could be: 1...max_rxqs */
455e86b1ab6SRaghu Vatsavayi .num_rxqs = DEF_RXQS_PER_INTF,
456e86b1ab6SRaghu Vatsavayi
457e86b1ab6SRaghu Vatsavayi /* Num of desc for rx rings */
458d18ca7dfSIntiyaz Basha .num_rx_descs = CN23XX_DEFAULT_OQ_DESCRIPTORS,
459e86b1ab6SRaghu Vatsavayi
460e86b1ab6SRaghu Vatsavayi /* Num of desc for tx rings */
461d18ca7dfSIntiyaz Basha .num_tx_descs = CN23XX_DEFAULT_IQ_DESCRIPTORS,
462e86b1ab6SRaghu Vatsavayi
463e86b1ab6SRaghu Vatsavayi /* SKB size, We need not change buf size even for Jumbo frames.
464e86b1ab6SRaghu Vatsavayi * Octeon can send jumbo frames in 4 consecutive descriptors,
465e86b1ab6SRaghu Vatsavayi */
466e86b1ab6SRaghu Vatsavayi .rx_buf_size = CN23XX_OQ_BUF_SIZE,
467e86b1ab6SRaghu Vatsavayi
468e86b1ab6SRaghu Vatsavayi .base_queue = BASE_QUEUE_NOT_REQUESTED,
469e86b1ab6SRaghu Vatsavayi
470e86b1ab6SRaghu Vatsavayi .gmx_port_id = 0,
471e86b1ab6SRaghu Vatsavayi },
472e86b1ab6SRaghu Vatsavayi
473e86b1ab6SRaghu Vatsavayi .nic_if_cfg[1] = {
474e86b1ab6SRaghu Vatsavayi /* Max Txqs: Half for each of the two ports :max_iq/2 */
475e86b1ab6SRaghu Vatsavayi .max_txqs = MAX_TXQS_PER_INTF,
476e86b1ab6SRaghu Vatsavayi
477e86b1ab6SRaghu Vatsavayi /* Actual configured value. Range could be: 1...max_txqs */
478e86b1ab6SRaghu Vatsavayi .num_txqs = DEF_TXQS_PER_INTF,
479e86b1ab6SRaghu Vatsavayi
480e86b1ab6SRaghu Vatsavayi /* Max Rxqs: Half for each of the two ports :max_oq/2 */
481e86b1ab6SRaghu Vatsavayi .max_rxqs = MAX_RXQS_PER_INTF,
482e86b1ab6SRaghu Vatsavayi
483e86b1ab6SRaghu Vatsavayi /* Actual configured value. Range could be: 1...max_rxqs */
484e86b1ab6SRaghu Vatsavayi .num_rxqs = DEF_RXQS_PER_INTF,
485e86b1ab6SRaghu Vatsavayi
486e86b1ab6SRaghu Vatsavayi /* Num of desc for rx rings */
487d18ca7dfSIntiyaz Basha .num_rx_descs = CN23XX_DEFAULT_OQ_DESCRIPTORS,
488e86b1ab6SRaghu Vatsavayi
489e86b1ab6SRaghu Vatsavayi /* Num of desc for tx rings */
490d18ca7dfSIntiyaz Basha .num_tx_descs = CN23XX_DEFAULT_IQ_DESCRIPTORS,
491e86b1ab6SRaghu Vatsavayi
492e86b1ab6SRaghu Vatsavayi /* SKB size, We need not change buf size even for Jumbo frames.
493e86b1ab6SRaghu Vatsavayi * Octeon can send jumbo frames in 4 consecutive descriptors,
494e86b1ab6SRaghu Vatsavayi */
495e86b1ab6SRaghu Vatsavayi .rx_buf_size = CN23XX_OQ_BUF_SIZE,
496e86b1ab6SRaghu Vatsavayi
497e86b1ab6SRaghu Vatsavayi .base_queue = BASE_QUEUE_NOT_REQUESTED,
498e86b1ab6SRaghu Vatsavayi
499e86b1ab6SRaghu Vatsavayi .gmx_port_id = 1,
500e86b1ab6SRaghu Vatsavayi },
501e86b1ab6SRaghu Vatsavayi
502e86b1ab6SRaghu Vatsavayi .misc = {
503e86b1ab6SRaghu Vatsavayi /* Host driver link query interval */
504e86b1ab6SRaghu Vatsavayi .oct_link_query_interval = 100,
505e86b1ab6SRaghu Vatsavayi
506e86b1ab6SRaghu Vatsavayi /* Octeon link query interval */
507e86b1ab6SRaghu Vatsavayi .host_link_query_interval = 500,
508e86b1ab6SRaghu Vatsavayi
509e86b1ab6SRaghu Vatsavayi .enable_sli_oq_bp = 0,
510e86b1ab6SRaghu Vatsavayi
511e86b1ab6SRaghu Vatsavayi /* Control queue group */
512e86b1ab6SRaghu Vatsavayi .ctrlq_grp = 1,
513e86b1ab6SRaghu Vatsavayi }
514e86b1ab6SRaghu Vatsavayi };
515e86b1ab6SRaghu Vatsavayi
516f21fb3edSRaghu Vatsavayi static struct octeon_config_ptr {
517f21fb3edSRaghu Vatsavayi u32 conf_type;
518f21fb3edSRaghu Vatsavayi } oct_conf_info[MAX_OCTEON_DEVICES] = {
519f21fb3edSRaghu Vatsavayi {
520f21fb3edSRaghu Vatsavayi OCTEON_CONFIG_TYPE_DEFAULT,
521f21fb3edSRaghu Vatsavayi }, {
522f21fb3edSRaghu Vatsavayi OCTEON_CONFIG_TYPE_DEFAULT,
523f21fb3edSRaghu Vatsavayi }, {
524f21fb3edSRaghu Vatsavayi OCTEON_CONFIG_TYPE_DEFAULT,
525f21fb3edSRaghu Vatsavayi }, {
526f21fb3edSRaghu Vatsavayi OCTEON_CONFIG_TYPE_DEFAULT,
527f21fb3edSRaghu Vatsavayi },
528f21fb3edSRaghu Vatsavayi };
529f21fb3edSRaghu Vatsavayi
530f21fb3edSRaghu Vatsavayi static char oct_dev_state_str[OCT_DEV_STATES + 1][32] = {
5319060e6baSIntiyaz Basha "BEGIN", "PCI-ENABLE-DONE", "PCI-MAP-DONE", "DISPATCH-INIT-DONE",
532f21fb3edSRaghu Vatsavayi "IQ-INIT-DONE", "SCBUFF-POOL-INIT-DONE", "RESPLIST-INIT-DONE",
5339060e6baSIntiyaz Basha "DROQ-INIT-DONE", "MBOX-SETUP-DONE", "MSIX-ALLOC-VECTOR-DONE",
5349060e6baSIntiyaz Basha "INTR-SET-DONE", "IO-QUEUES-INIT-DONE", "CONSOLE-INIT-DONE",
535f21fb3edSRaghu Vatsavayi "HOST-READY", "CORE-READY", "RUNNING", "IN-RESET",
536f21fb3edSRaghu Vatsavayi "INVALID"
537f21fb3edSRaghu Vatsavayi };
538f21fb3edSRaghu Vatsavayi
539f21fb3edSRaghu Vatsavayi static char oct_dev_app_str[CVM_DRV_APP_COUNT + 1][32] = {
540f21fb3edSRaghu Vatsavayi "BASE", "NIC", "UNKNOWN"};
541f21fb3edSRaghu Vatsavayi
542f21fb3edSRaghu Vatsavayi static struct octeon_device *octeon_device[MAX_OCTEON_DEVICES];
543e1e3ce62SRick Farrington static atomic_t adapter_refcounts[MAX_OCTEON_DEVICES];
544088b8749SRick Farrington static atomic_t adapter_fw_states[MAX_OCTEON_DEVICES];
545e1e3ce62SRick Farrington
546f21fb3edSRaghu Vatsavayi static u32 octeon_device_count;
547e1e3ce62SRick Farrington /* locks device array (i.e. octeon_device[]) */
54848b219a2SZheng Yongjun static DEFINE_SPINLOCK(octeon_devices_lock);
549f21fb3edSRaghu Vatsavayi
550f21fb3edSRaghu Vatsavayi static struct octeon_core_setup core_setup[MAX_OCTEON_DEVICES];
551f21fb3edSRaghu Vatsavayi
oct_set_config_info(int oct_id,int conf_type)5525b173cf9SRaghu Vatsavayi static void oct_set_config_info(int oct_id, int conf_type)
553f21fb3edSRaghu Vatsavayi {
554f21fb3edSRaghu Vatsavayi if (conf_type < 0 || conf_type > (NUM_OCTEON_CONFS - 1))
555f21fb3edSRaghu Vatsavayi conf_type = OCTEON_CONFIG_TYPE_DEFAULT;
556f21fb3edSRaghu Vatsavayi oct_conf_info[oct_id].conf_type = conf_type;
557f21fb3edSRaghu Vatsavayi }
558f21fb3edSRaghu Vatsavayi
octeon_init_device_list(int conf_type)559f21fb3edSRaghu Vatsavayi void octeon_init_device_list(int conf_type)
560f21fb3edSRaghu Vatsavayi {
561f21fb3edSRaghu Vatsavayi int i;
562f21fb3edSRaghu Vatsavayi
563f21fb3edSRaghu Vatsavayi memset(octeon_device, 0, (sizeof(void *) * MAX_OCTEON_DEVICES));
564f21fb3edSRaghu Vatsavayi for (i = 0; i < MAX_OCTEON_DEVICES; i++)
565f21fb3edSRaghu Vatsavayi oct_set_config_info(i, conf_type);
566f21fb3edSRaghu Vatsavayi }
567f71be9d0SMasahiro Yamada EXPORT_SYMBOL_GPL(octeon_init_device_list);
568f21fb3edSRaghu Vatsavayi
__retrieve_octeon_config_info(struct octeon_device * oct,u16 card_type)569f21fb3edSRaghu Vatsavayi static void *__retrieve_octeon_config_info(struct octeon_device *oct,
570f21fb3edSRaghu Vatsavayi u16 card_type)
571f21fb3edSRaghu Vatsavayi {
572f21fb3edSRaghu Vatsavayi u32 oct_id = oct->octeon_id;
573f21fb3edSRaghu Vatsavayi void *ret = NULL;
574f21fb3edSRaghu Vatsavayi
575f21fb3edSRaghu Vatsavayi switch (oct_conf_info[oct_id].conf_type) {
576f21fb3edSRaghu Vatsavayi case OCTEON_CONFIG_TYPE_DEFAULT:
577f21fb3edSRaghu Vatsavayi if (oct->chip_id == OCTEON_CN66XX) {
57869c69da3SRaghu Vatsavayi ret = &default_cn66xx_conf;
579f21fb3edSRaghu Vatsavayi } else if ((oct->chip_id == OCTEON_CN68XX) &&
580f21fb3edSRaghu Vatsavayi (card_type == LIO_210NV)) {
58169c69da3SRaghu Vatsavayi ret = &default_cn68xx_210nv_conf;
582f21fb3edSRaghu Vatsavayi } else if ((oct->chip_id == OCTEON_CN68XX) &&
583f21fb3edSRaghu Vatsavayi (card_type == LIO_410NV)) {
58469c69da3SRaghu Vatsavayi ret = &default_cn68xx_conf;
585e86b1ab6SRaghu Vatsavayi } else if (oct->chip_id == OCTEON_CN23XX_PF_VID) {
58669c69da3SRaghu Vatsavayi ret = &default_cn23xx_conf;
58769c69da3SRaghu Vatsavayi } else if (oct->chip_id == OCTEON_CN23XX_VF_VID) {
58869c69da3SRaghu Vatsavayi ret = &default_cn23xx_conf;
589f21fb3edSRaghu Vatsavayi }
590f21fb3edSRaghu Vatsavayi break;
591f21fb3edSRaghu Vatsavayi default:
592f21fb3edSRaghu Vatsavayi break;
593f21fb3edSRaghu Vatsavayi }
594f21fb3edSRaghu Vatsavayi return ret;
595f21fb3edSRaghu Vatsavayi }
596f21fb3edSRaghu Vatsavayi
__verify_octeon_config_info(struct octeon_device * oct,void * conf)597f21fb3edSRaghu Vatsavayi static int __verify_octeon_config_info(struct octeon_device *oct, void *conf)
598f21fb3edSRaghu Vatsavayi {
599f21fb3edSRaghu Vatsavayi switch (oct->chip_id) {
600f21fb3edSRaghu Vatsavayi case OCTEON_CN66XX:
601f21fb3edSRaghu Vatsavayi case OCTEON_CN68XX:
602f21fb3edSRaghu Vatsavayi return lio_validate_cn6xxx_config_info(oct, conf);
603e86b1ab6SRaghu Vatsavayi case OCTEON_CN23XX_PF_VID:
60469c69da3SRaghu Vatsavayi case OCTEON_CN23XX_VF_VID:
605e86b1ab6SRaghu Vatsavayi return 0;
606f21fb3edSRaghu Vatsavayi default:
607f21fb3edSRaghu Vatsavayi break;
608f21fb3edSRaghu Vatsavayi }
609f21fb3edSRaghu Vatsavayi
610f21fb3edSRaghu Vatsavayi return 1;
611f21fb3edSRaghu Vatsavayi }
612f21fb3edSRaghu Vatsavayi
oct_get_config_info(struct octeon_device * oct,u16 card_type)613f21fb3edSRaghu Vatsavayi void *oct_get_config_info(struct octeon_device *oct, u16 card_type)
614f21fb3edSRaghu Vatsavayi {
615f21fb3edSRaghu Vatsavayi void *conf = NULL;
616f21fb3edSRaghu Vatsavayi
617f21fb3edSRaghu Vatsavayi conf = __retrieve_octeon_config_info(oct, card_type);
618f21fb3edSRaghu Vatsavayi if (!conf)
619f21fb3edSRaghu Vatsavayi return NULL;
620f21fb3edSRaghu Vatsavayi
621f21fb3edSRaghu Vatsavayi if (__verify_octeon_config_info(oct, conf)) {
622f21fb3edSRaghu Vatsavayi dev_err(&oct->pci_dev->dev, "Configuration verification failed\n");
623f21fb3edSRaghu Vatsavayi return NULL;
624f21fb3edSRaghu Vatsavayi }
625f21fb3edSRaghu Vatsavayi
626f21fb3edSRaghu Vatsavayi return conf;
627f21fb3edSRaghu Vatsavayi }
628f21fb3edSRaghu Vatsavayi
lio_get_state_string(atomic_t * state_ptr)629f21fb3edSRaghu Vatsavayi char *lio_get_state_string(atomic_t *state_ptr)
630f21fb3edSRaghu Vatsavayi {
631f21fb3edSRaghu Vatsavayi s32 istate = (s32)atomic_read(state_ptr);
632f21fb3edSRaghu Vatsavayi
633f21fb3edSRaghu Vatsavayi if (istate > OCT_DEV_STATES || istate < 0)
634f21fb3edSRaghu Vatsavayi return oct_dev_state_str[OCT_DEV_STATE_INVALID];
635f21fb3edSRaghu Vatsavayi return oct_dev_state_str[istate];
636f21fb3edSRaghu Vatsavayi }
637f71be9d0SMasahiro Yamada EXPORT_SYMBOL_GPL(lio_get_state_string);
638f21fb3edSRaghu Vatsavayi
get_oct_app_string(u32 app_mode)639f21fb3edSRaghu Vatsavayi static char *get_oct_app_string(u32 app_mode)
640f21fb3edSRaghu Vatsavayi {
641f21fb3edSRaghu Vatsavayi if (app_mode <= CVM_DRV_APP_END)
642f21fb3edSRaghu Vatsavayi return oct_dev_app_str[app_mode - CVM_DRV_APP_START];
643f21fb3edSRaghu Vatsavayi return oct_dev_app_str[CVM_DRV_INVALID_APP - CVM_DRV_APP_START];
644f21fb3edSRaghu Vatsavayi }
645f21fb3edSRaghu Vatsavayi
octeon_free_device_mem(struct octeon_device * oct)646f21fb3edSRaghu Vatsavayi void octeon_free_device_mem(struct octeon_device *oct)
647f21fb3edSRaghu Vatsavayi {
6481e0d30feSRaghu Vatsavayi int i;
649f21fb3edSRaghu Vatsavayi
65063da8404SRaghu Vatsavayi for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct); i++) {
651763185a3SRaghu Vatsavayi if (oct->io_qmask.oq & BIT_ULL(i))
652f21fb3edSRaghu Vatsavayi vfree(oct->droq[i]);
653f21fb3edSRaghu Vatsavayi }
654f21fb3edSRaghu Vatsavayi
65563da8404SRaghu Vatsavayi for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) {
656763185a3SRaghu Vatsavayi if (oct->io_qmask.iq & BIT_ULL(i))
657f21fb3edSRaghu Vatsavayi vfree(oct->instr_queue[i]);
658f21fb3edSRaghu Vatsavayi }
659f21fb3edSRaghu Vatsavayi
660f21fb3edSRaghu Vatsavayi i = oct->octeon_id;
661f21fb3edSRaghu Vatsavayi vfree(oct);
662f21fb3edSRaghu Vatsavayi
663f21fb3edSRaghu Vatsavayi octeon_device[i] = NULL;
664f21fb3edSRaghu Vatsavayi octeon_device_count--;
665f21fb3edSRaghu Vatsavayi }
666f71be9d0SMasahiro Yamada EXPORT_SYMBOL_GPL(octeon_free_device_mem);
667f21fb3edSRaghu Vatsavayi
octeon_allocate_device_mem(u32 pci_id,u32 priv_size)668f21fb3edSRaghu Vatsavayi static struct octeon_device *octeon_allocate_device_mem(u32 pci_id,
669f21fb3edSRaghu Vatsavayi u32 priv_size)
670f21fb3edSRaghu Vatsavayi {
671f21fb3edSRaghu Vatsavayi struct octeon_device *oct;
672f21fb3edSRaghu Vatsavayi u8 *buf = NULL;
673f21fb3edSRaghu Vatsavayi u32 octdevsize = 0, configsize = 0, size;
674f21fb3edSRaghu Vatsavayi
675f21fb3edSRaghu Vatsavayi switch (pci_id) {
676f21fb3edSRaghu Vatsavayi case OCTEON_CN68XX:
677f21fb3edSRaghu Vatsavayi case OCTEON_CN66XX:
678f21fb3edSRaghu Vatsavayi configsize = sizeof(struct octeon_cn6xxx);
679f21fb3edSRaghu Vatsavayi break;
680f21fb3edSRaghu Vatsavayi
681e86b1ab6SRaghu Vatsavayi case OCTEON_CN23XX_PF_VID:
682e86b1ab6SRaghu Vatsavayi configsize = sizeof(struct octeon_cn23xx_pf);
683e86b1ab6SRaghu Vatsavayi break;
684111fc64aSRaghu Vatsavayi case OCTEON_CN23XX_VF_VID:
685111fc64aSRaghu Vatsavayi configsize = sizeof(struct octeon_cn23xx_vf);
686111fc64aSRaghu Vatsavayi break;
687f21fb3edSRaghu Vatsavayi default:
688f21fb3edSRaghu Vatsavayi pr_err("%s: Unknown PCI Device: 0x%x\n",
689f21fb3edSRaghu Vatsavayi __func__,
690f21fb3edSRaghu Vatsavayi pci_id);
691f21fb3edSRaghu Vatsavayi return NULL;
692f21fb3edSRaghu Vatsavayi }
693f21fb3edSRaghu Vatsavayi
694f21fb3edSRaghu Vatsavayi if (configsize & 0x7)
695f21fb3edSRaghu Vatsavayi configsize += (8 - (configsize & 0x7));
696f21fb3edSRaghu Vatsavayi
697f21fb3edSRaghu Vatsavayi octdevsize = sizeof(struct octeon_device);
698f21fb3edSRaghu Vatsavayi if (octdevsize & 0x7)
699f21fb3edSRaghu Vatsavayi octdevsize += (8 - (octdevsize & 0x7));
700f21fb3edSRaghu Vatsavayi
701f21fb3edSRaghu Vatsavayi if (priv_size & 0x7)
702f21fb3edSRaghu Vatsavayi priv_size += (8 - (priv_size & 0x7));
703f21fb3edSRaghu Vatsavayi
704f21fb3edSRaghu Vatsavayi size = octdevsize + priv_size + configsize +
705f21fb3edSRaghu Vatsavayi (sizeof(struct octeon_dispatch) * DISPATCH_LIST_SIZE);
706f21fb3edSRaghu Vatsavayi
70772bca208SHimanshu Jha buf = vzalloc(size);
708f21fb3edSRaghu Vatsavayi if (!buf)
709f21fb3edSRaghu Vatsavayi return NULL;
710f21fb3edSRaghu Vatsavayi
711f21fb3edSRaghu Vatsavayi oct = (struct octeon_device *)buf;
712f21fb3edSRaghu Vatsavayi oct->priv = (void *)(buf + octdevsize);
713f21fb3edSRaghu Vatsavayi oct->chip = (void *)(buf + octdevsize + priv_size);
714f21fb3edSRaghu Vatsavayi oct->dispatch.dlist = (struct octeon_dispatch *)
715f21fb3edSRaghu Vatsavayi (buf + octdevsize + priv_size + configsize);
716f21fb3edSRaghu Vatsavayi
717f21fb3edSRaghu Vatsavayi return oct;
718f21fb3edSRaghu Vatsavayi }
719f21fb3edSRaghu Vatsavayi
octeon_allocate_device(u32 pci_id,u32 priv_size)720f21fb3edSRaghu Vatsavayi struct octeon_device *octeon_allocate_device(u32 pci_id,
721f21fb3edSRaghu Vatsavayi u32 priv_size)
722f21fb3edSRaghu Vatsavayi {
723f21fb3edSRaghu Vatsavayi u32 oct_idx = 0;
724f21fb3edSRaghu Vatsavayi struct octeon_device *oct = NULL;
725f21fb3edSRaghu Vatsavayi
726e1e3ce62SRick Farrington spin_lock(&octeon_devices_lock);
727e1e3ce62SRick Farrington
728f21fb3edSRaghu Vatsavayi for (oct_idx = 0; oct_idx < MAX_OCTEON_DEVICES; oct_idx++)
729f21fb3edSRaghu Vatsavayi if (!octeon_device[oct_idx])
730f21fb3edSRaghu Vatsavayi break;
731f21fb3edSRaghu Vatsavayi
732e1e3ce62SRick Farrington if (oct_idx < MAX_OCTEON_DEVICES) {
733f21fb3edSRaghu Vatsavayi oct = octeon_allocate_device_mem(pci_id, priv_size);
734e1e3ce62SRick Farrington if (oct) {
735e1e3ce62SRick Farrington octeon_device_count++;
736e1e3ce62SRick Farrington octeon_device[oct_idx] = oct;
737e1e3ce62SRick Farrington }
738e1e3ce62SRick Farrington }
739e1e3ce62SRick Farrington
740e1e3ce62SRick Farrington spin_unlock(&octeon_devices_lock);
741f21fb3edSRaghu Vatsavayi if (!oct)
742f21fb3edSRaghu Vatsavayi return NULL;
743f21fb3edSRaghu Vatsavayi
744f21fb3edSRaghu Vatsavayi spin_lock_init(&oct->pci_win_lock);
745f21fb3edSRaghu Vatsavayi spin_lock_init(&oct->mem_access_lock);
746f21fb3edSRaghu Vatsavayi
747f21fb3edSRaghu Vatsavayi oct->octeon_id = oct_idx;
74863da8404SRaghu Vatsavayi snprintf(oct->device_name, sizeof(oct->device_name),
749f21fb3edSRaghu Vatsavayi "LiquidIO%d", (oct->octeon_id));
750f21fb3edSRaghu Vatsavayi
751f21fb3edSRaghu Vatsavayi return oct;
752f21fb3edSRaghu Vatsavayi }
753f71be9d0SMasahiro Yamada EXPORT_SYMBOL_GPL(octeon_allocate_device);
754f21fb3edSRaghu Vatsavayi
755e1e3ce62SRick Farrington /** Register a device's bus location at initialization time.
756e1e3ce62SRick Farrington * @param octeon_dev - pointer to the octeon device structure.
757e1e3ce62SRick Farrington * @param bus - PCIe bus #
758e1e3ce62SRick Farrington * @param dev - PCIe device #
759e1e3ce62SRick Farrington * @param func - PCIe function #
760e1e3ce62SRick Farrington * @param is_pf - TRUE for PF, FALSE for VF
761e1e3ce62SRick Farrington * @return reference count of device's adapter
762e1e3ce62SRick Farrington */
octeon_register_device(struct octeon_device * oct,int bus,int dev,int func,int is_pf)763e1e3ce62SRick Farrington int octeon_register_device(struct octeon_device *oct,
764e1e3ce62SRick Farrington int bus, int dev, int func, int is_pf)
765e1e3ce62SRick Farrington {
766e1e3ce62SRick Farrington int idx, refcount;
767e1e3ce62SRick Farrington
768e1e3ce62SRick Farrington oct->loc.bus = bus;
769e1e3ce62SRick Farrington oct->loc.dev = dev;
770e1e3ce62SRick Farrington oct->loc.func = func;
771e1e3ce62SRick Farrington
772e1e3ce62SRick Farrington oct->adapter_refcount = &adapter_refcounts[oct->octeon_id];
773e1e3ce62SRick Farrington atomic_set(oct->adapter_refcount, 0);
774e1e3ce62SRick Farrington
775088b8749SRick Farrington /* Like the reference count, the f/w state is shared 'per-adapter' */
776088b8749SRick Farrington oct->adapter_fw_state = &adapter_fw_states[oct->octeon_id];
777088b8749SRick Farrington atomic_set(oct->adapter_fw_state, FW_NEEDS_TO_BE_LOADED);
778088b8749SRick Farrington
779e1e3ce62SRick Farrington spin_lock(&octeon_devices_lock);
780e1e3ce62SRick Farrington for (idx = (int)oct->octeon_id - 1; idx >= 0; idx--) {
781e1e3ce62SRick Farrington if (!octeon_device[idx]) {
782e1e3ce62SRick Farrington dev_err(&oct->pci_dev->dev,
783e1e3ce62SRick Farrington "%s: Internal driver error, missing dev",
784e1e3ce62SRick Farrington __func__);
785e1e3ce62SRick Farrington spin_unlock(&octeon_devices_lock);
786e1e3ce62SRick Farrington atomic_inc(oct->adapter_refcount);
787e1e3ce62SRick Farrington return 1; /* here, refcount is guaranteed to be 1 */
788e1e3ce62SRick Farrington }
789088b8749SRick Farrington /* If another device is at same bus/dev, use its refcounter
790088b8749SRick Farrington * (and f/w state variable).
791088b8749SRick Farrington */
792e1e3ce62SRick Farrington if ((octeon_device[idx]->loc.bus == bus) &&
793e1e3ce62SRick Farrington (octeon_device[idx]->loc.dev == dev)) {
794e1e3ce62SRick Farrington oct->adapter_refcount =
795e1e3ce62SRick Farrington octeon_device[idx]->adapter_refcount;
796088b8749SRick Farrington oct->adapter_fw_state =
797088b8749SRick Farrington octeon_device[idx]->adapter_fw_state;
798e1e3ce62SRick Farrington break;
799e1e3ce62SRick Farrington }
800e1e3ce62SRick Farrington }
801e1e3ce62SRick Farrington spin_unlock(&octeon_devices_lock);
802e1e3ce62SRick Farrington
803e1e3ce62SRick Farrington atomic_inc(oct->adapter_refcount);
804e1e3ce62SRick Farrington refcount = atomic_read(oct->adapter_refcount);
805e1e3ce62SRick Farrington
806e1e3ce62SRick Farrington dev_dbg(&oct->pci_dev->dev, "%s: %02x:%02x:%d refcount %u", __func__,
807e1e3ce62SRick Farrington oct->loc.bus, oct->loc.dev, oct->loc.func, refcount);
808e1e3ce62SRick Farrington
809e1e3ce62SRick Farrington return refcount;
810e1e3ce62SRick Farrington }
811f71be9d0SMasahiro Yamada EXPORT_SYMBOL_GPL(octeon_register_device);
812e1e3ce62SRick Farrington
813e1e3ce62SRick Farrington /** Deregister a device at de-initialization time.
814e1e3ce62SRick Farrington * @param octeon_dev - pointer to the octeon device structure.
815e1e3ce62SRick Farrington * @return reference count of device's adapter
816e1e3ce62SRick Farrington */
octeon_deregister_device(struct octeon_device * oct)817e1e3ce62SRick Farrington int octeon_deregister_device(struct octeon_device *oct)
818e1e3ce62SRick Farrington {
819e1e3ce62SRick Farrington int refcount;
820e1e3ce62SRick Farrington
821e1e3ce62SRick Farrington atomic_dec(oct->adapter_refcount);
822e1e3ce62SRick Farrington refcount = atomic_read(oct->adapter_refcount);
823e1e3ce62SRick Farrington
824e1e3ce62SRick Farrington dev_dbg(&oct->pci_dev->dev, "%s: %04d:%02d:%d refcount %u", __func__,
825e1e3ce62SRick Farrington oct->loc.bus, oct->loc.dev, oct->loc.func, refcount);
826e1e3ce62SRick Farrington
827e1e3ce62SRick Farrington return refcount;
828e1e3ce62SRick Farrington }
829f71be9d0SMasahiro Yamada EXPORT_SYMBOL_GPL(octeon_deregister_device);
830e1e3ce62SRick Farrington
8315b07aee1SRaghu Vatsavayi int
octeon_allocate_ioq_vector(struct octeon_device * oct,u32 num_ioqs)832c33c9973SIntiyaz Basha octeon_allocate_ioq_vector(struct octeon_device *oct, u32 num_ioqs)
8335b07aee1SRaghu Vatsavayi {
8345b07aee1SRaghu Vatsavayi struct octeon_ioq_vector *ioq_vector;
8355b07aee1SRaghu Vatsavayi int cpu_num;
8365b07aee1SRaghu Vatsavayi int size;
837c33c9973SIntiyaz Basha int i;
838cf39faf5SRaghu Vatsavayi
8395b07aee1SRaghu Vatsavayi size = sizeof(struct octeon_ioq_vector) * num_ioqs;
8405b07aee1SRaghu Vatsavayi
84172bca208SHimanshu Jha oct->ioq_vector = vzalloc(size);
8425b07aee1SRaghu Vatsavayi if (!oct->ioq_vector)
843c33c9973SIntiyaz Basha return -1;
8445b07aee1SRaghu Vatsavayi for (i = 0; i < num_ioqs; i++) {
8455b07aee1SRaghu Vatsavayi ioq_vector = &oct->ioq_vector[i];
8465b07aee1SRaghu Vatsavayi ioq_vector->oct_dev = oct;
8475b07aee1SRaghu Vatsavayi ioq_vector->iq_index = i;
8485b07aee1SRaghu Vatsavayi ioq_vector->droq_index = i;
8495d65556bSRaghu Vatsavayi ioq_vector->mbox = oct->mbox[i];
8505b07aee1SRaghu Vatsavayi
8515b07aee1SRaghu Vatsavayi cpu_num = i % num_online_cpus();
8525b07aee1SRaghu Vatsavayi cpumask_set_cpu(cpu_num, &ioq_vector->affinity_mask);
8535b07aee1SRaghu Vatsavayi
8545b07aee1SRaghu Vatsavayi if (oct->chip_id == OCTEON_CN23XX_PF_VID)
8555b07aee1SRaghu Vatsavayi ioq_vector->ioq_num = i + oct->sriov_info.pf_srn;
8565b07aee1SRaghu Vatsavayi else
8575b07aee1SRaghu Vatsavayi ioq_vector->ioq_num = i;
8585b07aee1SRaghu Vatsavayi }
859c33c9973SIntiyaz Basha
8605b07aee1SRaghu Vatsavayi return 0;
8615b07aee1SRaghu Vatsavayi }
862f71be9d0SMasahiro Yamada EXPORT_SYMBOL_GPL(octeon_allocate_ioq_vector);
8635b07aee1SRaghu Vatsavayi
8645b07aee1SRaghu Vatsavayi void
octeon_free_ioq_vector(struct octeon_device * oct)8655b07aee1SRaghu Vatsavayi octeon_free_ioq_vector(struct octeon_device *oct)
8665b07aee1SRaghu Vatsavayi {
8675b07aee1SRaghu Vatsavayi vfree(oct->ioq_vector);
8685b07aee1SRaghu Vatsavayi }
869f71be9d0SMasahiro Yamada EXPORT_SYMBOL_GPL(octeon_free_ioq_vector);
8705b07aee1SRaghu Vatsavayi
87126236fa9SRaghu Vatsavayi /* this function is only for setting up the first queue */
octeon_setup_instr_queues(struct octeon_device * oct)872f21fb3edSRaghu Vatsavayi int octeon_setup_instr_queues(struct octeon_device *oct)
873f21fb3edSRaghu Vatsavayi {
874f21fb3edSRaghu Vatsavayi u32 num_descs = 0;
87526236fa9SRaghu Vatsavayi u32 iq_no = 0;
87626236fa9SRaghu Vatsavayi union oct_txpciq txpciq;
877b3ca9af0SVSR Burru int numa_node = dev_to_node(&oct->pci_dev->dev);
878f21fb3edSRaghu Vatsavayi
87926236fa9SRaghu Vatsavayi if (OCTEON_CN6XXX(oct))
880f21fb3edSRaghu Vatsavayi num_descs =
88197a25326SRaghu Vatsavayi CFG_GET_NUM_DEF_TX_DESCS(CHIP_CONF(oct, cn6xxx));
882e86b1ab6SRaghu Vatsavayi else if (OCTEON_CN23XX_PF(oct))
88397a25326SRaghu Vatsavayi num_descs = CFG_GET_NUM_DEF_TX_DESCS(CHIP_CONF(oct, cn23xx_pf));
8849003baf0SRaghu Vatsavayi else if (OCTEON_CN23XX_VF(oct))
8859003baf0SRaghu Vatsavayi num_descs = CFG_GET_NUM_DEF_TX_DESCS(CHIP_CONF(oct, cn23xx_vf));
886f21fb3edSRaghu Vatsavayi
887f21fb3edSRaghu Vatsavayi oct->num_iqs = 0;
888f21fb3edSRaghu Vatsavayi
8892c4aac74SRick Farrington oct->instr_queue[0] = vzalloc_node(sizeof(*oct->instr_queue[0]),
89026236fa9SRaghu Vatsavayi numa_node);
89126236fa9SRaghu Vatsavayi if (!oct->instr_queue[0])
89226236fa9SRaghu Vatsavayi oct->instr_queue[0] =
8932c4aac74SRick Farrington vzalloc(sizeof(struct octeon_instr_queue));
89426236fa9SRaghu Vatsavayi if (!oct->instr_queue[0])
895f21fb3edSRaghu Vatsavayi return 1;
89626236fa9SRaghu Vatsavayi memset(oct->instr_queue[0], 0, sizeof(struct octeon_instr_queue));
8970cece6c5SRaghu Vatsavayi oct->instr_queue[0]->q_index = 0;
89826236fa9SRaghu Vatsavayi oct->instr_queue[0]->app_ctx = (void *)(size_t)0;
8990cece6c5SRaghu Vatsavayi oct->instr_queue[0]->ifidx = 0;
90026236fa9SRaghu Vatsavayi txpciq.u64 = 0;
90126236fa9SRaghu Vatsavayi txpciq.s.q_no = iq_no;
9025b823514SRaghu Vatsavayi txpciq.s.pkind = oct->pfvf_hsword.pkind;
90326236fa9SRaghu Vatsavayi txpciq.s.use_qpg = 0;
90426236fa9SRaghu Vatsavayi txpciq.s.qpg = 0;
90526236fa9SRaghu Vatsavayi if (octeon_init_instr_queue(oct, txpciq, num_descs)) {
90626236fa9SRaghu Vatsavayi /* prevent memory leak */
90726236fa9SRaghu Vatsavayi vfree(oct->instr_queue[0]);
908515e752dSRaghu Vatsavayi oct->instr_queue[0] = NULL;
909f21fb3edSRaghu Vatsavayi return 1;
910f21fb3edSRaghu Vatsavayi }
911f21fb3edSRaghu Vatsavayi
91226236fa9SRaghu Vatsavayi oct->num_iqs++;
913f21fb3edSRaghu Vatsavayi return 0;
914f21fb3edSRaghu Vatsavayi }
915f71be9d0SMasahiro Yamada EXPORT_SYMBOL_GPL(octeon_setup_instr_queues);
916f21fb3edSRaghu Vatsavayi
octeon_setup_output_queues(struct octeon_device * oct)917f21fb3edSRaghu Vatsavayi int octeon_setup_output_queues(struct octeon_device *oct)
918f21fb3edSRaghu Vatsavayi {
919f21fb3edSRaghu Vatsavayi u32 num_descs = 0;
920f21fb3edSRaghu Vatsavayi u32 desc_size = 0;
92196ae48b7SRaghu Vatsavayi u32 oq_no = 0;
922b3ca9af0SVSR Burru int numa_node = dev_to_node(&oct->pci_dev->dev);
923f21fb3edSRaghu Vatsavayi
924f21fb3edSRaghu Vatsavayi if (OCTEON_CN6XXX(oct)) {
925f21fb3edSRaghu Vatsavayi num_descs =
92697a25326SRaghu Vatsavayi CFG_GET_NUM_DEF_RX_DESCS(CHIP_CONF(oct, cn6xxx));
927f21fb3edSRaghu Vatsavayi desc_size =
92897a25326SRaghu Vatsavayi CFG_GET_DEF_RX_BUF_SIZE(CHIP_CONF(oct, cn6xxx));
929e86b1ab6SRaghu Vatsavayi } else if (OCTEON_CN23XX_PF(oct)) {
93097a25326SRaghu Vatsavayi num_descs = CFG_GET_NUM_DEF_RX_DESCS(CHIP_CONF(oct, cn23xx_pf));
93197a25326SRaghu Vatsavayi desc_size = CFG_GET_DEF_RX_BUF_SIZE(CHIP_CONF(oct, cn23xx_pf));
9329003baf0SRaghu Vatsavayi } else if (OCTEON_CN23XX_VF(oct)) {
9339003baf0SRaghu Vatsavayi num_descs = CFG_GET_NUM_DEF_RX_DESCS(CHIP_CONF(oct, cn23xx_vf));
9349003baf0SRaghu Vatsavayi desc_size = CFG_GET_DEF_RX_BUF_SIZE(CHIP_CONF(oct, cn23xx_vf));
935f21fb3edSRaghu Vatsavayi }
936f21fb3edSRaghu Vatsavayi oct->num_oqs = 0;
9372c4aac74SRick Farrington oct->droq[0] = vzalloc_node(sizeof(*oct->droq[0]), numa_node);
93896ae48b7SRaghu Vatsavayi if (!oct->droq[0])
9392c4aac74SRick Farrington oct->droq[0] = vzalloc(sizeof(*oct->droq[0]));
94096ae48b7SRaghu Vatsavayi if (!oct->droq[0])
941f21fb3edSRaghu Vatsavayi return 1;
942f21fb3edSRaghu Vatsavayi
943515e752dSRaghu Vatsavayi if (octeon_init_droq(oct, oq_no, num_descs, desc_size, NULL)) {
944515e752dSRaghu Vatsavayi vfree(oct->droq[oq_no]);
945515e752dSRaghu Vatsavayi oct->droq[oq_no] = NULL;
946f21fb3edSRaghu Vatsavayi return 1;
947515e752dSRaghu Vatsavayi }
948f21fb3edSRaghu Vatsavayi oct->num_oqs++;
949f21fb3edSRaghu Vatsavayi
950f21fb3edSRaghu Vatsavayi return 0;
951f21fb3edSRaghu Vatsavayi }
952f71be9d0SMasahiro Yamada EXPORT_SYMBOL_GPL(octeon_setup_output_queues);
953f21fb3edSRaghu Vatsavayi
octeon_set_io_queues_off(struct octeon_device * oct)954c865cdf1SRaghu Vatsavayi int octeon_set_io_queues_off(struct octeon_device *oct)
955f21fb3edSRaghu Vatsavayi {
956c865cdf1SRaghu Vatsavayi int loop = BUSY_READING_REG_VF_LOOP_COUNT;
957c865cdf1SRaghu Vatsavayi
9585b823514SRaghu Vatsavayi if (OCTEON_CN6XXX(oct)) {
959f21fb3edSRaghu Vatsavayi octeon_write_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB, 0);
960f21fb3edSRaghu Vatsavayi octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_ENB, 0);
961c865cdf1SRaghu Vatsavayi } else if (oct->chip_id == OCTEON_CN23XX_VF_VID) {
962c865cdf1SRaghu Vatsavayi u32 q_no;
963c865cdf1SRaghu Vatsavayi
964c865cdf1SRaghu Vatsavayi /* IOQs will already be in reset.
965c865cdf1SRaghu Vatsavayi * If RST bit is set, wait for quiet bit to be set.
966c865cdf1SRaghu Vatsavayi * Once quiet bit is set, clear the RST bit.
967c865cdf1SRaghu Vatsavayi */
968c865cdf1SRaghu Vatsavayi for (q_no = 0; q_no < oct->sriov_info.rings_per_vf; q_no++) {
969c865cdf1SRaghu Vatsavayi u64 reg_val = octeon_read_csr64(
970c865cdf1SRaghu Vatsavayi oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no));
971c865cdf1SRaghu Vatsavayi
972c865cdf1SRaghu Vatsavayi while ((reg_val & CN23XX_PKT_INPUT_CTL_RST) &&
973c865cdf1SRaghu Vatsavayi !(reg_val & CN23XX_PKT_INPUT_CTL_QUIET) &&
974c865cdf1SRaghu Vatsavayi loop) {
975c865cdf1SRaghu Vatsavayi reg_val = octeon_read_csr64(
976c865cdf1SRaghu Vatsavayi oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
977c865cdf1SRaghu Vatsavayi loop--;
978f21fb3edSRaghu Vatsavayi }
979c865cdf1SRaghu Vatsavayi if (!loop) {
980c865cdf1SRaghu Vatsavayi dev_err(&oct->pci_dev->dev,
981c865cdf1SRaghu Vatsavayi "clearing the reset reg failed or setting the quiet reg failed for qno: %u\n",
982c865cdf1SRaghu Vatsavayi q_no);
983c865cdf1SRaghu Vatsavayi return -1;
984c865cdf1SRaghu Vatsavayi }
985c865cdf1SRaghu Vatsavayi
986c865cdf1SRaghu Vatsavayi reg_val = reg_val & ~CN23XX_PKT_INPUT_CTL_RST;
987c865cdf1SRaghu Vatsavayi octeon_write_csr64(oct,
988c865cdf1SRaghu Vatsavayi CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
989c865cdf1SRaghu Vatsavayi reg_val);
990c865cdf1SRaghu Vatsavayi
991c865cdf1SRaghu Vatsavayi reg_val = octeon_read_csr64(
992c865cdf1SRaghu Vatsavayi oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
993c865cdf1SRaghu Vatsavayi if (reg_val & CN23XX_PKT_INPUT_CTL_RST) {
994c865cdf1SRaghu Vatsavayi dev_err(&oct->pci_dev->dev,
995c865cdf1SRaghu Vatsavayi "unable to reset qno %u\n", q_no);
996c865cdf1SRaghu Vatsavayi return -1;
997c865cdf1SRaghu Vatsavayi }
998c865cdf1SRaghu Vatsavayi }
999c865cdf1SRaghu Vatsavayi }
1000c865cdf1SRaghu Vatsavayi return 0;
10015b823514SRaghu Vatsavayi }
1002f71be9d0SMasahiro Yamada EXPORT_SYMBOL_GPL(octeon_set_io_queues_off);
1003f21fb3edSRaghu Vatsavayi
octeon_set_droq_pkt_op(struct octeon_device * oct,u32 q_no,u32 enable)1004f21fb3edSRaghu Vatsavayi void octeon_set_droq_pkt_op(struct octeon_device *oct,
1005f21fb3edSRaghu Vatsavayi u32 q_no,
1006f21fb3edSRaghu Vatsavayi u32 enable)
1007f21fb3edSRaghu Vatsavayi {
1008f21fb3edSRaghu Vatsavayi u32 reg_val = 0;
1009f21fb3edSRaghu Vatsavayi
1010f21fb3edSRaghu Vatsavayi /* Disable the i/p and o/p queues for this Octeon. */
10115b823514SRaghu Vatsavayi if (OCTEON_CN6XXX(oct)) {
1012f21fb3edSRaghu Vatsavayi reg_val = octeon_read_csr(oct, CN6XXX_SLI_PKT_OUT_ENB);
1013f21fb3edSRaghu Vatsavayi
1014f21fb3edSRaghu Vatsavayi if (enable)
1015f21fb3edSRaghu Vatsavayi reg_val = reg_val | (1 << q_no);
1016f21fb3edSRaghu Vatsavayi else
1017f21fb3edSRaghu Vatsavayi reg_val = reg_val & (~(1 << q_no));
1018f21fb3edSRaghu Vatsavayi
1019f21fb3edSRaghu Vatsavayi octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_ENB, reg_val);
1020f21fb3edSRaghu Vatsavayi }
10215b823514SRaghu Vatsavayi }
1022f21fb3edSRaghu Vatsavayi
octeon_init_dispatch_list(struct octeon_device * oct)1023f21fb3edSRaghu Vatsavayi int octeon_init_dispatch_list(struct octeon_device *oct)
1024f21fb3edSRaghu Vatsavayi {
1025f21fb3edSRaghu Vatsavayi u32 i;
1026f21fb3edSRaghu Vatsavayi
1027f21fb3edSRaghu Vatsavayi oct->dispatch.count = 0;
1028f21fb3edSRaghu Vatsavayi
1029f21fb3edSRaghu Vatsavayi for (i = 0; i < DISPATCH_LIST_SIZE; i++) {
1030f21fb3edSRaghu Vatsavayi oct->dispatch.dlist[i].opcode = 0;
1031f21fb3edSRaghu Vatsavayi INIT_LIST_HEAD(&oct->dispatch.dlist[i].list);
1032f21fb3edSRaghu Vatsavayi }
1033f21fb3edSRaghu Vatsavayi
1034f21fb3edSRaghu Vatsavayi for (i = 0; i <= REQTYPE_LAST; i++)
1035f21fb3edSRaghu Vatsavayi octeon_register_reqtype_free_fn(oct, i, NULL);
1036f21fb3edSRaghu Vatsavayi
1037f21fb3edSRaghu Vatsavayi spin_lock_init(&oct->dispatch.lock);
1038f21fb3edSRaghu Vatsavayi
1039f21fb3edSRaghu Vatsavayi return 0;
1040f21fb3edSRaghu Vatsavayi }
1041f71be9d0SMasahiro Yamada EXPORT_SYMBOL_GPL(octeon_init_dispatch_list);
1042f21fb3edSRaghu Vatsavayi
octeon_delete_dispatch_list(struct octeon_device * oct)1043f21fb3edSRaghu Vatsavayi void octeon_delete_dispatch_list(struct octeon_device *oct)
1044f21fb3edSRaghu Vatsavayi {
1045f21fb3edSRaghu Vatsavayi u32 i;
1046f21fb3edSRaghu Vatsavayi struct list_head freelist, *temp, *tmp2;
1047f21fb3edSRaghu Vatsavayi
1048f21fb3edSRaghu Vatsavayi INIT_LIST_HEAD(&freelist);
1049f21fb3edSRaghu Vatsavayi
1050f21fb3edSRaghu Vatsavayi spin_lock_bh(&oct->dispatch.lock);
1051f21fb3edSRaghu Vatsavayi
1052f21fb3edSRaghu Vatsavayi for (i = 0; i < DISPATCH_LIST_SIZE; i++) {
1053f21fb3edSRaghu Vatsavayi struct list_head *dispatch;
1054f21fb3edSRaghu Vatsavayi
1055f21fb3edSRaghu Vatsavayi dispatch = &oct->dispatch.dlist[i].list;
1056f21fb3edSRaghu Vatsavayi while (dispatch->next != dispatch) {
1057f21fb3edSRaghu Vatsavayi temp = dispatch->next;
1058880e1b21Szhong jiang list_move_tail(temp, &freelist);
1059f21fb3edSRaghu Vatsavayi }
1060f21fb3edSRaghu Vatsavayi
1061f21fb3edSRaghu Vatsavayi oct->dispatch.dlist[i].opcode = 0;
1062f21fb3edSRaghu Vatsavayi }
1063f21fb3edSRaghu Vatsavayi
1064f21fb3edSRaghu Vatsavayi oct->dispatch.count = 0;
1065f21fb3edSRaghu Vatsavayi
1066f21fb3edSRaghu Vatsavayi spin_unlock_bh(&oct->dispatch.lock);
1067f21fb3edSRaghu Vatsavayi
1068f21fb3edSRaghu Vatsavayi list_for_each_safe(temp, tmp2, &freelist) {
1069f21fb3edSRaghu Vatsavayi list_del(temp);
10701e51f935SWang Hai kfree(temp);
1071f21fb3edSRaghu Vatsavayi }
1072f21fb3edSRaghu Vatsavayi }
1073f71be9d0SMasahiro Yamada EXPORT_SYMBOL_GPL(octeon_delete_dispatch_list);
1074f21fb3edSRaghu Vatsavayi
1075f21fb3edSRaghu Vatsavayi octeon_dispatch_fn_t
octeon_get_dispatch(struct octeon_device * octeon_dev,u16 opcode,u16 subcode)1076f21fb3edSRaghu Vatsavayi octeon_get_dispatch(struct octeon_device *octeon_dev, u16 opcode,
1077f21fb3edSRaghu Vatsavayi u16 subcode)
1078f21fb3edSRaghu Vatsavayi {
1079f21fb3edSRaghu Vatsavayi u32 idx;
1080f21fb3edSRaghu Vatsavayi struct list_head *dispatch;
1081f21fb3edSRaghu Vatsavayi octeon_dispatch_fn_t fn = NULL;
1082f21fb3edSRaghu Vatsavayi u16 combined_opcode = OPCODE_SUBCODE(opcode, subcode);
1083f21fb3edSRaghu Vatsavayi
1084f21fb3edSRaghu Vatsavayi idx = combined_opcode & OCTEON_OPCODE_MASK;
1085f21fb3edSRaghu Vatsavayi
1086f21fb3edSRaghu Vatsavayi spin_lock_bh(&octeon_dev->dispatch.lock);
1087f21fb3edSRaghu Vatsavayi
1088f21fb3edSRaghu Vatsavayi if (octeon_dev->dispatch.count == 0) {
1089f21fb3edSRaghu Vatsavayi spin_unlock_bh(&octeon_dev->dispatch.lock);
1090f21fb3edSRaghu Vatsavayi return NULL;
1091f21fb3edSRaghu Vatsavayi }
1092f21fb3edSRaghu Vatsavayi
1093f21fb3edSRaghu Vatsavayi if (!(octeon_dev->dispatch.dlist[idx].opcode)) {
1094f21fb3edSRaghu Vatsavayi spin_unlock_bh(&octeon_dev->dispatch.lock);
1095f21fb3edSRaghu Vatsavayi return NULL;
1096f21fb3edSRaghu Vatsavayi }
1097f21fb3edSRaghu Vatsavayi
1098f21fb3edSRaghu Vatsavayi if (octeon_dev->dispatch.dlist[idx].opcode == combined_opcode) {
1099f21fb3edSRaghu Vatsavayi fn = octeon_dev->dispatch.dlist[idx].dispatch_fn;
1100f21fb3edSRaghu Vatsavayi } else {
1101f21fb3edSRaghu Vatsavayi list_for_each(dispatch,
1102f21fb3edSRaghu Vatsavayi &octeon_dev->dispatch.dlist[idx].list) {
1103f21fb3edSRaghu Vatsavayi if (((struct octeon_dispatch *)dispatch)->opcode ==
1104f21fb3edSRaghu Vatsavayi combined_opcode) {
1105f21fb3edSRaghu Vatsavayi fn = ((struct octeon_dispatch *)
1106f21fb3edSRaghu Vatsavayi dispatch)->dispatch_fn;
1107f21fb3edSRaghu Vatsavayi break;
1108f21fb3edSRaghu Vatsavayi }
1109f21fb3edSRaghu Vatsavayi }
1110f21fb3edSRaghu Vatsavayi }
1111f21fb3edSRaghu Vatsavayi
1112f21fb3edSRaghu Vatsavayi spin_unlock_bh(&octeon_dev->dispatch.lock);
1113f21fb3edSRaghu Vatsavayi return fn;
1114f21fb3edSRaghu Vatsavayi }
1115f21fb3edSRaghu Vatsavayi
1116f21fb3edSRaghu Vatsavayi /* octeon_register_dispatch_fn
1117f21fb3edSRaghu Vatsavayi * Parameters:
1118f21fb3edSRaghu Vatsavayi * octeon_id - id of the octeon device.
1119f21fb3edSRaghu Vatsavayi * opcode - opcode for which driver should call the registered function
1120f21fb3edSRaghu Vatsavayi * subcode - subcode for which driver should call the registered function
1121f21fb3edSRaghu Vatsavayi * fn - The function to call when a packet with "opcode" arrives in
1122f21fb3edSRaghu Vatsavayi * octeon output queues.
1123f21fb3edSRaghu Vatsavayi * fn_arg - The argument to be passed when calling function "fn".
1124f21fb3edSRaghu Vatsavayi * Description:
1125f21fb3edSRaghu Vatsavayi * Registers a function and its argument to be called when a packet
1126f21fb3edSRaghu Vatsavayi * arrives in Octeon output queues with "opcode".
1127f21fb3edSRaghu Vatsavayi * Returns:
1128f21fb3edSRaghu Vatsavayi * Success: 0
1129f21fb3edSRaghu Vatsavayi * Failure: 1
1130f21fb3edSRaghu Vatsavayi * Locks:
1131f21fb3edSRaghu Vatsavayi * No locks are held.
1132f21fb3edSRaghu Vatsavayi */
1133f21fb3edSRaghu Vatsavayi int
octeon_register_dispatch_fn(struct octeon_device * oct,u16 opcode,u16 subcode,octeon_dispatch_fn_t fn,void * fn_arg)1134f21fb3edSRaghu Vatsavayi octeon_register_dispatch_fn(struct octeon_device *oct,
1135f21fb3edSRaghu Vatsavayi u16 opcode,
1136f21fb3edSRaghu Vatsavayi u16 subcode,
1137f21fb3edSRaghu Vatsavayi octeon_dispatch_fn_t fn, void *fn_arg)
1138f21fb3edSRaghu Vatsavayi {
1139f21fb3edSRaghu Vatsavayi u32 idx;
1140f21fb3edSRaghu Vatsavayi octeon_dispatch_fn_t pfn;
1141f21fb3edSRaghu Vatsavayi u16 combined_opcode = OPCODE_SUBCODE(opcode, subcode);
1142f21fb3edSRaghu Vatsavayi
1143f21fb3edSRaghu Vatsavayi idx = combined_opcode & OCTEON_OPCODE_MASK;
1144f21fb3edSRaghu Vatsavayi
1145f21fb3edSRaghu Vatsavayi spin_lock_bh(&oct->dispatch.lock);
1146f21fb3edSRaghu Vatsavayi /* Add dispatch function to first level of lookup table */
1147f21fb3edSRaghu Vatsavayi if (oct->dispatch.dlist[idx].opcode == 0) {
1148f21fb3edSRaghu Vatsavayi oct->dispatch.dlist[idx].opcode = combined_opcode;
1149f21fb3edSRaghu Vatsavayi oct->dispatch.dlist[idx].dispatch_fn = fn;
1150f21fb3edSRaghu Vatsavayi oct->dispatch.dlist[idx].arg = fn_arg;
1151f21fb3edSRaghu Vatsavayi oct->dispatch.count++;
1152f21fb3edSRaghu Vatsavayi spin_unlock_bh(&oct->dispatch.lock);
1153f21fb3edSRaghu Vatsavayi return 0;
1154f21fb3edSRaghu Vatsavayi }
1155f21fb3edSRaghu Vatsavayi
1156f21fb3edSRaghu Vatsavayi spin_unlock_bh(&oct->dispatch.lock);
1157f21fb3edSRaghu Vatsavayi
1158f21fb3edSRaghu Vatsavayi /* Check if there was a function already registered for this
1159f21fb3edSRaghu Vatsavayi * opcode/subcode.
1160f21fb3edSRaghu Vatsavayi */
1161f21fb3edSRaghu Vatsavayi pfn = octeon_get_dispatch(oct, opcode, subcode);
1162f21fb3edSRaghu Vatsavayi if (!pfn) {
1163f21fb3edSRaghu Vatsavayi struct octeon_dispatch *dispatch;
1164f21fb3edSRaghu Vatsavayi
1165f21fb3edSRaghu Vatsavayi dev_dbg(&oct->pci_dev->dev,
1166f21fb3edSRaghu Vatsavayi "Adding opcode to dispatch list linked list\n");
11671e51f935SWang Hai dispatch = kmalloc(sizeof(*dispatch), GFP_KERNEL);
11681e51f935SWang Hai if (!dispatch)
1169f21fb3edSRaghu Vatsavayi return 1;
11701e51f935SWang Hai
1171f21fb3edSRaghu Vatsavayi dispatch->opcode = combined_opcode;
1172f21fb3edSRaghu Vatsavayi dispatch->dispatch_fn = fn;
1173f21fb3edSRaghu Vatsavayi dispatch->arg = fn_arg;
1174f21fb3edSRaghu Vatsavayi
1175f21fb3edSRaghu Vatsavayi /* Add dispatch function to linked list of fn ptrs
1176f21fb3edSRaghu Vatsavayi * at the hashed index.
1177f21fb3edSRaghu Vatsavayi */
1178f21fb3edSRaghu Vatsavayi spin_lock_bh(&oct->dispatch.lock);
1179f21fb3edSRaghu Vatsavayi list_add(&dispatch->list, &oct->dispatch.dlist[idx].list);
1180f21fb3edSRaghu Vatsavayi oct->dispatch.count++;
1181f21fb3edSRaghu Vatsavayi spin_unlock_bh(&oct->dispatch.lock);
1182f21fb3edSRaghu Vatsavayi
1183f21fb3edSRaghu Vatsavayi } else {
1184bf534588SVijaya Mohan Guvva if (pfn == fn &&
1185bf534588SVijaya Mohan Guvva octeon_get_dispatch_arg(oct, opcode, subcode) == fn_arg)
1186bf534588SVijaya Mohan Guvva return 0;
1187bf534588SVijaya Mohan Guvva
1188f21fb3edSRaghu Vatsavayi dev_err(&oct->pci_dev->dev,
1189f21fb3edSRaghu Vatsavayi "Found previously registered dispatch fn for opcode/subcode: %x/%x\n",
1190f21fb3edSRaghu Vatsavayi opcode, subcode);
1191f21fb3edSRaghu Vatsavayi return 1;
1192f21fb3edSRaghu Vatsavayi }
1193f21fb3edSRaghu Vatsavayi
1194f21fb3edSRaghu Vatsavayi return 0;
1195f21fb3edSRaghu Vatsavayi }
1196f71be9d0SMasahiro Yamada EXPORT_SYMBOL_GPL(octeon_register_dispatch_fn);
1197f21fb3edSRaghu Vatsavayi
octeon_core_drv_init(struct octeon_recv_info * recv_info,void * buf)1198f21fb3edSRaghu Vatsavayi int octeon_core_drv_init(struct octeon_recv_info *recv_info, void *buf)
1199f21fb3edSRaghu Vatsavayi {
1200f21fb3edSRaghu Vatsavayi u32 i;
1201f21fb3edSRaghu Vatsavayi char app_name[16];
1202f21fb3edSRaghu Vatsavayi struct octeon_device *oct = (struct octeon_device *)buf;
1203f21fb3edSRaghu Vatsavayi struct octeon_recv_pkt *recv_pkt = recv_info->recv_pkt;
1204f21fb3edSRaghu Vatsavayi struct octeon_core_setup *cs = NULL;
1205f21fb3edSRaghu Vatsavayi u32 num_nic_ports = 0;
1206f21fb3edSRaghu Vatsavayi
1207f21fb3edSRaghu Vatsavayi if (OCTEON_CN6XXX(oct))
1208f21fb3edSRaghu Vatsavayi num_nic_ports =
120997a25326SRaghu Vatsavayi CFG_GET_NUM_NIC_PORTS(CHIP_CONF(oct, cn6xxx));
1210e86b1ab6SRaghu Vatsavayi else if (OCTEON_CN23XX_PF(oct))
1211e86b1ab6SRaghu Vatsavayi num_nic_ports =
121297a25326SRaghu Vatsavayi CFG_GET_NUM_NIC_PORTS(CHIP_CONF(oct, cn23xx_pf));
1213f21fb3edSRaghu Vatsavayi
1214f21fb3edSRaghu Vatsavayi if (atomic_read(&oct->status) >= OCT_DEV_RUNNING) {
1215f21fb3edSRaghu Vatsavayi dev_err(&oct->pci_dev->dev, "Received CORE OK when device state is 0x%x\n",
1216f21fb3edSRaghu Vatsavayi atomic_read(&oct->status));
1217f21fb3edSRaghu Vatsavayi goto core_drv_init_err;
1218f21fb3edSRaghu Vatsavayi }
1219f21fb3edSRaghu Vatsavayi
1220*c0423539SJustin Stitt strscpy(app_name,
1221f21fb3edSRaghu Vatsavayi get_oct_app_string(
1222f21fb3edSRaghu Vatsavayi (u32)recv_pkt->rh.r_core_drv_init.app_mode),
1223*c0423539SJustin Stitt sizeof(app_name));
1224f21fb3edSRaghu Vatsavayi oct->app_mode = (u32)recv_pkt->rh.r_core_drv_init.app_mode;
12255b173cf9SRaghu Vatsavayi if (recv_pkt->rh.r_core_drv_init.app_mode == CVM_DRV_NIC_APP) {
1226f21fb3edSRaghu Vatsavayi oct->fw_info.max_nic_ports =
1227f21fb3edSRaghu Vatsavayi (u32)recv_pkt->rh.r_core_drv_init.max_nic_ports;
1228f21fb3edSRaghu Vatsavayi oct->fw_info.num_gmx_ports =
1229f21fb3edSRaghu Vatsavayi (u32)recv_pkt->rh.r_core_drv_init.num_gmx_ports;
12305b173cf9SRaghu Vatsavayi }
1231f21fb3edSRaghu Vatsavayi
1232f21fb3edSRaghu Vatsavayi if (oct->fw_info.max_nic_ports < num_nic_ports) {
1233f21fb3edSRaghu Vatsavayi dev_err(&oct->pci_dev->dev,
1234f21fb3edSRaghu Vatsavayi "Config has more ports than firmware allows (%d > %d).\n",
1235f21fb3edSRaghu Vatsavayi num_nic_ports, oct->fw_info.max_nic_ports);
1236f21fb3edSRaghu Vatsavayi goto core_drv_init_err;
1237f21fb3edSRaghu Vatsavayi }
1238f21fb3edSRaghu Vatsavayi oct->fw_info.app_cap_flags = recv_pkt->rh.r_core_drv_init.app_cap_flags;
1239f21fb3edSRaghu Vatsavayi oct->fw_info.app_mode = (u32)recv_pkt->rh.r_core_drv_init.app_mode;
12405b823514SRaghu Vatsavayi oct->pfvf_hsword.app_mode = (u32)recv_pkt->rh.r_core_drv_init.app_mode;
12415b823514SRaghu Vatsavayi
12425b823514SRaghu Vatsavayi oct->pfvf_hsword.pkind = recv_pkt->rh.r_core_drv_init.pkind;
12435b823514SRaghu Vatsavayi
12445b823514SRaghu Vatsavayi for (i = 0; i < oct->num_iqs; i++)
12455b823514SRaghu Vatsavayi oct->instr_queue[i]->txpciq.s.pkind = oct->pfvf_hsword.pkind;
1246f21fb3edSRaghu Vatsavayi
1247f21fb3edSRaghu Vatsavayi atomic_set(&oct->status, OCT_DEV_CORE_OK);
1248f21fb3edSRaghu Vatsavayi
1249f21fb3edSRaghu Vatsavayi cs = &core_setup[oct->octeon_id];
1250f21fb3edSRaghu Vatsavayi
1251c4ee5d81SPrasad Kanneganti if (recv_pkt->buffer_size[0] != (sizeof(*cs) + OCT_DROQ_INFO_SIZE)) {
1252f21fb3edSRaghu Vatsavayi dev_dbg(&oct->pci_dev->dev, "Core setup bytes expected %u found %d\n",
1253f21fb3edSRaghu Vatsavayi (u32)sizeof(*cs),
1254f21fb3edSRaghu Vatsavayi recv_pkt->buffer_size[0]);
1255f21fb3edSRaghu Vatsavayi }
1256f21fb3edSRaghu Vatsavayi
1257c4ee5d81SPrasad Kanneganti memcpy(cs, get_rbd(
1258c4ee5d81SPrasad Kanneganti recv_pkt->buffer_ptr[0]) + OCT_DROQ_INFO_SIZE, sizeof(*cs));
1259c4ee5d81SPrasad Kanneganti
1260*c0423539SJustin Stitt strscpy(oct->boardinfo.name, cs->boardname,
1261*c0423539SJustin Stitt sizeof(oct->boardinfo.name));
1262*c0423539SJustin Stitt strscpy(oct->boardinfo.serial_number, cs->board_serial_number,
1263*c0423539SJustin Stitt sizeof(oct->boardinfo.serial_number));
1264f21fb3edSRaghu Vatsavayi
1265f21fb3edSRaghu Vatsavayi octeon_swap_8B_data((u64 *)cs, (sizeof(*cs) >> 3));
1266f21fb3edSRaghu Vatsavayi
1267f21fb3edSRaghu Vatsavayi oct->boardinfo.major = cs->board_rev_major;
1268f21fb3edSRaghu Vatsavayi oct->boardinfo.minor = cs->board_rev_minor;
1269f21fb3edSRaghu Vatsavayi
1270f21fb3edSRaghu Vatsavayi dev_info(&oct->pci_dev->dev,
1271f21fb3edSRaghu Vatsavayi "Running %s (%llu Hz)\n",
1272f21fb3edSRaghu Vatsavayi app_name, CVM_CAST64(cs->corefreq));
1273f21fb3edSRaghu Vatsavayi
1274f21fb3edSRaghu Vatsavayi core_drv_init_err:
1275f21fb3edSRaghu Vatsavayi for (i = 0; i < recv_pkt->buffer_count; i++)
1276f21fb3edSRaghu Vatsavayi recv_buffer_free(recv_pkt->buffer_ptr[i]);
1277f21fb3edSRaghu Vatsavayi octeon_free_recv_info(recv_info);
1278f21fb3edSRaghu Vatsavayi return 0;
1279f21fb3edSRaghu Vatsavayi }
1280f71be9d0SMasahiro Yamada EXPORT_SYMBOL_GPL(octeon_core_drv_init);
1281f21fb3edSRaghu Vatsavayi
octeon_get_tx_qsize(struct octeon_device * oct,u32 q_no)1282f21fb3edSRaghu Vatsavayi int octeon_get_tx_qsize(struct octeon_device *oct, u32 q_no)
1283f21fb3edSRaghu Vatsavayi
1284f21fb3edSRaghu Vatsavayi {
128563da8404SRaghu Vatsavayi if (oct && (q_no < MAX_OCTEON_INSTR_QUEUES(oct)) &&
1286763185a3SRaghu Vatsavayi (oct->io_qmask.iq & BIT_ULL(q_no)))
1287f21fb3edSRaghu Vatsavayi return oct->instr_queue[q_no]->max_count;
1288f21fb3edSRaghu Vatsavayi
1289f21fb3edSRaghu Vatsavayi return -1;
1290f21fb3edSRaghu Vatsavayi }
1291f71be9d0SMasahiro Yamada EXPORT_SYMBOL_GPL(octeon_get_tx_qsize);
1292f21fb3edSRaghu Vatsavayi
octeon_get_rx_qsize(struct octeon_device * oct,u32 q_no)1293f21fb3edSRaghu Vatsavayi int octeon_get_rx_qsize(struct octeon_device *oct, u32 q_no)
1294f21fb3edSRaghu Vatsavayi {
129563da8404SRaghu Vatsavayi if (oct && (q_no < MAX_OCTEON_OUTPUT_QUEUES(oct)) &&
1296763185a3SRaghu Vatsavayi (oct->io_qmask.oq & BIT_ULL(q_no)))
1297f21fb3edSRaghu Vatsavayi return oct->droq[q_no]->max_count;
1298f21fb3edSRaghu Vatsavayi return -1;
1299f21fb3edSRaghu Vatsavayi }
1300f71be9d0SMasahiro Yamada EXPORT_SYMBOL_GPL(octeon_get_rx_qsize);
1301f21fb3edSRaghu Vatsavayi
1302f21fb3edSRaghu Vatsavayi /* Retruns the host firmware handshake OCTEON specific configuration */
octeon_get_conf(struct octeon_device * oct)1303f21fb3edSRaghu Vatsavayi struct octeon_config *octeon_get_conf(struct octeon_device *oct)
1304f21fb3edSRaghu Vatsavayi {
1305f21fb3edSRaghu Vatsavayi struct octeon_config *default_oct_conf = NULL;
1306f21fb3edSRaghu Vatsavayi
1307f21fb3edSRaghu Vatsavayi /* check the OCTEON Device model & return the corresponding octeon
1308f21fb3edSRaghu Vatsavayi * configuration
1309f21fb3edSRaghu Vatsavayi */
1310f21fb3edSRaghu Vatsavayi
1311f21fb3edSRaghu Vatsavayi if (OCTEON_CN6XXX(oct)) {
1312f21fb3edSRaghu Vatsavayi default_oct_conf =
131397a25326SRaghu Vatsavayi (struct octeon_config *)(CHIP_CONF(oct, cn6xxx));
1314e86b1ab6SRaghu Vatsavayi } else if (OCTEON_CN23XX_PF(oct)) {
1315e86b1ab6SRaghu Vatsavayi default_oct_conf = (struct octeon_config *)
131697a25326SRaghu Vatsavayi (CHIP_CONF(oct, cn23xx_pf));
1317846b4687SRaghu Vatsavayi } else if (OCTEON_CN23XX_VF(oct)) {
1318846b4687SRaghu Vatsavayi default_oct_conf = (struct octeon_config *)
1319846b4687SRaghu Vatsavayi (CHIP_CONF(oct, cn23xx_vf));
1320f21fb3edSRaghu Vatsavayi }
1321f21fb3edSRaghu Vatsavayi return default_oct_conf;
1322f21fb3edSRaghu Vatsavayi }
1323f71be9d0SMasahiro Yamada EXPORT_SYMBOL_GPL(octeon_get_conf);
1324f21fb3edSRaghu Vatsavayi
1325f21fb3edSRaghu Vatsavayi /* scratch register address is same in all the OCT-II and CN70XX models */
1326f21fb3edSRaghu Vatsavayi #define CNXX_SLI_SCRATCH1 0x3C0
1327f21fb3edSRaghu Vatsavayi
1328d0ea5cbdSJesse Brandeburg /* Get the octeon device pointer.
1329f21fb3edSRaghu Vatsavayi * @param octeon_id - The id for which the octeon device pointer is required.
1330f21fb3edSRaghu Vatsavayi * @return Success: Octeon device pointer.
1331f21fb3edSRaghu Vatsavayi * @return Failure: NULL.
1332f21fb3edSRaghu Vatsavayi */
lio_get_device(u32 octeon_id)1333f21fb3edSRaghu Vatsavayi struct octeon_device *lio_get_device(u32 octeon_id)
1334f21fb3edSRaghu Vatsavayi {
1335f21fb3edSRaghu Vatsavayi if (octeon_id >= MAX_OCTEON_DEVICES)
1336f21fb3edSRaghu Vatsavayi return NULL;
1337f21fb3edSRaghu Vatsavayi else
1338f21fb3edSRaghu Vatsavayi return octeon_device[octeon_id];
1339f21fb3edSRaghu Vatsavayi }
1340f71be9d0SMasahiro Yamada EXPORT_SYMBOL_GPL(lio_get_device);
1341f21fb3edSRaghu Vatsavayi
lio_pci_readq(struct octeon_device * oct,u64 addr)1342f21fb3edSRaghu Vatsavayi u64 lio_pci_readq(struct octeon_device *oct, u64 addr)
1343f21fb3edSRaghu Vatsavayi {
1344f21fb3edSRaghu Vatsavayi u64 val64;
1345f21fb3edSRaghu Vatsavayi unsigned long flags;
134647dae52bSZheng Yongjun u32 addrhi;
1347f21fb3edSRaghu Vatsavayi
1348f21fb3edSRaghu Vatsavayi spin_lock_irqsave(&oct->pci_win_lock, flags);
1349f21fb3edSRaghu Vatsavayi
1350f21fb3edSRaghu Vatsavayi /* The windowed read happens when the LSB of the addr is written.
1351f21fb3edSRaghu Vatsavayi * So write MSB first
1352f21fb3edSRaghu Vatsavayi */
1353f21fb3edSRaghu Vatsavayi addrhi = (addr >> 32);
1354e86b1ab6SRaghu Vatsavayi if ((oct->chip_id == OCTEON_CN66XX) ||
1355e86b1ab6SRaghu Vatsavayi (oct->chip_id == OCTEON_CN68XX) ||
1356e86b1ab6SRaghu Vatsavayi (oct->chip_id == OCTEON_CN23XX_PF_VID))
1357f21fb3edSRaghu Vatsavayi addrhi |= 0x00060000;
1358f21fb3edSRaghu Vatsavayi writel(addrhi, oct->reg_list.pci_win_rd_addr_hi);
1359f21fb3edSRaghu Vatsavayi
1360f21fb3edSRaghu Vatsavayi /* Read back to preserve ordering of writes */
136147dae52bSZheng Yongjun readl(oct->reg_list.pci_win_rd_addr_hi);
1362f21fb3edSRaghu Vatsavayi
1363f21fb3edSRaghu Vatsavayi writel(addr & 0xffffffff, oct->reg_list.pci_win_rd_addr_lo);
136447dae52bSZheng Yongjun readl(oct->reg_list.pci_win_rd_addr_lo);
1365f21fb3edSRaghu Vatsavayi
1366f21fb3edSRaghu Vatsavayi val64 = readq(oct->reg_list.pci_win_rd_data);
1367f21fb3edSRaghu Vatsavayi
1368f21fb3edSRaghu Vatsavayi spin_unlock_irqrestore(&oct->pci_win_lock, flags);
1369f21fb3edSRaghu Vatsavayi
1370f21fb3edSRaghu Vatsavayi return val64;
1371f21fb3edSRaghu Vatsavayi }
1372f71be9d0SMasahiro Yamada EXPORT_SYMBOL_GPL(lio_pci_readq);
1373f21fb3edSRaghu Vatsavayi
lio_pci_writeq(struct octeon_device * oct,u64 val,u64 addr)1374f21fb3edSRaghu Vatsavayi void lio_pci_writeq(struct octeon_device *oct,
1375f21fb3edSRaghu Vatsavayi u64 val,
1376f21fb3edSRaghu Vatsavayi u64 addr)
1377f21fb3edSRaghu Vatsavayi {
1378f21fb3edSRaghu Vatsavayi unsigned long flags;
1379f21fb3edSRaghu Vatsavayi
1380f21fb3edSRaghu Vatsavayi spin_lock_irqsave(&oct->pci_win_lock, flags);
1381f21fb3edSRaghu Vatsavayi
1382f21fb3edSRaghu Vatsavayi writeq(addr, oct->reg_list.pci_win_wr_addr);
1383f21fb3edSRaghu Vatsavayi
1384f21fb3edSRaghu Vatsavayi /* The write happens when the LSB is written. So write MSB first. */
1385f21fb3edSRaghu Vatsavayi writel(val >> 32, oct->reg_list.pci_win_wr_data_hi);
1386f21fb3edSRaghu Vatsavayi /* Read the MSB to ensure ordering of writes. */
138747dae52bSZheng Yongjun readl(oct->reg_list.pci_win_wr_data_hi);
1388f21fb3edSRaghu Vatsavayi
1389f21fb3edSRaghu Vatsavayi writel(val & 0xffffffff, oct->reg_list.pci_win_wr_data_lo);
1390f21fb3edSRaghu Vatsavayi
1391f21fb3edSRaghu Vatsavayi spin_unlock_irqrestore(&oct->pci_win_lock, flags);
1392f21fb3edSRaghu Vatsavayi }
1393f71be9d0SMasahiro Yamada EXPORT_SYMBOL_GPL(lio_pci_writeq);
1394f21fb3edSRaghu Vatsavayi
octeon_mem_access_ok(struct octeon_device * oct)1395f21fb3edSRaghu Vatsavayi int octeon_mem_access_ok(struct octeon_device *oct)
1396f21fb3edSRaghu Vatsavayi {
1397f21fb3edSRaghu Vatsavayi u64 access_okay = 0;
139863da8404SRaghu Vatsavayi u64 lmc0_reset_ctl;
1399f21fb3edSRaghu Vatsavayi
1400f21fb3edSRaghu Vatsavayi /* Check to make sure a DDR interface is enabled */
1401e86b1ab6SRaghu Vatsavayi if (OCTEON_CN23XX_PF(oct)) {
1402e86b1ab6SRaghu Vatsavayi lmc0_reset_ctl = lio_pci_readq(oct, CN23XX_LMC0_RESET_CTL);
1403e86b1ab6SRaghu Vatsavayi access_okay =
1404e86b1ab6SRaghu Vatsavayi (lmc0_reset_ctl & CN23XX_LMC0_RESET_CTL_DDR3RST_MASK);
1405e86b1ab6SRaghu Vatsavayi } else {
140663da8404SRaghu Vatsavayi lmc0_reset_ctl = lio_pci_readq(oct, CN6XXX_LMC0_RESET_CTL);
1407e86b1ab6SRaghu Vatsavayi access_okay =
1408e86b1ab6SRaghu Vatsavayi (lmc0_reset_ctl & CN6XXX_LMC0_RESET_CTL_DDR3RST_MASK);
1409e86b1ab6SRaghu Vatsavayi }
1410f21fb3edSRaghu Vatsavayi
1411f21fb3edSRaghu Vatsavayi return access_okay ? 0 : 1;
1412f21fb3edSRaghu Vatsavayi }
1413f71be9d0SMasahiro Yamada EXPORT_SYMBOL_GPL(octeon_mem_access_ok);
1414f21fb3edSRaghu Vatsavayi
octeon_wait_for_ddr_init(struct octeon_device * oct,u32 * timeout)1415f21fb3edSRaghu Vatsavayi int octeon_wait_for_ddr_init(struct octeon_device *oct, u32 *timeout)
1416f21fb3edSRaghu Vatsavayi {
1417f21fb3edSRaghu Vatsavayi int ret = 1;
1418f21fb3edSRaghu Vatsavayi u32 ms;
1419f21fb3edSRaghu Vatsavayi
1420f21fb3edSRaghu Vatsavayi if (!timeout)
1421f21fb3edSRaghu Vatsavayi return ret;
1422f21fb3edSRaghu Vatsavayi
1423f21fb3edSRaghu Vatsavayi for (ms = 0; (ret != 0) && ((*timeout == 0) || (ms <= *timeout));
1424f21fb3edSRaghu Vatsavayi ms += HZ / 10) {
1425f21fb3edSRaghu Vatsavayi ret = octeon_mem_access_ok(oct);
1426f21fb3edSRaghu Vatsavayi
1427f21fb3edSRaghu Vatsavayi /* wait 100 ms */
1428f21fb3edSRaghu Vatsavayi if (ret)
1429f21fb3edSRaghu Vatsavayi schedule_timeout_uninterruptible(HZ / 10);
1430f21fb3edSRaghu Vatsavayi }
1431f21fb3edSRaghu Vatsavayi
1432f21fb3edSRaghu Vatsavayi return ret;
1433f21fb3edSRaghu Vatsavayi }
1434f71be9d0SMasahiro Yamada EXPORT_SYMBOL_GPL(octeon_wait_for_ddr_init);
1435f21fb3edSRaghu Vatsavayi
1436d0ea5cbdSJesse Brandeburg /* Get the octeon id assigned to the octeon device passed as argument.
1437f21fb3edSRaghu Vatsavayi * This function is exported to other modules.
1438f21fb3edSRaghu Vatsavayi * @param dev - octeon device pointer passed as a void *.
1439f21fb3edSRaghu Vatsavayi * @return octeon device id
1440f21fb3edSRaghu Vatsavayi */
lio_get_device_id(void * dev)1441f21fb3edSRaghu Vatsavayi int lio_get_device_id(void *dev)
1442f21fb3edSRaghu Vatsavayi {
1443f21fb3edSRaghu Vatsavayi struct octeon_device *octeon_dev = (struct octeon_device *)dev;
1444f21fb3edSRaghu Vatsavayi u32 i;
1445f21fb3edSRaghu Vatsavayi
1446f21fb3edSRaghu Vatsavayi for (i = 0; i < MAX_OCTEON_DEVICES; i++)
1447f21fb3edSRaghu Vatsavayi if (octeon_device[i] == octeon_dev)
1448f21fb3edSRaghu Vatsavayi return octeon_dev->octeon_id;
1449f21fb3edSRaghu Vatsavayi return -1;
1450f21fb3edSRaghu Vatsavayi }
1451cd8b1eb4SRaghu Vatsavayi
lio_enable_irq(struct octeon_droq * droq,struct octeon_instr_queue * iq)1452cd8b1eb4SRaghu Vatsavayi void lio_enable_irq(struct octeon_droq *droq, struct octeon_instr_queue *iq)
1453cd8b1eb4SRaghu Vatsavayi {
14549ded1a51SRaghu Vatsavayi u64 instr_cnt;
1455a55667e6SPrasad Kanneganti u32 pkts_pend;
14569ded1a51SRaghu Vatsavayi struct octeon_device *oct = NULL;
14579ded1a51SRaghu Vatsavayi
1458cd8b1eb4SRaghu Vatsavayi /* the whole thing needs to be atomic, ideally */
1459cd8b1eb4SRaghu Vatsavayi if (droq) {
1460a55667e6SPrasad Kanneganti pkts_pend = (u32)atomic_read(&droq->pkts_pending);
1461a55667e6SPrasad Kanneganti writel(droq->pkt_count - pkts_pend, droq->pkts_sent_reg);
1462a55667e6SPrasad Kanneganti droq->pkt_count = pkts_pend;
14639ded1a51SRaghu Vatsavayi oct = droq->oct_dev;
1464cd8b1eb4SRaghu Vatsavayi }
1465cd8b1eb4SRaghu Vatsavayi if (iq) {
1466cd8b1eb4SRaghu Vatsavayi spin_lock_bh(&iq->lock);
1467b943f17eSRick Farrington writel(iq->pkts_processed, iq->inst_cnt_reg);
1468b943f17eSRick Farrington iq->pkt_in_done -= iq->pkts_processed;
1469b943f17eSRick Farrington iq->pkts_processed = 0;
1470cdb478e5SSatanand Burla /* this write needs to be flushed before we release the lock */
1471cd8b1eb4SRaghu Vatsavayi spin_unlock_bh(&iq->lock);
14729ded1a51SRaghu Vatsavayi oct = iq->oct_dev;
14739ded1a51SRaghu Vatsavayi }
14749ded1a51SRaghu Vatsavayi /*write resend. Writing RESEND in SLI_PKTX_CNTS should be enough
14759ded1a51SRaghu Vatsavayi *to trigger tx interrupts as well, if they are pending.
14769ded1a51SRaghu Vatsavayi */
14779217c3cfSRaghu Vatsavayi if (oct && (OCTEON_CN23XX_PF(oct) || OCTEON_CN23XX_VF(oct))) {
14789ded1a51SRaghu Vatsavayi if (droq)
14799ded1a51SRaghu Vatsavayi writeq(CN23XX_INTR_RESEND, droq->pkts_sent_reg);
14809ded1a51SRaghu Vatsavayi /*we race with firmrware here. read and write the IN_DONE_CNTS*/
14819ded1a51SRaghu Vatsavayi else if (iq) {
14829ded1a51SRaghu Vatsavayi instr_cnt = readq(iq->inst_cnt_reg);
14839ded1a51SRaghu Vatsavayi writeq(((instr_cnt & 0xFFFFFFFF00000000ULL) |
14849ded1a51SRaghu Vatsavayi CN23XX_INTR_RESEND),
14859ded1a51SRaghu Vatsavayi iq->inst_cnt_reg);
14869ded1a51SRaghu Vatsavayi }
1487cd8b1eb4SRaghu Vatsavayi }
1488cd8b1eb4SRaghu Vatsavayi }
1489f71be9d0SMasahiro Yamada EXPORT_SYMBOL_GPL(lio_enable_irq);
1490