| /freebsd/usr.sbin/rrenumd/ |
| H A D | lexer.l | 3 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
67 digit [0-9]
68 letter [0-9A-Za-z]
69 hexdigit [0-9A-Fa-f]
72 hyphen \-
98 mprefix match_prefix|match-prefix
99 uprefix use_prefix|use-prefix
116 yylval.num = RPM_PCO_ADD;
120 yylval.num = RPM_PCO_CHANGE;
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| /freebsd/contrib/tcsh/ |
| H A D | ed.screen.c | 2 * ed.screen.c: Editor/termcap-curses interface
4 /*-
341 * A very useful table from justin@crim.ca (Justin Bur) :-)
343 * - first (and second:-) case fixed)
347 * -------------- ------- ------- ------------ ------------
350 * No Wrap no -- yes yes
363 xfree(t->str); in TCset()
364 t->str = NULL; in TCset()
369 t->str = xrealloc(t->str, size); in TCset()
370 memcpy(t->str, cap, size); in TCset()
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| /freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ |
| H A D | omap-gpmc.txt | 7 - compatible: Should be set to one of the following:
9 ti,omap2420-gpmc (omap2420)
10 ti,omap2430-gpmc (omap2430)
11 ti,omap3430-gpmc (omap3430 & omap3630)
12 ti,omap4430-gpmc (omap4430 & omap4460 & omap543x)
13 ti,am3352-gpmc (am335x devices)
15 - reg: A resource specifier for the register space
17 - ti,hwmods: Should be set to "ti,gpmc" until the DT transition is
19 - #address-cells: Must be set to 2 to allow memory address translation
20 - #size-cells: Must be set to 1 to allow CS address passing
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| H A D | ti,gpmc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controller
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| /freebsd/sys/contrib/device-tree/Bindings/spi/ |
| H A D | spi-fsl-dspi.txt | 4 - compatible : must be one of:
5 "fsl,vf610-dspi",
6 "fsl,ls1021a-v1.0-dspi",
7 "fsl,ls1012a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
8 "fsl,ls1028a-dspi",
9 "fsl,ls1043a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
10 "fsl,ls1046a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
11 "fsl,ls1088a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
12 "fsl,ls2080a-dspi" (optionally followed by "fsl,ls2085a-dspi"),
13 "fsl,ls2085a-dspi",
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| H A D | fsl,dspi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
15 - enum:
16 - fsl,vf610-dspi
17 - fsl,ls1021a-v1.0-dspi
18 - fsl,ls1012a-dspi
19 - fsl,ls1028a-dspi
20 - fsl,ls1043a-dspi
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| H A D | omap-spi.txt | 4 - compatible :
5 - "ti,am654-mcspi" for AM654.
6 - "ti,omap2-mcspi" for OMAP2 & OMAP3.
7 - "ti,omap4-mcspi" for OMAP4+.
8 - ti,spi-num-cs : Number of chipselect supported by the instance.
9 - ti,hwmods: Name of the hwmod associated to the McSPI
10 - ti,pindir-d0-out-d1-in: Select the D0 pin as output and D1 as
15 - dmas: List of DMA specifiers with the controller specific format
18 - dma-names: List of DMA request names. These strings correspond
28 #address-cells = <1>;
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| H A D | spi-cadence.txt | 2 -------------------------------------------
5 - compatible : Should be "cdns,spi-r1p6" or "xlnx,zynq-spi-r1p6".
6 - reg : Physical base address and size of SPI registers map.
7 - interrupts : Property with a value describing the interrupt
9 - clock-names : List of input clock names - "ref_clk", "pclk"
11 - clocks : Clock phandles (see clock bindings for details).
14 - num-cs : Number of chip selects used.
17 - is-decoded-cs : Flag to indicate whether decoder is used or not.
22 compatible = "xlnx,zynq-spi-r1p6";
23 clock-names = "ref_clk", "pclk";
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| H A D | spi-lantiq-ssc.txt | 4 - compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi",
5 "intel,lgm-spi"
6 - #address-cells: see spi-bus.txt
7 - #size-cells: see spi-bus.txt
8 - reg: address and length of the spi master registers
9 - interrupts:
10 For compatible "intel,lgm-ssc" - the common interrupt number for
18 - clocks: spi clock phandle
19 - num-cs: see spi-bus.txt, set to 8 if unset
20 - base-cs: the number of the first chip select, set to 1 if unset.
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| H A D | spi-bcm63xx.txt | 4 - compatible: must contain one of "brcm,bcm6348-spi", "brcm,bcm6358-spi".
5 - reg: Base address and size of the controllers memory area.
6 - interrupts: Interrupt for the SPI block.
7 - clocks: phandle of the SPI clock.
8 - clock-names: has to be "spi".
9 - #address-cells: <1>, as required by generic SPI binding.
10 - #size-cells: <0>, also as required by generic SPI binding.
13 - num-cs: some controllers have less than 8 cs signals. Defaults to 8
21 compatible = "brcm,bcm6368-spi", "brcm,bcm6358-spi";
27 clock-names = "spi";
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| H A D | spi-bcm63xx-hsspi.txt | 4 - compatible: must contain of "brcm,bcm6328-hsspi".
5 - reg: Base address and size of the controllers memory area.
6 - interrupts: Interrupt for the SPI block.
7 - clocks: phandles of the SPI clock and the PLL clock.
8 - clock-names: must be "hsspi", "pll".
9 - #address-cells: <1>, as required by generic SPI binding.
10 - #size-cells: <0>, also as required by generic SPI binding.
13 - num-cs: some controllers have less than 8 cs signals. Defaults to 8
21 compatible = "brcm,bcm6328-hsspi";
27 clock-names = "hsspi", "pll";
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| H A D | spi-cadence.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-cadence.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
13 - $ref: spi-controller.yaml#
18 - cdns,spi-r1p6
19 - xlnx,zynq-spi-r1p6
27 clock-names:
29 - const: ref_clk
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| H A D | spi-gpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI-GPIO
10 - Rob Herring <robh@kernel.org>
13 This represents a group of 3-n GPIO lines used for bit-banged SPI on
17 - $ref: /schemas/spi/spi-controller.yaml#
21 const: spi-gpio
23 sck-gpios:
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| H A D | spi-davinci.txt | 4 Keystone 2 - https://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf
5 dm644x - https://www.ti.com/lit/ug/sprue32a/sprue32a.pdf
6 OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
9 - #address-cells: number of cells required to define a chip select
11 - #size-cells: should be zero.
12 - compatible:
13 - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
14 - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
15 - "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC
17 - reg: Offset and length of SPI controller register space
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| H A D | microchip,mpfs-spi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Conor Dooley <conor.dooley@microchip.com>
19 - items:
20 - enum:
21 - microchip,mpfs-qspi
22 - microchip,pic64gx-qspi
23 - const: microchip,coreqspi-rtl-v2
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| H A D | spi-armada-3700.txt | 5 - compatible: should be "marvell,armada-3700-spi"
6 - reg: physical base address of the controller and length of memory mapped
8 - interrupts: The interrupt number. The interrupt specifier format depends on
10 - clocks: Must contain the clock source, usually from the North Bridge clocks.
11 - num-cs: The number of chip selects that is supported by this SPI Controller
12 - #address-cells: should be 1.
13 - #size-cells: should be 0.
18 compatible = "marvell,armada-3700-spi";
19 #address-cells = <1>;
20 #size-cells = <0>;
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| H A D | spi-fsl-lpspi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-fsl-lpspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
12 - Fabio Estevam <festevam@gmail.com>
15 - $ref: /schemas/spi/spi-controller.yaml#
20 - enum:
21 - fsl,imx7ulp-spi
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| H A D | samsung,spi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
19 - enum:
20 - google,gs101-spi
21 - samsung,s3c2443-spi # for S3C2443, S3C2416 and S3C2450
22 - samsung,s3c6410-spi
23 - samsung,s5pv210-spi # for S5PV210 and S5PC110
24 - samsung,exynos4210-spi
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| /freebsd/sys/contrib/xen/arch-x86/ |
| H A D | xen-x86_64.h | 2 * xen-x86_64.h
4 * Guest OS interface to x86 64-bit Xen.
24 * Copyright (c) 2004-2006, K A Fraser
32 * Input: %rdi, %rsi, %rdx, %r10, %r8, %r9 (arguments 1-6)
35 * call hypercall_page + hypercall-number * 32
36 * Clobbered: argument registers (e.g., 2-arg hypercall clobbers %rdi,%rsi)
40 * 64-bit segment selectors
41 * These flat segments are in the Xen-private section of every GDT. Since these
85 #define MACH2PHYS_NR_ENTRIES ((MACH2PHYS_VIRT_END-MACH2PHYS_VIRT_START)>>3)
92 * @which == SEGBASE_* ; @base == 64-bit base address
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| /freebsd/contrib/netbsd-tests/crypto/opencrypto/ |
| H A D | h_md5hmac.c | 3 /*-
43 int num; member
115 "Test Using Larger Than Block-Size Key - Hash Key First",
131 "Test Using Larger Than Block-Size Key and Larger "
132 "Than One Block-Size Data",
143 struct session_op cs; in main() local
154 memset(&cs, 0, sizeof(cs)); in main()
155 cs.mac = CRYPTO_MD5_HMAC; in main()
156 cs.mackeylen = tests[i].key_len; in main()
157 cs.mackey = __UNCONST(&tests[i].key); in main()
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| H A D | h_sha1hmac.c | 3 /*-
39 #define SHA1_HMAC_KEYLEN 20 /* Only key-length we support */
43 int num; member
123 "Test Using Larger Than Block-Size Key - Hash Key First",
140 "Test Using Larger Than Block-Size Key and Larger Than "
141 "One Block-Size Data",
153 struct session_op cs; in main() local
164 memset(&cs, 0, sizeof(cs)); in main()
165 cs.mac = CRYPTO_SHA1_HMAC; in main()
166 cs.mackeylen = tests[i].key_len; in main()
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| /freebsd/sys/contrib/device-tree/src/arm64/toshiba/ |
| H A D | tmpv7708.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * (C) Copyright 2018 - 2020, Toshiba Corporation.
10 #include <dt-bindings/clock/toshiba,tmpv770x.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 /memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
23 #size-cells = <0>;
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| /freebsd/sys/contrib/device-tree/Bindings/mtd/ |
| H A D | gpmc-nor.txt | 8 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
11 - bank-width: Width of NOR flash in bytes. GPMC supports 8-bit and
12 16-bit devices and so must be either 1 or 2 bytes.
13 - compatible: Documentation/devicetree/bindings/mtd/mtd-physmap.yaml
14 - gpmc,cs-on-ns: Chip-select assertion time
15 - gpmc,cs-rd-off-ns: Chip-select de-assertion time for reads
16 - gpmc,cs-wr-off-ns: Chip-select de-assertion time for writes
17 - gpmc,oe-on-ns: Output-enable assertion time
18 - gpmc,oe-off-ns: Output-enable de-assertion time
19 - gpmc,we-on-ns Write-enable assertion time
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | gpmc-eth.txt | 4 General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices
12 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
18 Child nodes need to specify the GPMC bus address width using the "bank-width"
20 specify the I/O registers address width. Even when the GPMC has a maximum 16-bit
21 address width, it supports devices with 32-bit word registers.
23 OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;".
26 - bank-width: Address width of the device in bytes. GPMC supports 8-bit
27 and 16-bit devices and so must be either 1 or 2 bytes.
28 - compatible: Compatible string property for the ethernet child device.
29 - gpmc,cs-on-ns: Chip-select assertion time
[all …]
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| /freebsd/sys/contrib/device-tree/src/riscv/canaan/ |
| H A D | canaan_kd233.dts | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
7 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
16 compatible = "canaan,kendryte-kd233", "canaan,kendryte-k210";
24 stdout-path = "serial0:115200n8";
27 gpio-leds {
28 compatible = "gpio-leds";
39 gpio-keys {
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