| /linux/drivers/net/ethernet/airoha/ |
| H A D | airoha_npu.c | 163 static int airoha_npu_send_msg(struct airoha_npu *npu, int func_id, in airoha_npu_send_msg() argument 171 dma_addr = dma_map_single(npu->dev, p, size, DMA_TO_DEVICE); in airoha_npu_send_msg() 172 ret = dma_mapping_error(npu->dev, dma_addr); in airoha_npu_send_msg() 176 spin_lock_bh(&npu->cores[core].lock); in airoha_npu_send_msg() 178 regmap_write(npu->regmap, REG_CR_MBQ0_CTRL(0) + offset, dma_addr); in airoha_npu_send_msg() 179 regmap_write(npu->regmap, REG_CR_MBQ0_CTRL(1) + offset, size); in airoha_npu_send_msg() 180 regmap_read(npu->regmap, REG_CR_MBQ0_CTRL(2) + offset, &val); in airoha_npu_send_msg() 181 regmap_write(npu->regmap, REG_CR_MBQ0_CTRL(2) + offset, val + 1); in airoha_npu_send_msg() 183 regmap_write(npu->regmap, REG_CR_MBQ0_CTRL(3) + offset, val); in airoha_npu_send_msg() 185 ret = regmap_read_poll_timeout_atomic(npu->regmap, in airoha_npu_send_msg() [all …]
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| H A D | airoha_ppe.c | 558 struct airoha_npu *npu, in airoha_ppe_foe_flow_stat_entry_reset() argument 561 memset_io(&npu->stats[index], 0, sizeof(*npu->stats)); in airoha_ppe_foe_flow_stat_entry_reset() 566 struct airoha_npu *npu) in airoha_ppe_foe_flow_stats_reset() argument 575 airoha_ppe_foe_flow_stat_entry_reset(ppe, npu, i); in airoha_ppe_foe_flow_stats_reset() 579 struct airoha_npu *npu, in airoha_ppe_foe_flow_stats_update() argument 616 airoha_ppe_foe_flow_stat_entry_reset(ppe, npu, index); in airoha_ppe_foe_flow_stats_update() 723 struct airoha_npu *npu; in airoha_ppe_foe_commit_entry() local 735 npu = rcu_dereference(eth->npu); in airoha_ppe_foe_commit_entry() 736 if (!npu) { in airoha_ppe_foe_commit_entry() 742 airoha_ppe_foe_flow_stats_update(ppe, npu, hwe, hash); in airoha_ppe_foe_commit_entry() [all …]
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| /linux/include/linux/soc/airoha/ |
| H A D | airoha_offload.h | 172 struct airoha_npu *npu; member 173 /* protect concurrent npu memory accesses */ 183 int (*ppe_init)(struct airoha_npu *npu); 184 int (*ppe_deinit)(struct airoha_npu *npu); 185 int (*ppe_init_stats)(struct airoha_npu *npu, 187 int (*ppe_flush_sram_entries)(struct airoha_npu *npu, 190 int (*ppe_foe_commit_entry)(struct airoha_npu *npu, 194 int (*wlan_init_reserved_memory)(struct airoha_npu *npu); 195 int (*wlan_send_msg)(struct airoha_npu *npu, int ifindex, 198 int (*wlan_get_msg)(struct airoha_npu *npu, int ifindex, [all …]
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| /linux/drivers/accel/amdxdna/ |
| H A D | Kconfig | 14 Choose this option to enable support for NPU integrated into AMD 15 client CPUs like AMD Ryzen AI 300 Series. AMD NPU can be used to
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| H A D | amdxdna_pci_drv.c | 22 MODULE_FIRMWARE("amdnpu/1502_00/npu.sbin"); 23 MODULE_FIRMWARE("amdnpu/17f0_10/npu.sbin"); 24 MODULE_FIRMWARE("amdnpu/17f0_11/npu.sbin"); 25 MODULE_FIRMWARE("amdnpu/17f0_20/npu.sbin");
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| H A D | npu6_regs.c | 15 /* NPU Public Registers on MpNPUAxiXbar (refer to Diag npu_registers.h) */
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| H A D | npu5_regs.c | 15 /* NPU Public Registers on MpNPUAxiXbar (refer to Diag npu_registers.h) */
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| /linux/Documentation/accel/amdxdna/ |
| H A D | index.rst | 4 accel/amdxdna NPU driver 7 The accel/amdxdna driver supports the AMD NPU (Neural Processing Unit).
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| /linux/arch/arm64/boot/dts/airoha/ |
| H A D | en7581.dtsi | 18 npu-binary@84000000 { 23 npu-flag@84b0000 { 28 npu-pkt@85000000 { 33 npu-phyaddr@86b00000 { 38 npu-rxdesc@86d00000 {
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| /linux/drivers/accel/ivpu/ |
| H A D | ivpu_drv.c | 52 MODULE_PARM_DESC(pll_min_ratio, "Minimum PLL ratio used to set NPU frequency"); 56 MODULE_PARM_DESC(pll_max_ratio, "Maximum PLL ratio used to set NPU frequency"); 68 MODULE_PARM_DESC(force_snoop, "Force snooping for NPU host memory access"); 424 ivpu_err(vdev, "Invalid NPU ready message: 0x%x\n", ipc_hdr.data_addr); in ivpu_wait_for_ready() 429 ivpu_dbg(vdev, PM, "NPU ready message received successfully\n"); in ivpu_wait_for_ready() 520 /* Save PCI state before powering down as it sometimes gets corrupted if NPU hangs */ in ivpu_shutdown() 641 /* NPU does not require 10m D3hot delay */ in ivpu_pci_init()
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| H A D | ivpu_hw.c | 278 ivpu_err(vdev, "Failed to reset NPU IP\n"); in ivpu_hw_reset() 297 ivpu_warn(vdev, "NPU not idle during power down\n"); in ivpu_hw_power_down() 300 ivpu_err(vdev, "Failed to reset NPU\n"); in ivpu_hw_power_down()
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| H A D | ivpu_drv.h | 24 #define DRIVER_DESC "Driver for Intel NPU (Neural Processing Unit)" 267 ivpu_err(vdev, "Unknown NPU IP generation\n"); in ivpu_hw_ip_gen()
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| /linux/tools/perf/pmu-events/arch/arm64/freescale/imx8mp/sys/ |
| H A D | metrics.json | 259 "BriefDescription": "bytes of npu read from ddr", 260 "MetricName": "imx8mp_ddr_read.npu", 267 "BriefDescription": "bytes of npu write to ddr", 268 "MetricName": "imx8mp_ddr_write.npu",
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| /linux/drivers/accel/rocket/ |
| H A D | rocket_job.c | 36 return "rockchip-npu"; in rocket_fence_get_timeline_name() 300 * we were resetting the NPU. in rocket_job_run() 375 /* NPU has been reset, we can clear the reset pending bit. */ in rocket_reset() 388 dev_err(core->dev, "NPU job timed out"); in rocket_job_timedout()
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| /linux/drivers/accel/ethosu/ |
| H A D | Kconfig | 4 tristate "Arm Ethos-U65/U85 NPU"
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| H A D | ethosu_job.c | 37 return "ethosu-npu"; in ethosu_fence_get_timeline_name() 269 dev_err(dev->base.dev, "NPU sched timed out: NPU %s, cmdstream offset 0x%x: 0x%x\n", in ethosu_job_timedout()
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| /linux/drivers/pmdomain/sunxi/ |
| H A D | sun20i-ppu.c | 187 "NPU", 198 "NPU",
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| /linux/drivers/pmdomain/thead/ |
| H A D | Kconfig | 11 which can be managed independently. For example GPU, NPU,
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| /linux/drivers/misc/ocxl/ |
| H A D | link.c | 66 * time. The NPU won't raise another interrupt until the 650 * before we clear the NPU context cache below, so that the in ocxl_link_update_pe() 658 * cache of the NPU. in ocxl_link_update_pe() 712 * before we clear the NPU context cache below, so that the in ocxl_link_remove_pe() 720 * cache of the NPU. in ocxl_link_remove_pe()
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| /linux/arch/powerpc/platforms/powernv/ |
| H A D | ocxl.c | 10 /* PASIDs are 20-bit, but on P9, NPU can only handle 15 bits */ 43 * for a (BDF, pasid) combination. When it receives a command, the NPU 286 * on the device. The NPU needs to be configured to know how in pnv_ocxl_get_pasid_count() 329 * The TL capabilities are a characteristic of the NPU, so in pnv_ocxl_get_tl_cap()
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| H A D | opal-hmi.c | 150 printk("%s NPU checkstop on chip %x\n", level, in print_npu_checkstop_reason() 170 printk("%s NPU checkstop on chip %x: FIR%d bit %d is set\n", in print_npu_checkstop_reason()
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| /linux/arch/arm64/boot/dts/amlogic/ |
| H A D | meson-g12b-a311d-bananapi-m2s.dts | 35 &npu {
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| H A D | meson-g12b-a311d-khadas-vim3.dts | 43 &npu {
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| /linux/Documentation/devicetree/bindings/interconnect/ |
| H A D | qcom,sm6350-rpmh.yaml | 24 - qcom,sm6350-npu-noc
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| /linux/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3588-orangepi-5.dtsi | 382 npu-supply = <&vdd_npu_s0>; 388 npu-supply = <&vdd_npu_s0>; 394 npu-supply = <&vdd_npu_s0>;
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