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Searched +full:npcm750 +full:- +full:gcr (Results 1 – 15 of 15) sorted by relevance

/linux/arch/arm64/boot/dts/nuvoton/
H A Dnuvoton-common-npcm8xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/clock/nuvoton,npcm845-clk.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
16 compatible = "simple-bus";
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/linux/Documentation/devicetree/bindings/soc/nuvoton/
H A Dnuvoton,npcm-gcr.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/soc/nuvoton/nuvoton,npcm-gcr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jonathan Neuschäfer <j.neuschaefer@gmx.net>
11 - Tomer Maimon <tmaimon77@gmail.com>
14 The Global Control Registers (GCR) are a block of registers in Nuvoton SoCs
21 - enum:
22 - nuvoton,wpcm450-gcr
23 - nuvoton,npcm750-gcr
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/linux/Documentation/devicetree/bindings/reset/
H A Dnuvoton,npcm750-reset.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/nuvoton,npcm750-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tomer Maimon <tmaimon77@gmail.com>
15 - nuvoton,npcm750-reset # Poleg NPCM7XX SoC
16 - nuvoton,npcm845-reset # Arbel NPCM8XX SoC
21 '#reset-cells':
24 '#clock-cells':
29 - description: specify external 25MHz reference clock.
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/linux/arch/arm/mach-npcm/
H A Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0
5 #define pr_fmt(fmt) "nuvoton,npcm7xx-smp: " fmt
28 gcr_np = of_find_compatible_node(NULL, NULL, "nuvoton,npcm750-gcr"); in npcm7xx_smp_boot_secondary()
30 pr_err("no gcr device node\n"); in npcm7xx_smp_boot_secondary()
31 ret = -ENODEV; in npcm7xx_smp_boot_secondary()
36 pr_err("could not iomap gcr"); in npcm7xx_smp_boot_secondary()
37 ret = -ENOMEM; in npcm7xx_smp_boot_secondary()
57 scu_np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); in npcm7xx_smp_prepare_cpus()
78 CPU_METHOD_OF_DECLARE(npcm7xx_smp, "nuvoton,npcm750-smp", &npcm7xx_smp_ops);
/linux/Documentation/devicetree/bindings/media/
H A Dnuvoton,npcm-vcd.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nuvoton,npcm-vcd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Joseph Liu <kwliu@nuvoton.com>
11 - Marvin Lin <kflin@nuvoton.com>
19 - nuvoton,npcm750-vcd
20 - nuvoton,npcm845-vcd
33 description: phandle to access GCR (Global Control Register) registers.
43 memory-region:
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/linux/Documentation/devicetree/bindings/arm/cpu-enable-method/
H A Dnuvoton,npcm750-smp2 Secondary CPU enable-method "nuvoton,npcm750-smp" binding
5 To apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be
8 Enable method name: "nuvoton,npcm750-smp"
9 Compatible machines: "nuvoton,npcm750"
10 Compatible CPUs: "arm,cortex-a9"
14 This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
15 "nuvoton,npcm750-gcr".
20 #address-cells = <1>;
21 #size-cells = <0>;
22 enable-method = "nuvoton,npcm750-smp";
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/linux/arch/arm/boot/dts/nuvoton/
H A Dnuvoton-common-npcm7xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
7 #include <dt-bindings/reset/nuvoton,npcm7xx-reset.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
12 interrupt-parent = <&gic>;
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
18 clock-frequency = <25000000>;
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H A Dnuvoton-npcm750-runbmc-olympus.dts1 // SPDX-License-Identifier: GPL-2.0
5 /dts-v1/;
6 #include "nuvoton-npcm750.dtsi"
7 #include "nuvoton-npcm750-runbmc-olympus-pincfg.dtsi"
9 #include <dt-bindings/i2c/i2c.h>
10 #include <dt-bindings/gpio/gpio.h>
13 model = "Nuvoton npcm750 RunBMC Olympus";
14 compatible = "nuvoton,npcm750";
43 stdout-path = &serial3;
50 iio-hwmon {
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H A Dnuvoton-npcm730-kudo.dts1 // SPDX-License-Identifier: GPL-2.0
4 /dts-v1/;
5 #include "nuvoton-npcm730.dtsi"
7 #include <dt-bindings/gpio/gpio.h>
41 stdout-path = &serial3;
48 iio-hwmon {
49 compatible = "iio-hwmon";
50 io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
55 compatible = "nuvoton,npcm750-jtag-master";
56 #address-cells = <1>;
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H A Dnuvoton-npcm730-gbs.dts1 // SPDX-License-Identifier: GPL-2.0
4 /dts-v1/;
5 #include "nuvoton-npcm730.dtsi"
6 #include <dt-bindings/gpio/gpio.h>
10 compatible = "quanta,gbs-bmc","nuvoton,npcm730";
71 stdout-path = &serial0;
78 gpio-keys {
79 compatible = "gpio-keys";
80 sas-cable0 {
81 label = "sas-cable0";
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/linux/drivers/reset/
H A Dreset-npcm.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/reset-controller.h>
20 #include <soc/nuvoton/clock-npcm8xx.h>
22 /* NPCM7xx GCR registers */
109 writel(NPCM_SWRST << rc->sw_reset_number, rc->base + NPCM_SWRSTR); in npcm_rc_restart()
126 spin_lock_irqsave(&rc->lock, flags); in npcm_rc_setclear_reset()
127 stat = readl(rc->base + ctrl_offset); in npcm_rc_setclear_reset()
129 writel(stat | rst_bit, rc->base + ctrl_offset); in npcm_rc_setclear_reset()
131 writel(stat & ~rst_bit, rc->base + ctrl_offset); in npcm_rc_setclear_reset()
132 spin_unlock_irqrestore(&rc->lock, flags); in npcm_rc_setclear_reset()
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/linux/Documentation/devicetree/bindings/i2c/
H A Dnuvoton,npcm7xx-i2c.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/i2c/nuvoton,npcm7xx-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Tali Perry <tali.perry1@gmail.com>
20 - nuvoton,npcm750-i2c
21 - nuvoton,npcm845-i2c
33 clock-frequency:
40 nuvoton,sys-mgr:
45 - compatible
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/linux/drivers/peci/controller/
H A Dpeci-npcm.c1 // SPDX-License-Identifier: GPL-2.0
15 /* NPCM GCR module */
31 /* NPCM_PECI_CTL_STS - 0x00 : Control Register */
38 /* NPCM_PECI_RD_LENGTH - 0x04 : Command Register */
41 /* NPCM_PECI_CMD - 0x10 : Command Register */
44 /* NPCM_PECI_WR_LENGTH - 0x1C : Command Register */
47 /* NPCM_PECI_PDDR - 0x2C : Command Register */
75 struct npcm_peci *priv = dev_get_drvdata(controller->dev.parent); in npcm_peci_xfer()
76 unsigned long timeout = msecs_to_jiffies(priv->cmd_timeout_ms); in npcm_peci_xfer()
82 ret = regmap_read_poll_timeout(priv->regmap, NPCM_PECI_CTL_STS, cmd_sts, in npcm_peci_xfer()
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/linux/drivers/pinctrl/nuvoton/
H A Dpinctrl-npcm7xx.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2016-2018 Nuvoton Technology corporation.
21 #include <linux/pinctrl/pinconf-generic.h>
26 /* GCR registers */
51 #define NPCM7XX_GP_N_PU 0x1c /* Pull-up */
52 #define NPCM7XX_GP_N_PD 0x20 /* Pull-down */
110 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); in npcm_gpio_set()
115 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); in npcm_gpio_set()
124 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); in npcm_gpio_clr()
129 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); in npcm_gpio_clr()
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/linux/drivers/i2c/busses/
H A Di2c-npcm7xx.c1 // SPDX-License-Identifier: GPL-2.0
125 #define NPCM_I2CTXF_CTL 0x12 /* Tx-FIFO Control */
128 #define NPCM_I2CTXF_STS 0x1A /* Tx-FIFO Status */
129 #define NPCM_I2CRXF_STS 0x1C /* Rx-FIFO Status */
130 #define NPCM_I2CRXF_CTL 0x1E /* Rx-FIFO Control */
343 u8 i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3); in npcm_i2c_select_bank()
349 iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3); in npcm_i2c_select_bank()
354 bus->stop_ind = I2C_NO_STATUS_IND; in npcm_i2c_init_params()
355 bus->rd_size = 0; in npcm_i2c_init_params()
356 bus->wr_size = 0; in npcm_i2c_init_params()
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