Lines Matching +full:npcm750 +full:- +full:gcr
1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/reset-controller.h>
20 #include <soc/nuvoton/clock-npcm8xx.h>
22 /* NPCM7xx GCR registers */
109 writel(NPCM_SWRST << rc->sw_reset_number, rc->base + NPCM_SWRSTR); in npcm_rc_restart()
126 spin_lock_irqsave(&rc->lock, flags); in npcm_rc_setclear_reset()
127 stat = readl(rc->base + ctrl_offset); in npcm_rc_setclear_reset()
129 writel(stat | rst_bit, rc->base + ctrl_offset); in npcm_rc_setclear_reset()
131 writel(stat & ~rst_bit, rc->base + ctrl_offset); in npcm_rc_setclear_reset()
132 spin_unlock_irqrestore(&rc->lock, flags); in npcm_rc_setclear_reset()
155 return (readl(rc->base + ctrl_offset) & rst_bit); in npcm_rc_status()
166 offset = reset_spec->args[0]; in npcm_reset_xlate()
167 for (off_num = 0 ; off_num < rc->info->num_ipsrst ; off_num++) { in npcm_reset_xlate()
168 if (offset == rc->info->ipsrst[off_num]) { in npcm_reset_xlate()
175 dev_err(rcdev->dev, "Error reset register (0x%x)\n", offset); in npcm_reset_xlate()
176 return -EINVAL; in npcm_reset_xlate()
179 bit = reset_spec->args[1]; in npcm_reset_xlate()
181 dev_err(rcdev->dev, "Error reset number (%d)\n", bit); in npcm_reset_xlate()
182 return -EINVAL; in npcm_reset_xlate()
189 { .compatible = "nuvoton,npcm750-reset", .data = &npxm7xx_reset_info},
190 { .compatible = "nuvoton,npcm845-reset", .data = &npxm8xx_reset_info},
202 regmap_read(rc->gcr_regmap, NPCM_MDLR_OFFSET, &mdlr); in npcm_usb_reset_npcm7xx()
220 iprst1 = readl(rc->base + NPCM_IPSRST1); in npcm_usb_reset_npcm7xx()
221 iprst2 = readl(rc->base + NPCM_IPSRST2); in npcm_usb_reset_npcm7xx()
222 iprst3 = readl(rc->base + NPCM_IPSRST3); in npcm_usb_reset_npcm7xx()
229 writel(iprst1, rc->base + NPCM_IPSRST1); in npcm_usb_reset_npcm7xx()
230 writel(iprst2, rc->base + NPCM_IPSRST2); in npcm_usb_reset_npcm7xx()
231 writel(iprst3, rc->base + NPCM_IPSRST3); in npcm_usb_reset_npcm7xx()
234 regmap_update_bits(rc->gcr_regmap, NPCM_USB1PHYCTL_OFFSET, in npcm_usb_reset_npcm7xx()
236 regmap_update_bits(rc->gcr_regmap, NPCM_USB2PHYCTL_OFFSET, in npcm_usb_reset_npcm7xx()
241 writel(iprst3, rc->base + NPCM_IPSRST3); in npcm_usb_reset_npcm7xx()
246 regmap_update_bits(rc->gcr_regmap, NPCM_USB1PHYCTL_OFFSET, in npcm_usb_reset_npcm7xx()
248 regmap_update_bits(rc->gcr_regmap, NPCM_USB2PHYCTL_OFFSET, in npcm_usb_reset_npcm7xx()
256 writel(iprst1, rc->base + NPCM_IPSRST1); in npcm_usb_reset_npcm7xx()
257 writel(iprst2, rc->base + NPCM_IPSRST2); in npcm_usb_reset_npcm7xx()
258 writel(iprst3, rc->base + NPCM_IPSRST3); in npcm_usb_reset_npcm7xx()
270 regmap_read(rc->gcr_regmap, NPCM_MDLR_OFFSET, &mdlr); in npcm_usb_reset_npcm8xx()
290 iprst1 = readl(rc->base + NPCM_IPSRST1); in npcm_usb_reset_npcm8xx()
291 iprst2 = readl(rc->base + NPCM_IPSRST2); in npcm_usb_reset_npcm8xx()
292 iprst3 = readl(rc->base + NPCM_IPSRST3); in npcm_usb_reset_npcm8xx()
293 iprst4 = readl(rc->base + NPCM_IPSRST4); in npcm_usb_reset_npcm8xx()
301 writel(iprst1, rc->base + NPCM_IPSRST1); in npcm_usb_reset_npcm8xx()
302 writel(iprst2, rc->base + NPCM_IPSRST2); in npcm_usb_reset_npcm8xx()
303 writel(iprst3, rc->base + NPCM_IPSRST3); in npcm_usb_reset_npcm8xx()
304 writel(iprst4, rc->base + NPCM_IPSRST4); in npcm_usb_reset_npcm8xx()
307 regmap_update_bits(rc->gcr_regmap, NPCM_USB1PHYCTL_OFFSET, in npcm_usb_reset_npcm8xx()
309 regmap_update_bits(rc->gcr_regmap, NPCM_USB2PHYCTL_OFFSET, in npcm_usb_reset_npcm8xx()
311 regmap_update_bits(rc->gcr_regmap, NPCM_USB3PHYCTL_OFFSET, in npcm_usb_reset_npcm8xx()
316 writel(iprst3, rc->base + NPCM_IPSRST3); in npcm_usb_reset_npcm8xx()
318 writel(iprst4, rc->base + NPCM_IPSRST4); in npcm_usb_reset_npcm8xx()
321 regmap_update_bits(rc->gcr_regmap, NPCM_USB1PHYCTL_OFFSET, in npcm_usb_reset_npcm8xx()
323 regmap_update_bits(rc->gcr_regmap, NPCM_USB2PHYCTL_OFFSET, in npcm_usb_reset_npcm8xx()
325 regmap_update_bits(rc->gcr_regmap, NPCM_USB3PHYCTL_OFFSET, in npcm_usb_reset_npcm8xx()
334 writel(iprst1, rc->base + NPCM_IPSRST1); in npcm_usb_reset_npcm8xx()
335 writel(iprst2, rc->base + NPCM_IPSRST2); in npcm_usb_reset_npcm8xx()
336 writel(iprst3, rc->base + NPCM_IPSRST3); in npcm_usb_reset_npcm8xx()
337 writel(iprst4, rc->base + NPCM_IPSRST4); in npcm_usb_reset_npcm8xx()
346 struct device *dev = &pdev->dev; in npcm_usb_reset()
348 rc->gcr_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "nuvoton,sysgcr"); in npcm_usb_reset()
349 if (IS_ERR(rc->gcr_regmap)) { in npcm_usb_reset()
350 dev_warn(&pdev->dev, "Failed to find nuvoton,sysgcr property, please update the device tree\n"); in npcm_usb_reset()
351 dev_info(&pdev->dev, "Using nuvoton,npcm750-gcr for Poleg backward compatibility\n"); in npcm_usb_reset()
352 rc->gcr_regmap = syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr"); in npcm_usb_reset()
353 if (IS_ERR(rc->gcr_regmap)) { in npcm_usb_reset()
354 dev_err(&pdev->dev, "Failed to find nuvoton,npcm750-gcr"); in npcm_usb_reset()
355 return PTR_ERR(rc->gcr_regmap); in npcm_usb_reset()
359 rc->info = device_get_match_data(dev); in npcm_usb_reset()
360 switch (rc->info->bmc_id) { in npcm_usb_reset()
368 return -ENODEV; in npcm_usb_reset()
404 return ERR_PTR(-ENOMEM); in npcm_clock_adev_alloc()
406 rdev->base = rst_data->base; in npcm_clock_adev_alloc()
408 adev = &rdev->adev; in npcm_clock_adev_alloc()
409 adev->name = clk_name; in npcm_clock_adev_alloc()
410 adev->dev.parent = rst_data->dev; in npcm_clock_adev_alloc()
411 adev->dev.release = npcm_clock_adev_release; in npcm_clock_adev_alloc()
412 adev->id = 555u; in npcm_clock_adev_alloc()
438 return devm_add_action_or_reset(rst_data->dev, npcm_clock_unregister_adev, adev); in npcm8xx_clock_controller_register()
446 rc = devm_kzalloc(&pdev->dev, sizeof(*rc), GFP_KERNEL); in npcm_rc_probe()
448 return -ENOMEM; in npcm_rc_probe()
450 rc->base = devm_platform_ioremap_resource(pdev, 0); in npcm_rc_probe()
451 if (IS_ERR(rc->base)) in npcm_rc_probe()
452 return PTR_ERR(rc->base); in npcm_rc_probe()
454 spin_lock_init(&rc->lock); in npcm_rc_probe()
456 rc->rcdev.owner = THIS_MODULE; in npcm_rc_probe()
457 rc->rcdev.ops = &npcm_rc_ops; in npcm_rc_probe()
458 rc->rcdev.of_node = pdev->dev.of_node; in npcm_rc_probe()
459 rc->rcdev.of_reset_n_cells = 2; in npcm_rc_probe()
460 rc->rcdev.of_xlate = npcm_reset_xlate; in npcm_rc_probe()
461 rc->dev = &pdev->dev; in npcm_rc_probe()
463 ret = devm_reset_controller_register(&pdev->dev, &rc->rcdev); in npcm_rc_probe()
465 dev_err(&pdev->dev, "unable to register device\n"); in npcm_rc_probe()
470 dev_warn(&pdev->dev, "NPCM USB reset failed, can cause issues with UDC and USB host\n"); in npcm_rc_probe()
472 if (!of_property_read_u32(pdev->dev.of_node, "nuvoton,sw-reset-number", in npcm_rc_probe()
473 &rc->sw_reset_number)) { in npcm_rc_probe()
474 if (rc->sw_reset_number && rc->sw_reset_number < 5) { in npcm_rc_probe()
475 rc->restart_nb.priority = 192; in npcm_rc_probe()
476 rc->restart_nb.notifier_call = npcm_rc_restart; in npcm_rc_probe()
477 ret = register_restart_handler(&rc->restart_nb); in npcm_rc_probe()
479 dev_warn(&pdev->dev, "failed to register restart handler\n"); in npcm_rc_probe()
485 switch (rc->info->bmc_id) { in npcm_rc_probe()
487 return npcm8xx_clock_controller_register(rc, "clk-npcm8xx"); in npcm_rc_probe()
496 .name = "npcm-reset",