1 // SPDX-License-Identifier: GPL-2.0
15 /* NPCM GCR module */
31 /* NPCM_PECI_CTL_STS - 0x00 : Control Register */
38 /* NPCM_PECI_RD_LENGTH - 0x04 : Command Register */
41 /* NPCM_PECI_CMD - 0x10 : Command Register */
44 /* NPCM_PECI_WR_LENGTH - 0x1C : Command Register */
47 /* NPCM_PECI_PDDR - 0x2C : Command Register */
75 	struct npcm_peci *priv = dev_get_drvdata(controller->dev.parent);  in npcm_peci_xfer()
76 	unsigned long timeout = msecs_to_jiffies(priv->cmd_timeout_ms);  in npcm_peci_xfer()
82 	ret = regmap_read_poll_timeout(priv->regmap, NPCM_PECI_CTL_STS, cmd_sts,  in npcm_peci_xfer()
87 		return ret; /* -ETIMEDOUT */  in npcm_peci_xfer()
89 	spin_lock_irq(&priv->lock);  in npcm_peci_xfer()
90 	reinit_completion(&priv->xfer_complete);  in npcm_peci_xfer()
92 	regmap_write(priv->regmap, NPCM_PECI_ADDR, addr);  in npcm_peci_xfer()
93 	regmap_write(priv->regmap, NPCM_PECI_RD_LENGTH, NPCM_PECI_WR_LEN_MASK & req->rx.len);  in npcm_peci_xfer()
94 	regmap_write(priv->regmap, NPCM_PECI_WR_LENGTH, NPCM_PECI_WR_LEN_MASK & req->tx.len);  in npcm_peci_xfer()
96 	if (req->tx.len) {  in npcm_peci_xfer()
97 		regmap_write(priv->regmap, NPCM_PECI_CMD, req->tx.buf[0]);  in npcm_peci_xfer()
99 		for (i = 0; i < (req->tx.len - 1); i++)  in npcm_peci_xfer()
100 			regmap_write(priv->regmap, NPCM_PECI_DAT_INOUT(i), req->tx.buf[i + 1]);  in npcm_peci_xfer()
104 	dev_dbg(priv->dev, "addr : %#02x, tx.len : %#02x, rx.len : %#02x\n",  in npcm_peci_xfer()
105 		addr, req->tx.len, req->rx.len);  in npcm_peci_xfer()
106 	print_hex_dump_bytes("TX : ", DUMP_PREFIX_NONE, req->tx.buf, req->tx.len);  in npcm_peci_xfer()
109 	priv->status = 0;  in npcm_peci_xfer()
110 	regmap_update_bits(priv->regmap, NPCM_PECI_CTL_STS, NPCM_PECI_CTRL_START_BUSY,  in npcm_peci_xfer()
113 	spin_unlock_irq(&priv->lock);  in npcm_peci_xfer()
115 	ret = wait_for_completion_interruptible_timeout(&priv->xfer_complete, timeout);  in npcm_peci_xfer()
120 		dev_dbg(priv->dev, "timeout waiting for a response\n");  in npcm_peci_xfer()
121 		return -ETIMEDOUT;  in npcm_peci_xfer()
124 	spin_lock_irq(&priv->lock);  in npcm_peci_xfer()
126 	if (priv->status != NPCM_PECI_CTRL_DONE) {  in npcm_peci_xfer()
127 		spin_unlock_irq(&priv->lock);  in npcm_peci_xfer()
128 		dev_dbg(priv->dev, "no valid response, status: %#02x\n", priv->status);  in npcm_peci_xfer()
129 		return -EIO;  in npcm_peci_xfer()
132 	regmap_write(priv->regmap, NPCM_PECI_CMD, 0);  in npcm_peci_xfer()
134 	for (i = 0; i < req->rx.len; i++) {  in npcm_peci_xfer()
135 		regmap_read(priv->regmap, NPCM_PECI_DAT_INOUT(i), &msg_rd);  in npcm_peci_xfer()
136 		req->rx.buf[i] = (u8)msg_rd;  in npcm_peci_xfer()
139 	spin_unlock_irq(&priv->lock);  in npcm_peci_xfer()
142 	print_hex_dump_bytes("RX : ", DUMP_PREFIX_NONE, req->rx.buf, req->rx.len);  in npcm_peci_xfer()
153 	spin_lock(&priv->lock);  in npcm_peci_irq_handler()
154 	regmap_read(priv->regmap, NPCM_PECI_CTL_STS, &status);  in npcm_peci_irq_handler()
155 	priv->status |= (status & NPCM_PECI_INT_MASK);  in npcm_peci_irq_handler()
169 		complete(&priv->xfer_complete);  in npcm_peci_irq_handler()
172 	regmap_write_bits(priv->regmap, NPCM_PECI_CTL_STS, NPCM_PECI_INT_MASK, status_ack);  in npcm_peci_irq_handler()
174 	spin_unlock(&priv->lock);  in npcm_peci_irq_handler()
183 	priv->clk = devm_clk_get_enabled(priv->dev, NULL);  in npcm_peci_init_ctrl()
184 	if (IS_ERR(priv->clk)) {  in npcm_peci_init_ctrl()
185 		dev_err(priv->dev, "failed to get ref clock\n");  in npcm_peci_init_ctrl()
186 		return PTR_ERR(priv->clk);  in npcm_peci_init_ctrl()
189 	ret = device_property_read_u32(priv->dev, "cmd-timeout-ms", &priv->cmd_timeout_ms);  in npcm_peci_init_ctrl()
191 		priv->cmd_timeout_ms = NPCM_PECI_CMD_TIMEOUT_MS_DEFAULT;  in npcm_peci_init_ctrl()
192 	} else if (priv->cmd_timeout_ms > NPCM_PECI_CMD_TIMEOUT_MS_MAX ||  in npcm_peci_init_ctrl()
193 		   priv->cmd_timeout_ms == 0) {  in npcm_peci_init_ctrl()
194 		dev_warn(priv->dev, "invalid cmd-timeout-ms: %u, falling back to: %u\n",  in npcm_peci_init_ctrl()
195 			 priv->cmd_timeout_ms, NPCM_PECI_CMD_TIMEOUT_MS_DEFAULT);  in npcm_peci_init_ctrl()
197 		priv->cmd_timeout_ms = NPCM_PECI_CMD_TIMEOUT_MS_DEFAULT;  in npcm_peci_init_ctrl()
200 	regmap_update_bits(priv->regmap, NPCM_PECI_CTL2, NPCM_PECI_CTL2_MASK,  in npcm_peci_init_ctrl()
203 	regmap_update_bits(priv->regmap, NPCM_PECI_PDDR, NPCM_PECI_PDDR_MASK,  in npcm_peci_init_ctrl()
206 	ret = regmap_read_poll_timeout(priv->regmap, NPCM_PECI_CTL_STS, cmd_sts,  in npcm_peci_init_ctrl()
211 		return ret; /* -ETIMEDOUT */  in npcm_peci_init_ctrl()
214 	regmap_update_bits(priv->regmap, NPCM_PECI_CTL_STS, NPCM_PECI_CTRL_DONE_INT_EN,  in npcm_peci_init_ctrl()
238 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);  in npcm_peci_probe()
240 		return -ENOMEM;  in npcm_peci_probe()
242 	priv->dev = &pdev->dev;  in npcm_peci_probe()
243 	dev_set_drvdata(&pdev->dev, priv);  in npcm_peci_probe()
249 	priv->regmap = devm_regmap_init_mmio(&pdev->dev, base, &npcm_peci_regmap_config);  in npcm_peci_probe()
250 	if (IS_ERR(priv->regmap))  in npcm_peci_probe()
251 		return PTR_ERR(priv->regmap);  in npcm_peci_probe()
253 	priv->irq = platform_get_irq(pdev, 0);  in npcm_peci_probe()
254 	if (priv->irq < 0)  in npcm_peci_probe()
255 		return priv->irq;  in npcm_peci_probe()
257 	ret = devm_request_irq(&pdev->dev, priv->irq, npcm_peci_irq_handler,  in npcm_peci_probe()
258 			       0, "peci-npcm-irq", priv);  in npcm_peci_probe()
262 	init_completion(&priv->xfer_complete);  in npcm_peci_probe()
263 	spin_lock_init(&priv->lock);  in npcm_peci_probe()
269 	controller = devm_peci_controller_add(priv->dev, &npcm_ops);  in npcm_peci_probe()
271 		return dev_err_probe(priv->dev, PTR_ERR(controller),  in npcm_peci_probe()
274 	priv->controller = controller;  in npcm_peci_probe()
280 	{ .compatible = "nuvoton,npcm750-peci", },
281 	{ .compatible = "nuvoton,npcm845-peci", },