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/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls2080a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
5 * Copyright 2014-2016 Freescale Semiconductor, Inc.
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include "fsl-ls208xa.dtsi"
17 compatible = "arm,cortex-a57-pmu";
25 compatible = "arm,cortex-a57";
28 cpu-idle-states = <&CPU_PW20>;
29 next-level-cache = <&cluster0_l2>;
30 #cooling-cells = <2>;
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H A Dfsl-ls1028a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1028A family SoC.
5 * Copyright 2018-2020 NXP
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
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/linux/Documentation/devicetree/bindings/pci/
H A Dnvidia,tegra20-pcie.txt4 - compatible: Must be:
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
10 - power-domains: To ungate power partition by BPMP powergate driver. Must
13 - device_type: Must be "pci"
14 - reg: A list of physical base address and length for each set of controller
15 registers. Must contain an entry for each entry in the reg-names property.
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H A Dv3,v360epc-pci.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pci/v3,v360epc-pci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
16 - $ref: /schemas/pci/pci-host-bridge.yaml#
21 - const: arm,integrator-ap-pci
22 - const: v3,v360epc-pci
26 - description: V3 host bridge controller
27 - description: Configuration space
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H A Dqcom,pcie-sa8255p.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sa8255p.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
19 const: qcom,pcie-sa8255p
25 address corresponds to the first bus in the "bus-range" property. If
26 no "bus-range" is specified, this will be bus 0 (the default).
31 As described in IEEE Std 1275-1994, but must provide at least a
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H A Dhost-generic-pci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/host-generic-pci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
13 Firmware-initialised PCI host controllers and PCI emulations, such as the
14 virtio-pci implementations found in kvmtool and other para-virtualised
21 Configuration Space is assumed to be memory-mapped (as opposed to being
26 For CAM, this 24-bit offset is:
41 - description:
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H A Dnvidia,tegra194-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
20 See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device
26 - nvidia,tegra194-pcie
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H A Dmarvell,armada8k-pcie.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/marvell,armada8k-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thomas Petazzoni <thomas.petazzoni@bootlin.com>
20 - marvell,armada8k-pcie
22 - compatible
25 - $ref: snps,dw-pcie.yaml#
30 - enum:
31 - marvell,armada8k-pcie
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H A Dfsl,layerscape-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
16 which is used to describe the PLL settings at the time of chip-reset.
26 - enum:
27 - fsl,ls1012a-pcie
28 - fsl,ls1021a-pcie
29 - fsl,ls1028a-pcie
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/linux/drivers/pci/
H A Dsetup-bus.c1 // SPDX-License-Identifier: GPL-2.0
11 * PCI-PCI bridges cleanup, sorted resource allocation.
14 * tighter packing. Prefetchable range support.
54 list_del(&dev_res->list); in free_list()
60 * add_to_list() - Add a new resource tracker to the list
75 return -ENOMEM; in add_to_list()
77 tmp->res = res; in add_to_list()
78 tmp->dev = dev; in add_to_list()
79 tmp->start = res->start; in add_to_list()
80 tmp->end = res->end; in add_to_list()
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H A Dsetup-res.c1 // SPDX-License-Identifier: GPL-2.0
35 /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */ in pci_std_update_resource()
36 if (dev->is_virtfn) in pci_std_update_resource()
43 if (!res->flags) in pci_std_update_resource()
46 if (res->flags & IORESOURCE_UNSET) in pci_std_update_resource()
50 * Ignore non-moveable resources. This might be legacy resources for in pci_std_update_resource()
54 if (res->flags & IORESOURCE_PCI_FIXED) in pci_std_update_resource()
57 pcibios_resource_to_bus(dev->bus, &region, res); in pci_std_update_resource()
60 if (res->flags & IORESOURCE_IO) { in pci_std_update_resource()
62 new |= res->flags & ~PCI_BASE_ADDRESS_IO_MASK; in pci_std_update_resource()
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/linux/drivers/pci/controller/
H A Dpci-v3-semi.c1 // SPDX-License-Identifier: GPL-2.0
6 * Based on the code from arch/arm/mach-integrator/pci_v3.c
8 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd
134 /* PCI BASE bits (PCI -> Local Bus) */
141 /* PCI MAP bits (PCI -> Local bus) */
150 /* LB_BASE0,1 bits (Local bus -> PCI) */
172 /* LB_MAP0,1 bits (Local bus -> PCI) */
185 /* LB_BASE2 bits (Local bus -> PCI IO) */
192 /* LB_MAP2 bits (Local bus -> PCI IO) */
229 /* ARM Integrator-specific extended control registers */
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H A Dpci-thunder-pem.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2015 - 2016 Cavium, Inc.
12 #include <linux/pci-acpi.h>
13 #include <linux/pci-ecam.h>
15 #include <linux/io-64-nonatomic-lo-hi.h>
17 #include "pci-host-common.h"
27 * N.B. This is a non-standard platform-specific ECAM bus shift value. For
29 * include/linux/pci-ecam.h.
42 struct pci_config_window *cfg = bus->sysdata; in thunder_pem_bridge_read()
43 struct thunder_pem_pci *pem_pci = (struct thunder_pem_pci *)cfg->priv; in thunder_pem_bridge_read()
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/linux/arch/arm/boot/dts/st/
H A Dspear1310.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
15 compatible = "st,spear-spics-gpio";
17 st-spics,peripcfg-reg = <0x3b0>;
18 st-spics,sw-enable-bit = <12>;
19 st-spics,cs-value-bit = <11>;
20 st-spics,cs-enable-mask = <3>;
21 st-spics,cs-enable-shift = <8>;
22 gpio-controller;
23 #gpio-cells = <2>;
27 compatible = "st,spear1310-miphy";
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H A Dspear1340.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
16 compatible = "st,spear-spics-gpio";
18 st-spics,peripcfg-reg = <0x42c>;
19 st-spics,sw-enable-bit = <21>;
20 st-spics,cs-value-bit = <20>;
21 st-spics,cs-enable-mask = <3>;
22 st-spics,cs-enable-shift = <18>;
23 gpio-controller;
24 #gpio-cells = <2>;
29 compatible = "st,spear1340-miphy";
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/linux/arch/arm/boot/dts/arm/
H A Dversatile-pb.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include "versatile-ab.dts"
6 compatible = "arm,versatile-pb";
10 sic: interrupt-controller@10003000 {
11 clear-mask = <0xffffffff>;
14 * figure 3-30 page 3-74 of ARM DUI 0224B
16 valid-mask = <0x7fe003ff>;
23 gpio-controller;
24 #gpio-cells = <2>;
25 interrupt-controller;
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/linux/arch/x86/pci/
H A Dbroadcom_bus.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include <asm/pci-direct.h>
45 /* read the non-prefetchable memory window */ in cnb20le_res()
55 /* read the prefetchable memory window */ in cnb20le_res()
81 list_for_each_entry(root_res, &info->resources, list) in cnb20le_res()
82 printk(KERN_INFO "host bridge window %pR\n", &root_res->res); in cnb20le_res()
/linux/sound/pci/lx6464es/
H A Dlx6464es.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* -*- linux-c -*- *
65 void __iomem *port_dsp_bar; /* memory port (32-bit,
66 * non-prefetchable,
/linux/arch/powerpc/boot/
H A Dcuboot-pq2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Old U-boot compatibility for PowerQUICC II
15 #include "fsl-soc.h"
40 /* Different versions of u-boot put the BCSR in different places, and
44 * For any node defined as compatible with fsl,pq2-localbus,
58 if (!bus_node || !dt_is_compatible(bus_node, "fsl,pq2-localbus")) in update_cs_ranges()
103 option | ~(cs_ranges_buf[i].size - 1)); in update_cs_ranges()
113 /* Older u-boots don't set PCI up properly. Update the hardware to match
114 * the device tree. The prefetch mem region and non-prefetch mem region
117 * 32-bit PCI is supported. All three region types (prefetchable mem,
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/linux/arch/powerpc/platforms/powernv/
H A Dpci-sriov.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 * The majority of the complexity in supporting SR-IOV on PowerNV comes from
20 * the address range that we want to map to be power-of-two sized and aligned.
24 * For a SR-IOV BAR things are a little more awkward since size and alignment
25 * are not coupled. The alignment is set based on the per-VF BAR size, but
26 * the total BAR area is: number-of-vfs * per-vf-size. The number of VFs
29 * allocate the SR-IOV BARs in a way that lets us map them using the MBT.
32 * of MBT entry that we use. We only support SR-IOV on PHB3 (IODA2) and above,
40 * b) An un-segmented BAR that maps the whole address range to a specific PE.
43 * We prefer to use mode a) since it only requires one MBT entry per SR-IOV BAR
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/linux/include/uapi/linux/
H A Dpci_regs.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
5 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
25 * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
26 * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of
50 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
59 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
83 #define PCI_HEADER_TYPE_MFD 0x80 /* Multi-Function Device (possible) */
109 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
124 /* 0x35-0x3b are reserved */
130 /* Header type 1 (PCI-to-PCI bridges) */
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/linux/drivers/pci/hotplug/
H A Dcpqphp_pci.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
49 endp = (end - sizeof(struct hrt) + 1); in detect_HRT_floating_pointer()
80 if (func->pci_dev == NULL) in cpqhp_configure_device()
81 func->pci_dev = pci_get_domain_bus_and_slot(0, func->bus, in cpqhp_configure_device()
82 PCI_DEVFN(func->device, in cpqhp_configure_device()
83 func->function)); in cpqhp_configure_device()
86 if (func->pci_dev == NULL) { in cpqhp_configure_device()
89 num = pci_scan_slot(ctrl->pci_dev->bus, PCI_DEVFN(func->device, func->function)); in cpqhp_configure_device()
91 pci_bus_add_devices(ctrl->pci_dev->bus); in cpqhp_configure_device()
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/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra234.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
9 #include <dt-bindings/power/tegra234-powergate.h>
10 #include <dt-bindings/reset/tegra234-reset.h>
11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
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/linux/arch/arm/boot/dts/amazon/
H A Dalpine.dtsi27 #include <dt-bindings/interrupt-controller/arm-gic.h>
30 #address-cells = <2>;
31 #size-cells = <2>;
42 #address-cells = <1>;
43 #size-cells = <0>;
44 enable-method = "al,alpine-smp";
47 compatible = "arm,cortex-a15";
50 clock-frequency = <1700000000>;
54 compatible = "arm,cortex-a15";
57 clock-frequency = <1700000000>;
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/linux/Documentation/PCI/
H A Dsysfs-pci.rst1 .. SPDX-License-Identifier: GPL-2.0
11 |-- 0000:17:00.0
12 | |-- class
13 | |-- config
14 | |-- device
15 | |-- enable
16 | |-- irq
17 | |-- local_cpus
18 | |-- remove
19 | |-- resource
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