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/linux/Documentation/devicetree/bindings/pci/
H A Dv3-v360epc-pci.txt6 - compatible: should be one of:
7 "v3,v360epc-pci"
8 "arm,integrator-ap-pci", "v3,v360epc-pci"
9 - reg: should contain two register areas:
12 - interrupts: should contain a reference to the V3 error interrupt
14 - bus-range: see pci.txt
15 - ranges: this follows the standard PCI bindings in the IEEE Std
16 1275-1994 (see pci.txt) with the following restriction:
17 - The non-prefetchable and prefetchable memory windows must
19 - The prefetchable memory window must be immediately adjacent
[all …]
H A Dnvidia,tegra20-pcie.txt4 - compatible: Must be:
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
10 - power-domains: To ungate power partition by BPMP powergate driver. Must
13 - device_type: Must be "pci"
14 - reg: A list of physical base address and length for each set of controller
15 registers. Must contain an entry for each entry in the reg-names property.
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H A Dhost-generic-pci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/host-generic-pci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
13 Firmware-initialised PCI host controllers and PCI emulations, such as the
14 virtio-pci implementations found in kvmtool and other para-virtualised
21 Configuration Space is assumed to be memory-mapped (as opposed to being
26 For CAM, this 24-bit offset is:
41 - description:
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H A Dnvidia,tegra194-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
20 See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device
26 - nvidia,tegra194-pcie
[all …]
H A Dpci-armada8k.txt4 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
7 - compatible: "marvell,armada8k-pcie"
8 - reg: must contain two register regions
9 - the control register region
10 - the config space region
11 - reg-names:
12 - "ctrl" for the control register region
13 - "config" for the config space region
14 - interrupts: Interrupt specifier for the PCIe controller
15 - clocks: reference to the PCIe controller clocks
[all …]
H A Daxis,artpec6-pcie.txt1 * Axis ARTPEC-6 PCIe interface
4 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
7 - compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
8 "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode;
9 "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode;
10 "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode;
11 - reg: base addresses and lengths of the PCIe controller (DBI),
13 - reg-names: Must include the following entries:
14 - "dbi"
15 - "phy"
[all …]
H A Dfsl,layerscape-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
16 which is used to describe the PLL settings at the time of chip-reset.
26 - enum:
27 - fsl,ls1012a-pcie
28 - fsl,ls1021a-pcie
29 - fsl,ls1028a-pcie
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/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls2080a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
5 * Copyright 2014-2016 Freescale Semiconductor, Inc.
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include "fsl-ls208xa.dtsi"
17 compatible = "arm,cortex-a57-pmu";
25 compatible = "arm,cortex-a57";
28 cpu-idle-states = <&CPU_PW20>;
29 next-level-cache = <&cluster0_l2>;
30 #cooling-cells = <2>;
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H A Dfsl-ls1028a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1028A family SoC.
5 * Copyright 2018-2020 NXP
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
[all …]
H A Dfsl-ls1088a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1088A family SoC.
5 * Copyright 2017-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
26 #address-cells = <1>;
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H A Dfsl-lx2160a.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree Include file for Layerscape-LX2160A family SoC.
5 // Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
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/linux/drivers/pci/controller/
H A Dpci-v3-semi.c1 // SPDX-License-Identifier: GPL-2.0
6 * Based on the code from arch/arm/mach-integrator/pci_v3.c
8 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd
134 /* PCI BASE bits (PCI -> Local Bus) */
141 /* PCI MAP bits (PCI -> Local bus) */
150 /* LB_BASE0,1 bits (Local bus -> PCI) */
172 /* LB_MAP0,1 bits (Local bus -> PCI) */
185 /* LB_BASE2 bits (Local bus -> PCI IO) */
192 /* LB_MAP2 bits (Local bus -> PCI IO) */
229 /* ARM Integrator-specific extended control registers */
[all …]
/linux/arch/arm/boot/dts/st/
H A Dspear1310.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
15 compatible = "st,spear-spics-gpio";
17 st-spics,peripcfg-reg = <0x3b0>;
18 st-spics,sw-enable-bit = <12>;
19 st-spics,cs-value-bit = <11>;
20 st-spics,cs-enable-mask = <3>;
21 st-spics,cs-enable-shift = <8>;
22 gpio-controller;
23 #gpio-cells = <2>;
27 compatible = "st,spear1310-miphy";
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H A Dspear1340.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
16 compatible = "st,spear-spics-gpio";
18 st-spics,peripcfg-reg = <0x42c>;
19 st-spics,sw-enable-bit = <21>;
20 st-spics,cs-value-bit = <20>;
21 st-spics,cs-enable-mask = <3>;
22 st-spics,cs-enable-shift = <18>;
23 gpio-controller;
24 #gpio-cells = <2>;
29 compatible = "st,spear1340-miphy";
[all …]
/linux/arch/arm/boot/dts/arm/
H A Dversatile-pb.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include "versatile-ab.dts"
6 compatible = "arm,versatile-pb";
10 sic: interrupt-controller@10003000 {
11 clear-mask = <0xffffffff>;
14 * figure 3-30 page 3-74 of ARM DUI 0224B
16 valid-mask = <0x7fe003ff>;
23 gpio-controller;
24 #gpio-cells = <2>;
25 interrupt-controller;
[all …]
/linux/arch/x86/pci/
H A Dbroadcom_bus.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include <asm/pci-direct.h>
45 /* read the non-prefetchable memory window */ in cnb20le_res()
55 /* read the prefetchable memory window */ in cnb20le_res()
81 list_for_each_entry(root_res, &info->resources, list) in cnb20le_res()
82 printk(KERN_INFO "host bridge window %pR\n", &root_res->res); in cnb20le_res()
/linux/sound/pci/lx6464es/
H A Dlx6464es.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* -*- linux-c -*- *
65 void __iomem *port_dsp_bar; /* memory port (32-bit,
66 * non-prefetchable,
/linux/arch/powerpc/boot/
H A Dcuboot-pq2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Old U-boot compatibility for PowerQUICC II
15 #include "fsl-soc.h"
40 /* Different versions of u-boot put the BCSR in different places, and
44 * For any node defined as compatible with fsl,pq2-localbus,
58 if (!bus_node || !dt_is_compatible(bus_node, "fsl,pq2-localbus")) in update_cs_ranges()
103 option | ~(cs_ranges_buf[i].size - 1)); in update_cs_ranges()
113 /* Older u-boots don't set PCI up properly. Update the hardware to match
114 * the device tree. The prefetch mem region and non-prefetch mem region
117 * 32-bit PCI is supported. All three region types (prefetchable mem,
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-cp11x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
9 #include <dt-bindings/thermal/thermal.h>
11 #include "armada-common.dtsi"
27 thermal-zones {
28 CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(ic-thermal) {
29 polling-delay-passive = <0>; /* Interrupt driven */
30 polling-delay = <0>; /* Interrupt driven */
32 thermal-sensors = <&CP11X_LABEL(thermal) 0>;
42 cooling-maps { };
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/linux/arch/powerpc/platforms/powernv/
H A Dpci-sriov.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 * The majority of the complexity in supporting SR-IOV on PowerNV comes from
20 * the address range that we want to map to be power-of-two sized and aligned.
24 * For a SR-IOV BAR things are a little more awkward since size and alignment
25 * are not coupled. The alignment is set based on the per-VF BAR size, but
26 * the total BAR area is: number-of-vfs * per-vf-size. The number of VFs
29 * allocate the SR-IOV BARs in a way that lets us map them using the MBT.
32 * of MBT entry that we use. We only support SR-IOV on PHB3 (IODA2) and above,
40 * b) An un-segmented BAR that maps the whole address range to a specific PE.
43 * We prefer to use mode a) since it only requires one MBT entry per SR-IOV BAR
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/linux/Documentation/admin-guide/media/
H A Dpci-cardlist.rst1 .. SPDX-License-Identifier: GPL-2.0
9 - Vendor ID and device ID;
10 - Subsystem ID and Subsystem device ID;
12 The ``lspci -nn`` command allows identifying the vendor/device PCI IDs:
14 .. code-block:: none
15 :emphasize-lines: 3
17 $ lspci -nn
23 …02:02.0 Multimedia video controller [0400]: Conexant Systems, Inc. CX23418 Single-Chip MPEG-2 Enco…
27 The subsystem IDs can be obtained using ``lspci -vn``
29 .. code-block:: none
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/linux/arch/arm/boot/dts/amazon/
H A Dalpine.dtsi27 #include <dt-bindings/interrupt-controller/arm-gic.h>
30 #address-cells = <2>;
31 #size-cells = <2>;
42 #address-cells = <1>;
43 #size-cells = <0>;
44 enable-method = "al,alpine-smp";
47 compatible = "arm,cortex-a15";
50 clock-frequency = <1700000000>;
54 compatible = "arm,cortex-a15";
57 clock-frequency = <1700000000>;
[all …]
/linux/Documentation/PCI/
H A Dsysfs-pci.rst1 .. SPDX-License-Identifier: GPL-2.0
11 |-- 0000:17:00.0
12 | |-- class
13 | |-- config
14 | |-- device
15 | |-- enable
16 | |-- irq
17 | |-- local_cpus
18 | |-- remove
19 | |-- resource
[all …]
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
[all …]
H A Dtegra234-p3740-0002+p3701-0008.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/sound/rt5640.h>
7 #include "tegra234-p3701-0008.dtsi"
11 compatible = "nvidia,p3740-0002+p3701-0008", "nvidia,p3701-0008", "nvidia,tegra234";
19 stdout-path = "serial0:115200n8";
29 dai-format = "i2s";
30 remote-endpoint = <&rt5640_ep>;
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