non\-prefetch (full) in projects: freebsd

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/freebsd/lib/libpmc/pmu-events/arch/arm64/fujitsu/a64fx/
H A D	other.json	3 "PublicDescription": "This event counts the occurrence count of the micro-operation split.", 6 "BriefDescription": "This event counts the occurrence count of the micro-operation split." 9 …o operation was committed because the oldest and uncommitted load/store/prefetch operation waits f… 12 …o operation was committed because the oldest and uncommitted load/store/prefetch operation waits f… 21 …instruction was committed because the oldest and uncommitted load/store/prefetch operation waits f… 24 …instruction was committed because the oldest and uncommitted load/store/prefetch operation waits f… 33 …instruction was committed because the oldest and uncommitted load/store/prefetch operation waits f… 36 …instruction was committed because the oldest and uncommitted load/store/prefetch operation waits f… 45 …unts every cycle that no instruction was committed due to the lack of an available prefetch port.", 48 …ounts every cycle that no instruction was committed due to the lack of an available prefetch port." [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/amdzen2/
H A D	memory.json	5 …"BriefDescription": "Non-forwardable conflict; used to reduce STLI's via software. All reasons. St… 6 …-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older … 24 "BriefDescription": "Retired lock instructions. Non-speculative lock succeeded.", 84 "BriefDescription": "A non-cacheable store and the non-cacheable commit buffer is full." 90 …esses, although these are generally rare. Each increment represents an eight-byte access, although… 197 "BriefDescription": "Total Page Table Walks on I-side.", 215 "BriefDescription": "Total Page Table Walks on D-side.", 238 "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative).", 244 …"BriefDescription": "Software Prefetch Instructions Dispatched (Speculative). PrefetchNTA instruct… 250 …"BriefDescription": "Software Prefetch Instructions Dispatched (Speculative). See docAPM3 PREFETCH… [all …]
H A D	cache.json	5 …ion": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including hardware and soft… 11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.", 17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.", 23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.", 29 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request… 35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.", 41 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches a… 64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.", 70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab… 76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.", [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/amdzen3/
H A D	memory.json	5 …"BriefDescription": "Non-forwardable conflict; used to reduce STLI's via software. All reasons. St… 6 …-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older … 24 "BriefDescription": "Retired lock instructions. Non-speculative lock succeeded.", 36 … "BriefDescription": "The number of retired CLFLUSH instructions. This is a non-speculative event." 46 …"BriefDescription": "Load-op-Store Dispatch. Dispatch of a single op that performs a load from and… 84 "BriefDescription": "A non-cacheable store and the non-cacheable commit buffer is full.", 91 …esses, although these are generally rare. Each increment represents an eight-byte access, although… 258 "BriefDescription": "Total Page Table Walks on I-side.", 276 "BriefDescription": "Total Page Table Walks on D-side.", 306 "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative).", [all …]
H A D	cache.json	5 …ion": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including hardware and soft… 11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.", 17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.", 23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.", 29 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request… 35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.", 41 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches a… 64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.", 70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab… 76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.", [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/amdzen1/
H A D	cache.json	5 …etch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cachea… 35 … instruction stream was being modified by another processor in an MP system - typically a highly u… 52 …l. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.", 58 …be (external or LS). The number of instruction cache lines invalidated. A non-SMC event is CMC (cr… 64 …iting fill response. The number of instruction cache lines invalidated. A non-SMC event is CMC (cr… 75 …ion": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including hardware and soft… 81 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.", 87 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.", 93 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.", 99 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request… [all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A D	l2c2x0.yaml	`1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Rob Herring <robh@kernel.org> 16 models (Note 1). Some of the properties that are just prefixed "cache-*" are 22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These 28 - $ref: /schemas/cache-controller.yaml# 33 - enum: 34 - arm,pl310-cache 35 - arm,l220-cache [all …]`
/freebsd/sys/contrib/device-tree/Bindings/cache/
H A D	l2c2x0.yaml	`1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Rob Herring <robh@kernel.org> 16 models (Note 1). Some of the properties that are just prefixed "cache-*" are 22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These 28 - $ref: /schemas/cache-controller.yaml# 33 - enum: 34 - arm,pl310-cache 35 - arm,l220-cache [all …]`
/freebsd/lib/libpmc/pmu-events/arch/powerpc/power8/
H A D	other.json	11 …"BriefDescription": "Cycles in 2-lpar mode. Threads 0-3 belong to Lpar0 and threads 4-7 belong to … 17 …cles in 4 LPAR mode. Threads 0-1 belong to lpar0, threads 2-3 belong to lpar1, threads 4-5 belong … 23 …p pump (prediction=correct) for all data types (demand load,data prefetch,inst prefetch,inst fetch… 24 …ip pump (prediction=correct) for all data types ( demand load,data,inst prefetch,inst fetch,xlate … 29 …s this scope was group pump for all data types (demand load,data prefetch,inst prefetch,inst fetch… 30 …his scope was group pump for all data types excluding data prefetch (demand load,inst prefetch,ins… 35 …ler than Initial Pump Scope for all data types (demand load,data prefetch,inst prefetch,inst fetch… 41 …n Initial Pump Scope (Chip) for all data types (demand load,data prefetch,inst prefetch,inst fetch… 42 …nitial pump was chip pumpfor all data types excluding data prefetch (demand load,inst prefetch,ins… 47 …s across all types of pumps for all data types (demand load,data prefetch,inst prefetch,inst fetch… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/ivytown/
H A D	uncore-cache.json	10 … "BriefDescription": "All LLC Misses (code+ data rd + data wr - including demand and prefetch)", 31 …"BriefDescription": "LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derive… 42 …"BriefDescription": "LLC misses - Uncacheable reads. Derived from unc_c_tor_inserts.miss_opcode.un… 53 …"BriefDescription": "LLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode.rfo_p… 64 …"BriefDescription": "LLC prefetch misses for code reads. Derived from unc_c_tor_inserts.miss_opcod… 75 …"BriefDescription": "LLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcod… 86 …"BriefDescription": "PCIe allocating writes that miss LLC - DDIO misses. Derived from unc_c_tor_in… 119 …"BriefDescription": "LLC misses for PCIe non-snoop reads. Derived from unc_c_tor_inserts.miss_opco… 130 …"BriefDescription": "LLC misses for PCIe non-snoop writes (full line). Derived from unc_c_tor_inse… 207 "BriefDescription": "PCIe non-snoop reads. Derived from unc_c_tor_inserts.opcode.pcie_read", [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/goldmont/
H A D	cache.json	22 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.", 37 …prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely ind… 140 … Typically a load will receive this indication when some other load or prefetch missed the L1 cac… 193 "BriefDescription": "Memory uops retired that split a cache-line (Precise event capable)", 205 "BriefDescription": "Load uops retired that split a cache-line (Precise event capable)", 217 "BriefDescription": "Stores uops retired that split a cache-line (Precise event capable)", 238 "BriefDescription": "Counts data reads (demand & prefetch) that hit the L2 cache.", 246 …"PublicDescription": "Counts data reads (demand & prefetch) that hit the L2 cache. Requires MSR_OF… 251 "BriefDescription": "Counts data reads (demand & prefetch) that miss the L2 cache.", 259 …"PublicDescription": "Counts data reads (demand & prefetch) that miss the L2 cache. Requires MSR_O… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/tremontx/
H A D	cache.json	26 …"BriefDescription": "Counts the number of demand and prefetch transactions that the External Queue… 33 …prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition wh… 108 …talled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", 118 …the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM).", 125 …truction cache or translation lookaside buffer (TLB) access which hit in DRAM or MMIO (non-DRAM).", 154 … the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", 164 …ber of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", 411 … were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was fo… 488 … were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was fo… 554 … were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was fo… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/goldmontplus/
H A D	cache.json	26 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.", 45 …prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely ind… 159 … Typically a load will receive this indication when some other load or prefetch missed the L1 cac… 216 "BriefDescription": "Memory uops retired that split a cache-line (Precise event capable)", 229 "BriefDescription": "Load uops retired that split a cache-line (Precise event capable)", 242 "BriefDescription": "Stores uops retired that split a cache-line (Precise event capable)", 266 …"BriefDescription": "Counts data reads (demand & prefetch) have any transaction responses from the… 276 …"PublicDescription": "Counts data reads (demand & prefetch) have any transaction responses from th… 281 "BriefDescription": "Counts data reads (demand & prefetch) hit the L2 cache.", 291 …"PublicDescription": "Counts data reads (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE… [all …]
/freebsd/lib/libpmc/
H A D	pmc.corei7.3	`44 .Bl -tag -width "Li PMC_CLASS_IAP" 46 Fixed-function counters that count only one hardware event per counter. 58 .%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual" 60 .%N "Order Number: 253669-033US" 67 Not all CPUs in this family implement fixed-function counters. 70 .Bl -column "PMC_CAP_INTERRUPT" "Support" 87 .Bl -tag -width indent 89 Configure the Off-core Response bits. 90 .Bl -tag -width indent 92 Counts the number of demand and DCU prefetch data reads of full [all …]`
H A D	pmc.westmere.3	44 .Bl -tag -width "Li PMC_CLASS_IAP" 46 Fixed-function counters that count only one hardware event per counter. 58 .%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual" 60 .%N "Order Number: 253669-033US" 69 .Bl -column "PMC_CAP_INTERRUPT" "Support" 86 .Bl -tag -width indent 88 Configure the Off-core Response bits. 89 .Bl -tag -width indent 91 Counts the number of demand and DCU prefetch data reads of full 97 Counts the number of demand and DCU prefetch reads for ownership [all …]
H A D	pmc.atom.3	`44 .Bl -tag -width "Li PMC_CLASS_IAP" 46 Fixed-function counters that count only one hardware event per counter. 58 .%B "IA-32 Intel(R) Architecture Software Developer's Manual" 60 .%N "Order Number 253669-027US" 69 .Bl -column "PMC_CAP_INTERRUPT" "Support" 86 .Bl -tag -width indent 94 Configure the PMC to count the number of de-asserted to asserted 120 Events that require core-specificity to be specified use a 126 .Bl -tag -width indent 142 .Bl -tag -width indent [all …]`
H A D	pmc.core2.3	44 .Bl -tag -width "Li PMC_CLASS_IAP" 46 Fixed-function counters that count only one hardware event per counter. 58 .%B "IA-32 Intel(R) Architecture Software Developer's Manual" 60 .%N "Order Number 253669-027US" 67 Not all CPUs in this family implement fixed-function counters. 70 .Bl -column "PMC_CAP_INTERRUPT" "Support" 87 .Bl -tag -width indent 93 Configure the PMC to count the number of de-asserted to asserted 119 Events that require core-specificity to be specified use a 125 .Bl -tag -width indent [all …]
H A D	pmc.core.3	`50 .%B IA-32 Intel\(rg Architecture Software Developer's Manual 52 .%N Order Number 253669-027US 63 .Bl -column "PMC_CAP_INTERRUPT" "Support" 80 .Bl -tag -width indent 86 Configure the PMC to count the number of de-asserted to asserted 112 Events that require core-specificity to be specified use a 118 .Bl -tag -width indent -compact 133 .Bl -tag -width indent -compact 142 Events that require a hardware prefetch qualifier to be specified use an 144 .Dq Li prefetch= Ns Ar value , [all …]`
/freebsd/sys/arm/arm/
H A D	pl310.c	`1 /- 2 SPDX-License-Identifier: BSD-3-Clause 72 mtx_lock_spin(&(sc)->sc_mtx); \ 76 mtx_unlock_spin(&(sc)->sc_mtx); \ 85 static const uint32_t g_l2cache_align_mask = (32 - 1); 94 {"arm,pl310", true}, /* Non-standard, FreeBSD. */ 95 {"arm,pl310-cache", true}, 125 uint32_t aux, prefetch; in pl310_print_config() local 130 prefetch = pl310_read4(sc, PL310_PREFETCH_CTRL); in pl310_print_config() 132 device_printf(sc->sc_dev, "Early BRESP response: %s\n", in pl310_print_config() [all …]`
/freebsd/lib/libpmc/pmu-events/arch/powerpc/power9/
H A D	marked.json	35 …as reloaded from local core's L2 with dispatch conflict due to an instruction fetch (not prefetch)" 80 …ache was reloaded from local core's L2 without conflict due to an instruction fetch (not prefetch)" 120 …other chip's memory on the same Node or Group (Distant) due to an instruction fetch (not prefetch)" 155 …r's Instruction cache was reloaded from local core's L2 due to an instruction fetch (not prefetch)" 195 …dified (M) data from another core's L3 on the same chip due to an instruction fetch (not prefetch)" 235 "BriefDescription": "Counts all Icache prefetch reloads ( includes demand turned into prefetch)" 265 …mp Scope was system pump for all data types excluding data prefetch (demand load,inst prefetch,ins… 270 …ish stall while waiting for the non-speculative finish of either a stcx waiting for its result or … 280 …nother chip's L4 on a different Node or Group (Distant) due to an instruction fetch (not prefetch)" 285 … pipeline cycles, or because the VSU is busy with multi-cycle instructions, or because of a write-… [all …]
H A D	other.json	60 …ferenced a line in an active fuzzy prefetch stream. The stream could have been allocated through t… 65 "BriefDescription": "Read-write data cache collisions" 90 "BriefDescription": "D-cache invalidates sent over the reload bus to the core" 95 …ruction cache was reloaded from the local chip's Memory due to an instruction fetch (not prefetch)" 115 …"BriefDescription": "Prefetch scope predictor selected GS or NNS, but was wrong because scope was … 200 "BriefDescription": "Read-write data cache collisions" 210 …riefDescription": "Prefetch stream allocated in the conservative phase by either the hardware pref… 275 "BriefDescription": "Prefetch stream allocated by the hardware prefetch mechanism" 280 …-word boundary, which causes it to require an additional slice than than what normally would be re… 300 "BriefDescription": "I-cache Invalidates sent over the realod bus to the core" [all …]
/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a75/
H A D	mmu.json	9 …lk handled by the MMU. This event is not counted when it is accessible from Non-secure EL0 or EL1", 12 …alk handled by the MMU. This event is not counted when it is accessible from Non-secure EL0 or EL1" 15 …lk handled by the MMU. This event is not counted when it is accessible from Non-secure EL0 or EL1", 18 …alk handled by the MMU. This event is not counted when it is accessible from Non-secure EL0 or EL1" 33 …on": "Duration of a translation table walk requested by a Preload instruction or Prefetch request", 36 …ion": "Duration of a translation table walk requested by a Preload instruction or Prefetch request"
/freebsd/lib/libpmc/pmu-events/arch/x86/icelake/
H A D	other.json	3 … where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.", 9 …s running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX… 21 … running with power-delivery for license level 1. This includes high current AVX 256-bit instruct… 33 … running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture). … 165 …"BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFET… 179 …"BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFET… 193 …"BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFET… 207 …"BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that have any t… 221 …"BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM suppl… 235 …"BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM suppl… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/sandybridge/
H A D	cache.json	126 …ion": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from th… 199 "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch.", 208 "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch.", 433 "BriefDescription": "Core-originated cacheable demand requests missed LLC.", 442 "BriefDescription": "Core-originated cacheable demand requests that refer to LLC.", 451 …d load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. (Precise E… 457 …-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (sa… 462 …Retired load uops which data sources were HitM responses from shared LLC. (Precise Event - PEBS).", 468 …-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (sa… 473 …d uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. (Precise … [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/jaketown/
H A D	cache.json	126 …ion": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from th… 199 "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch.", 208 "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch.", 433 "BriefDescription": "Core-originated cacheable demand requests missed LLC.", 442 "BriefDescription": "Core-originated cacheable demand requests that refer to LLC.", 451 …iption": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core c… 456 …-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (sa… 466 …his event counts retired load uops that hit in the last-level cache (L3) and were found in a non-m… 471 …n": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core … 542 …"PublicDescription": "This event counts retired load uops that hit in the last-level (L3) cache wi… [all …]

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