xref: /freebsd/lib/libpmc/pmu-events/arch/arm64/fujitsu/a64fx/other.json (revision 9d97138e2d138bcd03dc28f45e78b13c536bed84)
1*9d97138eSMitchell Horne[
2*9d97138eSMitchell Horne  {
3*9d97138eSMitchell Horne    "PublicDescription": "This event counts the occurrence count of the micro-operation split.",
4*9d97138eSMitchell Horne    "EventCode": "0x139",
5*9d97138eSMitchell Horne    "EventName": "UOP_SPLIT",
6*9d97138eSMitchell Horne    "BriefDescription": "This event counts the occurrence count of the micro-operation split."
7*9d97138eSMitchell Horne  },
8*9d97138eSMitchell Horne  {
9*9d97138eSMitchell Horne    "PublicDescription": "This event counts every cycle that no operation was committed because the oldest and uncommitted load/store/prefetch operation waits for memory access.",
10*9d97138eSMitchell Horne    "EventCode": "0x180",
11*9d97138eSMitchell Horne    "EventName": "LD_COMP_WAIT_L2_MISS",
12*9d97138eSMitchell Horne    "BriefDescription": "This event counts every cycle that no operation was committed because the oldest and uncommitted load/store/prefetch operation waits for memory access."
13*9d97138eSMitchell Horne  },
14*9d97138eSMitchell Horne  {
15*9d97138eSMitchell Horne    "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for memory access.",
16*9d97138eSMitchell Horne    "EventCode": "0x181",
17*9d97138eSMitchell Horne    "EventName": "LD_COMP_WAIT_L2_MISS_EX",
18*9d97138eSMitchell Horne    "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for memory access."
19*9d97138eSMitchell Horne  },
20*9d97138eSMitchell Horne  {
21*9d97138eSMitchell Horne    "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L2 cache access.",
22*9d97138eSMitchell Horne    "EventCode": "0x182",
23*9d97138eSMitchell Horne    "EventName": "LD_COMP_WAIT_L1_MISS",
24*9d97138eSMitchell Horne    "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L2 cache access."
25*9d97138eSMitchell Horne  },
26*9d97138eSMitchell Horne  {
27*9d97138eSMitchell Horne    "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L2 cache access.",
28*9d97138eSMitchell Horne    "EventCode": "0x183",
29*9d97138eSMitchell Horne    "EventName": "LD_COMP_WAIT_L1_MISS_EX",
30*9d97138eSMitchell Horne    "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L2 cache access."
31*9d97138eSMitchell Horne  },
32*9d97138eSMitchell Horne  {
33*9d97138eSMitchell Horne    "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L1D cache, L2 cache and memory access.",
34*9d97138eSMitchell Horne    "EventCode": "0x184",
35*9d97138eSMitchell Horne    "EventName": "LD_COMP_WAIT",
36*9d97138eSMitchell Horne    "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L1D cache, L2 cache and memory access."
37*9d97138eSMitchell Horne  },
38*9d97138eSMitchell Horne  {
39*9d97138eSMitchell Horne    "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L1D cache, L2 cache and memory access.",
40*9d97138eSMitchell Horne    "EventCode": "0x185",
41*9d97138eSMitchell Horne    "EventName": "LD_COMP_WAIT_EX",
42*9d97138eSMitchell Horne    "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L1D cache, L2 cache and memory access."
43*9d97138eSMitchell Horne  },
44*9d97138eSMitchell Horne  {
45*9d97138eSMitchell Horne    "PublicDescription": "This event counts every cycle that no instruction was committed due to the lack of an available prefetch port.",
46*9d97138eSMitchell Horne    "EventCode": "0x186",
47*9d97138eSMitchell Horne    "EventName": "LD_COMP_WAIT_PFP_BUSY",
48*9d97138eSMitchell Horne    "BriefDescription": "This event counts every cycle that no instruction was committed due to the lack of an available prefetch port."
49*9d97138eSMitchell Horne  },
50*9d97138eSMitchell Horne  {
51*9d97138eSMitchell Horne    "PublicDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by an integer load operation.",
52*9d97138eSMitchell Horne    "EventCode": "0x187",
53*9d97138eSMitchell Horne    "EventName": "LD_COMP_WAIT_PFP_BUSY_EX",
54*9d97138eSMitchell Horne    "BriefDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by an integer load operation."
55*9d97138eSMitchell Horne  },
56*9d97138eSMitchell Horne  {
57*9d97138eSMitchell Horne    "PublicDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by a software prefetch instruction.",
58*9d97138eSMitchell Horne    "EventCode": "0x188",
59*9d97138eSMitchell Horne    "EventName": "LD_COMP_WAIT_PFP_BUSY_SWPF",
60*9d97138eSMitchell Horne    "BriefDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by a software prefetch instruction."
61*9d97138eSMitchell Horne  },
62*9d97138eSMitchell Horne  {
63*9d97138eSMitchell Horne    "PublicDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is an integer or floating-point/SIMD instruction.",
64*9d97138eSMitchell Horne    "EventCode": "0x189",
65*9d97138eSMitchell Horne    "EventName": "EU_COMP_WAIT",
66*9d97138eSMitchell Horne    "BriefDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is an integer or floating-point/SIMD instruction."
67*9d97138eSMitchell Horne  },
68*9d97138eSMitchell Horne  {
69*9d97138eSMitchell Horne    "PublicDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a floating-point/SIMD instruction.",
70*9d97138eSMitchell Horne    "EventCode": "0x18A",
71*9d97138eSMitchell Horne    "EventName": "FL_COMP_WAIT",
72*9d97138eSMitchell Horne    "BriefDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a floating-point/SIMD instruction."
73*9d97138eSMitchell Horne  },
74*9d97138eSMitchell Horne  {
75*9d97138eSMitchell Horne    "PublicDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a branch instruction.",
76*9d97138eSMitchell Horne    "EventCode": "0x18B",
77*9d97138eSMitchell Horne    "EventName": "BR_COMP_WAIT",
78*9d97138eSMitchell Horne    "BriefDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a branch instruction."
79*9d97138eSMitchell Horne  },
80*9d97138eSMitchell Horne  {
81*9d97138eSMitchell Horne    "PublicDescription": "This event counts every cycle that no instruction was committed because the CSE is empty.",
82*9d97138eSMitchell Horne    "EventCode": "0x18C",
83*9d97138eSMitchell Horne    "EventName": "ROB_EMPTY",
84*9d97138eSMitchell Horne    "BriefDescription": "This event counts every cycle that no instruction was committed because the CSE is empty."
85*9d97138eSMitchell Horne  },
86*9d97138eSMitchell Horne  {
87*9d97138eSMitchell Horne    "PublicDescription": "This event counts every cycle that no instruction was committed because the CSE is empty and the store port (SP) is full.",
88*9d97138eSMitchell Horne    "EventCode": "0x18D",
89*9d97138eSMitchell Horne    "EventName": "ROB_EMPTY_STQ_BUSY",
90*9d97138eSMitchell Horne    "BriefDescription": "This event counts every cycle that no instruction was committed because the CSE is empty and the store port (SP) is full."
91*9d97138eSMitchell Horne  },
92*9d97138eSMitchell Horne  {
93*9d97138eSMitchell Horne    "PublicDescription": "This event counts every cycle that the instruction unit is halted by the WFE/WFI instruction.",
94*9d97138eSMitchell Horne    "EventCode": "0x18E",
95*9d97138eSMitchell Horne    "EventName": "WFE_WFI_CYCLE",
96*9d97138eSMitchell Horne    "BriefDescription": "This event counts every cycle that the instruction unit is halted by the WFE/WFI instruction."
97*9d97138eSMitchell Horne  },
98*9d97138eSMitchell Horne  {
99*9d97138eSMitchell Horne    "PublicDescription": "This event counts every cycle that no instruction was committed, but counts at the time when commits MOVPRFX only.",
100*9d97138eSMitchell Horne    "EventCode": "0x190",
101*9d97138eSMitchell Horne    "EventName": "_0INST_COMMIT",
102*9d97138eSMitchell Horne    "BriefDescription": "This event counts every cycle that no instruction was committed, but counts at the time when commits MOVPRFX only."
103*9d97138eSMitchell Horne  },
104*9d97138eSMitchell Horne  {
105*9d97138eSMitchell Horne    "PublicDescription": "This event counts every cycle that one instruction is committed.",
106*9d97138eSMitchell Horne    "EventCode": "0x191",
107*9d97138eSMitchell Horne    "EventName": "_1INST_COMMIT",
108*9d97138eSMitchell Horne    "BriefDescription": "This event counts every cycle that one instruction is committed."
109*9d97138eSMitchell Horne  },
110*9d97138eSMitchell Horne  {
111*9d97138eSMitchell Horne    "PublicDescription": "This event counts every cycle that two instructions are committed.",
112*9d97138eSMitchell Horne    "EventCode": "0x192",
113*9d97138eSMitchell Horne    "EventName": "_2INST_COMMIT",
114*9d97138eSMitchell Horne    "BriefDescription": "This event counts every cycle that two instructions are committed."
115*9d97138eSMitchell Horne  },
116*9d97138eSMitchell Horne  {
117*9d97138eSMitchell Horne    "PublicDescription": "This event counts every cycle that three instructions are committed.",
118*9d97138eSMitchell Horne    "EventCode": "0x193",
119*9d97138eSMitchell Horne    "EventName": "_3INST_COMMIT",
120*9d97138eSMitchell Horne    "BriefDescription": "This event counts every cycle that three instructions are committed."
121*9d97138eSMitchell Horne  },
122*9d97138eSMitchell Horne  {
123*9d97138eSMitchell Horne    "PublicDescription": "This event counts every cycle that four instructions are committed.",
124*9d97138eSMitchell Horne    "EventCode": "0x194",
125*9d97138eSMitchell Horne    "EventName": "_4INST_COMMIT",
126*9d97138eSMitchell Horne    "BriefDescription": "This event counts every cycle that four instructions are committed."
127*9d97138eSMitchell Horne  },
128*9d97138eSMitchell Horne  {
129*9d97138eSMitchell Horne    "PublicDescription": "This event counts every cycle that only any micro-operations are committed.",
130*9d97138eSMitchell Horne    "EventCode": "0x198",
131*9d97138eSMitchell Horne    "EventName": "UOP_ONLY_COMMIT",
132*9d97138eSMitchell Horne    "BriefDescription": "This event counts every cycle that only any micro-operations are committed."
133*9d97138eSMitchell Horne  },
134*9d97138eSMitchell Horne  {
135*9d97138eSMitchell Horne    "PublicDescription": "This event counts every cycle that only the MOVPRFX instruction is committed.",
136*9d97138eSMitchell Horne    "EventCode": "0x199",
137*9d97138eSMitchell Horne    "EventName": "SINGLE_MOVPRFX_COMMIT",
138*9d97138eSMitchell Horne    "BriefDescription": "This event counts every cycle that only the MOVPRFX instruction is committed."
139*9d97138eSMitchell Horne  },
140*9d97138eSMitchell Horne  {
141*9d97138eSMitchell Horne    "PublicDescription": "This event counts energy consumption per cycle of core.",
142*9d97138eSMitchell Horne    "EventCode": "0x1E0",
143*9d97138eSMitchell Horne    "EventName": "EA_CORE",
144*9d97138eSMitchell Horne    "BriefDescription": "This event counts energy consumption per cycle of core."
145*9d97138eSMitchell Horne  },
146*9d97138eSMitchell Horne  {
147*9d97138eSMitchell Horne    "PublicDescription": "This event counts streaming prefetch requests to L1D cache generated by hardware prefetcher.",
148*9d97138eSMitchell Horne    "EventCode": "0x230",
149*9d97138eSMitchell Horne    "EventName": "L1HWPF_STREAM_PF",
150*9d97138eSMitchell Horne    "BriefDescription": "This event counts streaming prefetch requests to L1D cache generated by hardware prefetcher."
151*9d97138eSMitchell Horne  },
152*9d97138eSMitchell Horne  {
153*9d97138eSMitchell Horne    "PublicDescription": "This event counts allocation type prefetch injection requests to L1D cache generated by hardware prefetcher.",
154*9d97138eSMitchell Horne    "EventCode": "0x231",
155*9d97138eSMitchell Horne    "EventName": "L1HWPF_INJ_ALLOC_PF",
156*9d97138eSMitchell Horne    "BriefDescription": "This event counts allocation type prefetch injection requests to L1D cache generated by hardware prefetcher."
157*9d97138eSMitchell Horne  },
158*9d97138eSMitchell Horne  {
159*9d97138eSMitchell Horne    "PublicDescription": "This event counts non-allocation type prefetch injection requests to L1D cache generated by hardware prefetcher.",
160*9d97138eSMitchell Horne    "EventCode": "0x232",
161*9d97138eSMitchell Horne    "EventName": "L1HWPF_INJ_NOALLOC_PF",
162*9d97138eSMitchell Horne    "BriefDescription": "This event counts non-allocation type prefetch injection requests to L1D cache generated by hardware prefetcher."
163*9d97138eSMitchell Horne  },
164*9d97138eSMitchell Horne  {
165*9d97138eSMitchell Horne    "PublicDescription": "This event counts streaming prefetch requests to L2 cache generated by hardware prefecher.",
166*9d97138eSMitchell Horne    "EventCode": "0x233",
167*9d97138eSMitchell Horne    "EventName": "L2HWPF_STREAM_PF",
168*9d97138eSMitchell Horne    "BriefDescription": "This event counts streaming prefetch requests to L2 cache generated by hardware prefecher."
169*9d97138eSMitchell Horne  },
170*9d97138eSMitchell Horne  {
171*9d97138eSMitchell Horne    "PublicDescription": "This event counts allocation type prefetch injection requests to L2 cache generated by hardware prefetcher.",
172*9d97138eSMitchell Horne    "EventCode": "0x234",
173*9d97138eSMitchell Horne    "EventName": "L2HWPF_INJ_ALLOC_PF",
174*9d97138eSMitchell Horne    "BriefDescription": "This event counts allocation type prefetch injection requests to L2 cache generated by hardware prefetcher."
175*9d97138eSMitchell Horne  },
176*9d97138eSMitchell Horne  {
177*9d97138eSMitchell Horne    "PublicDescription": "This event counts non-allocation type prefetch injection requests to L2 cache generated by hardware prefetcher.",
178*9d97138eSMitchell Horne    "EventCode": "0x235",
179*9d97138eSMitchell Horne    "EventName": "L2HWPF_INJ_NOALLOC_PF",
180*9d97138eSMitchell Horne    "BriefDescription": "This event counts non-allocation type prefetch injection requests to L2 cache generated by hardware prefetcher."
181*9d97138eSMitchell Horne  },
182*9d97138eSMitchell Horne  {
183*9d97138eSMitchell Horne    "PublicDescription": "This event counts prefetch requests to L2 cache generated by the other causes.",
184*9d97138eSMitchell Horne    "EventCode": "0x236",
185*9d97138eSMitchell Horne    "EventName": "L2HWPF_OTHER",
186*9d97138eSMitchell Horne    "BriefDescription": "This event counts prefetch requests to L2 cache generated by the other causes."
187*9d97138eSMitchell Horne  }
188*9d97138eSMitchell Horne]
189