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/freebsd/lib/libpmc/pmu-events/arch/x86/ivybridge/
H A D	uncore.json	7 "BriefDescription": "A snoop misses in some processor core.", 8 "PublicDescription": "A snoop misses in some processor core.", 19 "BriefDescription": "A snoop invalidates a non-modified line in some processor core.", 20 "PublicDescription": "A snoop invalidates a non-modified line in some processor core.", 31 "BriefDescription": "A snoop hits a non-modified line in some processor core.", 32 "PublicDescription": "A snoop hits a non-modified line in some processor core.", 43 "BriefDescription": "A snoop hits a modified line in some processor core.", 44 "PublicDescription": "A snoop hits a modified line in some processor core.", 55 "BriefDescription": "A snoop invalidates a modified line in some processor core.", 56 "PublicDescription": "A snoop invalidates a modified line in some processor core.", [all …]
H A D	uncore-cache.json	3 … "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.", 8 … "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.", 13 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state.", 18 "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.", 23 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state.", 28 "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.", 33 "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.", 38 … "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.", 43 …Description": "L3 Lookup external snoop request that access cache and found line in E or S-state.", 48 …Description": "L3 Lookup external snoop request that access cache and found line in E or S-state.", [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/sandybridge/
H A D	uncore.json	7 "BriefDescription": "A snoop misses in some processor core.", 8 "PublicDescription": "A snoop misses in some processor core.", 19 "BriefDescription": "A snoop invalidates a non-modified line in some processor core.", 20 "PublicDescription": "A snoop invalidates a non-modified line in some processor core.", 31 "BriefDescription": "A snoop hits a non-modified line in some processor core.", 32 "PublicDescription": "A snoop hits a non-modified line in some processor core.", 43 "BriefDescription": "A snoop hits a modified line in some processor core.", 44 "PublicDescription": "A snoop hits a modified line in some processor core.", 55 "BriefDescription": "A snoop invalidates a modified line in some processor core.", 56 "PublicDescription": "A snoop invalidates a modified line in some processor core.", [all …]
H A D	uncore-cache.json	3 … "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.", 8 … "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.", 13 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state.", 18 "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.", 23 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state.", 28 "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.", 33 "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.", 38 … "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.", 43 …Description": "L3 Lookup external snoop request that access cache and found line in E or S-state.", 48 …Description": "L3 Lookup external snoop request that access cache and found line in E or S-state.", [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/haswell/
H A D	uncore.json	7 "BriefDescription": "An external snoop misses in some processor core.", 8 "PublicDescription": "An external snoop misses in some processor core.", 19 …fDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request whi… 20 …cDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request whi… 31 …"BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor c… 32 …"PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor … 43 "BriefDescription": "An external snoop hits a non-modified line in some processor core.", 44 "PublicDescription": "An external snoop hits a non-modified line in some processor core.", 55 …ion": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a… 56 …ion": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a… [all …]
H A D	uncore-cache.json	3 … "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.", 8 … "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.", 13 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state.", 18 "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.", 23 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state.", 28 "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.", 33 "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.", 38 … "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.", 43 …Description": "L3 Lookup external snoop request that access cache and found line in E or S-state.", 48 …Description": "L3 Lookup external snoop request that access cache and found line in E or S-state.", [all …]
H A D	uncore-other.json	12 …"BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture,… 17 …"PublicDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture… 22 …Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI… 26 …Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI… 31 … waiting for data return from memory controller. Account for coherent and non-coherent requests in… 41 …"BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and no… 46 …"PublicDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and n… 51 …"BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and… 56 …"PublicDescription": "Number of Writes allocated - any write transactions: full/partials writes an… 61 "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.", [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/skylake/
H A D	uncore.json	7 …fDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request whi… 8 …cDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request whi… 19 …"BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor c… 20 …"PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor … 31 …ion": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a… 32 …ion": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a… 43 …ption": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits… 44 …ption": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits… 55 "BriefDescription": "L3 Lookup write request that access cache and found line in M-state", 56 "PublicDescription": "L3 Lookup write request that access cache and found line in M-state.", [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/broadwell/
H A D	uncore.json	7 …fDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request whi… 8 …cDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request whi… 19 …"BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor c… 20 …"PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor … 31 …ion": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a… 32 …ion": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a… 43 …ption": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits… 44 …ption": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits… 55 "BriefDescription": "L3 Lookup read request that access cache and found line in M-state", 56 "PublicDescription": "L3 Lookup read request that access cache and found line in M-state.", [all …]
/freebsd/sys/dev/bhnd/
H A D	bhnd_erom_if.m	1 #- 2 # Copyright (c) 2016-2017 Landon Fuller <landon@landonf.org> 61 * the first bus core. 62 * @param base_addr Address of the first bus core. 65 * within the first core, this parameter should be 94 * @retval non-zero if an error occurs initializing the EROM parser, 121 * @param[out] cores The table of parsed core descriptors. 122 * @param[out] num_cores The number of core records in @p cores. 125 * @retval non-zero if an error occurs, a regular unix error code will 138 * @param cores A core table allocated by @p erom. [all …]
H A D	bhnd_erom.h	1 /- 2 SPDX-License-Identifier: BSD-2-Clause 4 * Copyright (c) 2015-2017 Landon Fuller <landonf@FreeBSD.org> 127 * first bus core. 130 * registers within the first core, this parameter should 158 * @param[out] cores The table of parsed core descriptors. 159 * @param[out] num_cores The number of core records in @p cores. 162 * @retval non-zero if an error occurs, a regular unix error code will 176 * @param cores A core table allocated by @p erom. 185 * Locate the first core table entry in @p erom that matches @p desc. [all …]
/freebsd/sys/dev/bhnd/bcma/
H A D	bcma_erom.c	1 /- 2 SPDX-License-Identifier: BSD-2-Clause 4 * Copyright (c) 2015-2017 Landon Fuller <landonf@landonf.org> 53 * Provides auto-discovery of BCMA cores on Broadcom's HND SoC. 55 * The EROM core address can be found at BCMA_CC_EROM_ADDR within the 56 * ChipCommon registers. The table itself is comprised of 32-bit 57 * type-tagged entries, organized into an array of variable-length 58 * core descriptor records. 60 * The final core descriptor is followed by a 32-bit BCMA_EROM_TABLE_EOF (0xF) 89 struct bhnd_core_info *core); [all …]
/freebsd/sys/dev/bhnd/bhndb/
H A D	bhndb_if.m	1 #- 2 # Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 71 struct bhnd_core_info core) 78 struct bhnd_core_info core) 122 * @param child The bhndb-attached device. 134 * @param child The bhndb-attached device. 145 * Return true if the hardware required by @p core is unpopulated or 148 * In some cases, the core's pins may be left floating, or the hardware 149 * may otherwise be non-functional; this method allows the parent device 150 * to explicitly specify whether @p core should be disabled. [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/amdzen3/
H A D	cache.json	5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har… 11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.", 17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.", 23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.", 29 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request… 35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.", 41 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches a… 64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.", 70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab… 76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.", [all …]
/freebsd/lib/libpmc/
H A D	pmc.haswelluc.3	45 .Bl -tag -width "Li PMC_CLASS_UCP" 47 Fixed-function counters that count only one hardware event per counter. 59 .%B "Intel(R) 64 and IA-32 Architectures Software Developers Manual" 61 .%N "Order Number: 325462-045US" 68 Not all CPUs in this family implement fixed-function counters. 71 .Bl -column "PMC_CAP_INTERRUPT" "Support" 88 .Bl -tag -width indent 94 Configure the PMC to count the number of de-asserted to asserted 109 .Bl -tag -width indent 112 A snoop misses in some processor core. [all …]
/freebsd/sys/contrib/device-tree/Bindings/usb/
H A D	dwc3.txt	1 synopsys DWC3 CORE 3 DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties 7 - compatible: must be "snps,dwc3" 8 - reg : Address and length of the register set for the device 9 - interrupts: Interrupts used by the dwc3 controller. 10 - clock-names: list of clock names. Ideally should be "ref", 12 - clocks: list of phandle and clock specifier pairs corresponding to 13 entries in the clock-names property. 16 clocks are optional if the parent node (i.e. glue-layer) is compatible to 18 "cavium,octeon-7130-usb-uctl" [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/amdzen1/
H A D	cache.json	5 …etch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cachea… 35 … instruction stream was being modified by another processor in an MP system - typically a highly u… 52 …l. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.", 58 …ache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other threa… 64 …ache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other threa… 75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har… 81 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.", 87 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.", 93 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.", 99 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/tigerlake/
H A D	other.json	3 …"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped… 9 …Core cycles where the core was running with power-delivery for baseline license level 0. This inc… 14 …"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped… 20 …Core cycles where the core was running with power-delivery for license level 1. This includes hig… 25 …"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped… 31 …Core cycles where the core was running with power-delivery for license level 2 (introduced in Skyl…
/freebsd/lib/libpmc/pmu-events/arch/x86/tremontx/
H A D	cache.json	3 …"BriefDescription": "Counts the number of core requests (demand and L1 prefetchers) rejected by th… 10 …core requests rejected by the L2 queue (L2Q) due to a full or nearly full condition, which likely … 33 … The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L… 37 … "BriefDescription": "Counts the total number of L2 Cache accesses. Counts on a per core basis.", 44 …ejects front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only. Counts on a per core basis.", 48 …ion": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a per core basis.", 55 …rom a front door request only (does not include rejects or recycles), Counts on a per core basis.", 60 …on": "Counts the number of L2 Cache accesses that resulted in a miss. Counts on a per core basis.", 67 …rom a front door request only (does not include rejects or recycles). Counts on a per core basis.", 72 …ts the number of L2 Cache accesses that miss the L2 and get rejected. Counts on a per core basis.", [all …]
/freebsd/sys/contrib/dev/acpica/
H A D	changes.txt	1 ---------------------------------------- 6 Fix 2 critical CVE addressing memory leaks - Seunghun Han 17 ---------------------------------------- 30 ---------------------------------------- 35 …that the PHAT firmware health record offset works correctly, fix various sub-table offsets, preven… 37 Fix the optional table 4-byte signature. Contributed by: Daniil Tatianin <99danilt@gmail.com> 56 ---------------------------------------- 71 Add new tables for various architectures/OS, mainly RISC-V and also update many more. 73 Add an option to either make the output deterministic or non-deterministic. 80 ---------------------------------------- [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/amdzen2/
H A D	cache.json	5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har… 11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.", 17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.", 23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.", 29 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request… 35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.", 41 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches a… 64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.", 70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab… 76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.", [all …]
/freebsd/contrib/llvm-project/clang/lib/StaticAnalyzer/Checkers/
H A D	TrustNonnullChecker.cpp	1 //== TrustNonnullChecker.cpp --------- API nullability modeling -- C++ ---==// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 // This checker adds nullability-related assumptions: 12 // which come from system headers actually return a non-null pointer. 14 // 2. NSDictionary key is non-null after the keyword subscript operation 15 // on read if and only if the resulting expression is non-null. 17 // 3. NSMutableDictionary index is non-null after a write operation. 19 //===----------------------------------------------------------------------===// 23 #include "clang/StaticAnalyzer/Core/Checker.h" [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/skylakex/
H A D	other.json	3 …"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped… 8 …Core cycles where the core was running with power-delivery for baseline license level 0. This inc… 13 …"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped… 18 …Core cycles where the core was running with power-delivery for license level 1. This includes hig… 23 …"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped… 28 …Core cycles where the core was running with power-delivery for license level 2 (introduced in Skyl… 33 … "BriefDescription": "Core cycles the core was throttled due to a pending power level request.", 38 …"PublicDescription": "Core cycles the out-of-order engine was throttled due to a pending power lev…
/freebsd/lib/libpmc/pmu-events/arch/x86/icelakex/
H A D	cache.json	9 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 59 …non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined u… 102 …"BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered… 108 …y an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.", 132 …from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are … 216 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", 228 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.", 270 …"BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetche… 276 …": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requ… 282 …"BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetch… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/elkhartlake/
H A D	cache.json	15 …"Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.", 22 …s an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.", 27 … "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.", 34 …s an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.", 39 …"Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit… 46 …ber of cycles a core is stalled due to an instruction cache or translation lookaside buffer (TLB) … 51 …"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache o… 58 …"PublicDescription": "Counts the number of cycles a core is stalled due to an instruction cache or… 63 …ounts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit i… 70 …es a core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) access whic… [all …]

12 3 4 5 6 7 8 9 10 >>...65