1*52d973f5SAlexander Motin[ 2*52d973f5SAlexander Motin { 3*52d973f5SAlexander Motin "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.", 4*52d973f5SAlexander Motin "CollectPEBSRecord": "2", 5*52d973f5SAlexander Motin "Counter": "0,1,2,3", 6*52d973f5SAlexander Motin "EventCode": "0x28", 7*52d973f5SAlexander Motin "EventName": "CORE_POWER.LVL0_TURBO_LICENSE", 8*52d973f5SAlexander Motin "PEBScounters": "0,1,2,3", 9*52d973f5SAlexander Motin "PublicDescription": "Counts Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.", 10*52d973f5SAlexander Motin "SampleAfterValue": "200003", 11*52d973f5SAlexander Motin "UMask": "0x7" 12*52d973f5SAlexander Motin }, 13*52d973f5SAlexander Motin { 14*52d973f5SAlexander Motin "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.", 15*52d973f5SAlexander Motin "CollectPEBSRecord": "2", 16*52d973f5SAlexander Motin "Counter": "0,1,2,3", 17*52d973f5SAlexander Motin "EventCode": "0x28", 18*52d973f5SAlexander Motin "EventName": "CORE_POWER.LVL1_TURBO_LICENSE", 19*52d973f5SAlexander Motin "PEBScounters": "0,1,2,3", 20*52d973f5SAlexander Motin "PublicDescription": "Counts Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.", 21*52d973f5SAlexander Motin "SampleAfterValue": "200003", 22*52d973f5SAlexander Motin "UMask": "0x18" 23*52d973f5SAlexander Motin }, 24*52d973f5SAlexander Motin { 25*52d973f5SAlexander Motin "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.", 26*52d973f5SAlexander Motin "CollectPEBSRecord": "2", 27*52d973f5SAlexander Motin "Counter": "0,1,2,3", 28*52d973f5SAlexander Motin "EventCode": "0x28", 29*52d973f5SAlexander Motin "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", 30*52d973f5SAlexander Motin "PEBScounters": "0,1,2,3", 31*52d973f5SAlexander Motin "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture). This includes high current AVX 512-bit instructions.", 32*52d973f5SAlexander Motin "SampleAfterValue": "200003", 33*52d973f5SAlexander Motin "UMask": "0x20" 34*52d973f5SAlexander Motin }, 35*52d973f5SAlexander Motin { 36*52d973f5SAlexander Motin "BriefDescription": "Counts streaming stores that have any type of response.", 37*52d973f5SAlexander Motin "CollectPEBSRecord": "2", 38*52d973f5SAlexander Motin "Counter": "0,1,2,3", 39*52d973f5SAlexander Motin "EventCode": "0xB7, 0xBB", 40*52d973f5SAlexander Motin "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", 41*52d973f5SAlexander Motin "MSRIndex": "0x1a6,0x1a7", 42*52d973f5SAlexander Motin "MSRValue": "0x10800", 43*52d973f5SAlexander Motin "Offcore": "1", 44*52d973f5SAlexander Motin "PEBScounters": "0,1,2,3", 45*52d973f5SAlexander Motin "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 46*52d973f5SAlexander Motin "SampleAfterValue": "100003", 47*52d973f5SAlexander Motin "UMask": "0x1" 48*52d973f5SAlexander Motin } 49*52d973f5SAlexander Motin] 50